SGS Thomson Microelectronics ST19SF02 Datasheet
■ ENHANCED 8 BIT CPU WITH EXTENDED
ADDRESSING MODES
■ 32 K BYTES OF USER ROM WITH
PARTITIONING
■ SYSTEM ROM
■ 960 BYTES OF USER RAM WITH
PARTITIONING
■ 2 K BYTES OF USER EEPROM WITH
PARTITIONING
– Highly reliable CMOS EEPROM submicron
technology
– 10 years data retention
– 100,000 Erase/Write cycles endurance
– Separate Write and Erase cycles for fast "1"
programming
– 1 to 32 bytes Erase or Program
■ SECURITY FIREWALLS FOR MEMORIES
■ VERY HIGH SECURITY FEATURES
INCLUDING EEPROM FLASH PROGRAM
■ 8 BIT TIMER WITH INTERRUPT CAPABILITY
■ 2 SERIAL ACCESS, ISO 7816-3 COMPATIBLE
■ 3V ± 10% or 5V ± 10% S UP PLY VOLT AG E
■ POWER SAVING STANDBY MODE
■ CONTACT ASSIGNMENT COMPATIBLE ISO
7816-2
■ ESD PROTECTION GRE ATE R THA N 5000V
ST19SF02
Smar tcard MC U
With 2 KBytes of EEPROM
DATA BRIEFING
4
4
Micromodule (D4)
4
4
Wafer
October 1999
This is Brief Data from STMicroelectronics. Details are subject to change without notice. For complete data, please contact
your nearest Sales Office or SmartCard Products Divison, Rousset, France. Fax: (+33) 4 42 25 87 29
1/2
ST19SF02
HARDWARE DESCRIPTION
The ST19SF02, a member of the ST19 device
family, is a serial access microcontroller especially
designed for very large volume and cost competitive secure portable objects.
The ST19SF02 i s based on a STMicr oelectronics
8 bit CPU core including on-chip memories: 960
Bytes of RAM, 32 K Bytes of USER ROM and 2 K
Bytes of EEPROM.
RAM, ROM and EEPROM memories can be configured into partitions. Access rules from any
memory partition to another partition are s etup by
the user defined Memory Access Control Logic.
Figure 1. Blo ck di a gram
It is manufactured using the highly reliable ST
technology.
As all o ther ST19 f am ily m emb ers, it is fully co mpatible with the ISO standards for Smartcard applications.
SOFTWARE DESCRIPTION
Software development and firmware (ROM code/
options) generation are completed by the ST16-19
HDSE development system.
RAM EEPROM
960
BYTES
CLOCK
GENERATOR
MODULE
CLK
BYTES
MEMORY ACCESS FIREWALL
8 BIT
TIMER
2 K
SECURITY
ADMINISTRATOR
USER
ROM
32 K
BYTES
INTERNAL BUS
RESET
UNPREDICTABLE
NUMBER
GENERATOR
SYSTEM ROM
SYSTEM ROM
FIREWALL
8 BIT
CPU
SERIAL
I/O
INTERFACE
I/OGNDVcc
SCP 101b/DS
2/2
Loading...