SGS Thomson Microelectronics ST19GF34 Datasheet

ST19GF34 FEATURES:

■ ENHANCED 8 BIT CPU WITH EXTENDED

ADDRESSING MODES

■ USER ROM WITH PARTITIONING

■ 56 K BYTES OF SYSTEM ROM

■ 1984BYTES OF USER RAM WITH

PARTITIONING

■ 34 K BYTES OF USER EEPROM WITH

PARTITIONING

– Highly reliable CMOS EEPROM submicron

technology
– 10 years data retention
– 100,000 Erase/Write cycles endurance
– Separate Write and Erase cycles for fast "1"

programming
– 1 to 64 bytes Erase or Program
– Full support of GSM Toolkit and Javacard im-

plementation

■ SECURITY FIREWALLS FOR MEMORIES

■ VERY HIGH SECURITY FEATURES

INCLUDING EEPROM FLASH PROGRAM

■ 8 BIT TIMER WITH INTERRUPT CAPABILITY

■ 2 SERIAL ACCESS, ISO 7816-3 COMPATIBLE

■ 3V ± 10% or 5V ± 10% SUPPLY VOLTAGE

■ POWER SAVING STANDBY MODE

■ CONTACT ASSIGNMENT COMPATIBLE ISO

7816-2

■ ESD PROTECTION GRE ATE R THA N 5000V

ST19GF34

Smartcard MC U

With 34 KBytes EEPROM

DATA BRIEFING

4

4

Micromodule (D4)

4

4

Wafer

October 1999

This is Brief Data from STMicroelectronics. Details are subject to change without notice. For complete data, please contact
your nearest Sales Office or SmartCard Products Divison, Rousset, France. Fax: [phone]

1/2

ST19GF34

HARDWARE DESCRIPTION

The ST19GF34, a member of the ST19 device
family, is a serial access microcontroller especially
designed for very large volume and cost competi­tive secure portable objects.

The ST19GF34 i s based on a STMicroelectronics
8 bit CPU core including on-chip memories: 1984
Bytes of RAM, 56 K B ytes of USER ROM and 34
K Bytes of EEPROM.

RAM, ROM and EEPROM memories can be con­figured into partitions. Access rules from any
memory partition to another partition are s etup by
the user defined Memory Access Control Logic.

It is manufactured using the highly reliable ST
technology.

As all o ther ST19 f am ily m emb ers, it is fully co m­patible with the ISO standards for Smartcard appli­cations.

SOFTWARE DESCRIPTION

Software development and firmware (ROM code/
options) generation are completed by the ST16-19
HDSE development system.

Figure 1. Block Diagram

RAM EEPROM

1984

Bytes

CLOCK
GENERA­TOR
MODULE

USER

34 K

Bytes

MEMORY ACCESS FIREWALL

8 BIT
TIMER

SECURITY

ADMINISTRATOR

ROM

56 K

Bytes

INTERNAL BUS

UNPRE­DICTABLE
NUMBER
GENERATOR

SYSTEM ROM

SYSTEM ROM
FIREWALL

8 BIT
CPU

SERIAL
I/O
INTER­FACE

2/2

CLK

RESET

I/OGNDVcc

SCP 101b/DS