SGS Thomson Microelectronics ST10R172LT1, ST10R172L Datasheet

16-BIT LOW VOLTAGE ROMLESS MCU

■ High Performance 16-bit CPU

● CPU Frequency: 0 to 50 MHz

● 40ns instruction cycle time at 50-MHz CPU

clock

● 4-stage pipeline

● Register-based des ign with multiple

variable register banks

● Enhanc ed bool ean bit manip ulation

facilities

● Additional instructions to support HLL and

operating systems

● Single-cycle context switching support

● 1024 bytes on-Chip special func tion

■ Memory Organisation

● 1KByte on-chip RAM

● Up to 16 MBytes linear address space for

code and data (1 MByte with SSP used)

■ External Memory Interface

● Programmable external bus characteristics

for different address ranges

● 8-bit or 16-bit external data bus

● Mu ltiplexed or demultiplexed external

address/data buses

● Five programmable chip-select signals

● Hold and hold-acknowledge bus arbitration

support

■ One Channel PWM Unit

■ Fail Safe Protection

● Programmable watchdog timer

● Oscill ator Watchdog

■ Interrupt

● 8-channel interrupt-driven single-cycle data

transfer facilities via peripheral event controller (PEC)

● 16-pr iority-level interrupt system with 17

sources, sample-rate down to 40 ns

■ Timers

ST10R172L

PRODUCT PREVIEW

Dedicated

pins

OSC

● Two multi-functional general purpose timer

units with 5 timers

● Clock Generation via on-chip PLL, or via

direct or prescaled clock input

■ Serial Channels

● Sy nchronous/asynchronous

● Hi gh-speed-sy nchronous serial port SSP

■ Up to 77 general purpose I/O lines

■ No bootstrap loader

■ Electrical Characteristics

● 5V Tolerant I/Os

● 5V Fail-Safe Inputs (Port 5)

● Power: 3.3 Volt +/-0.3V

● Idle and power down modes

■ Support

● C-com pilers, macro-assembler packages,

emulators, evaluation boards, HLLdebuggers, simulators, logic analyser disassemblers, programming boards

■ Package

● 1 00-P in Thin Quad Flat Pack (TQFP)

P.6

WDT

PLL

DPRAM

Inte rru p t C o n tro lle r

ASC GPT1/2

P.3

P.4

XSSP

ST10 CORE

&PEC

PWM

P.5

P.1 P.0

P.7

Po.2

Rev. 1.1

April 2000 1/68

This is preliminary information on a new product now in development. Details are subject to change without notice.

Table of Contents

1 PIN DESCRIPTIO N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 MEMORY MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 INTERRUPT AND TRAP FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1 INTERRUPT SOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2 HARDWARE TRAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 PARALLEL P ORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 EXTERNAL BUS CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8 PWM MODUL E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

9 GENERAL PU RPOSE TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

9.1 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

9.2 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

10 SERIAL CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

11 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

12 SYSTEM RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

13 POWER REDUCTION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

14 SPECIAL FUNCTION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

15 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

15.1 ABSOLUTE MAXIMUM RAT INGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

15.2 DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

15.3 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

15.3.1 Cpu Clock Generation Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

15.3.2 Memory Cycle Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

15.3.3 Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

15.3.4 Demultiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2/68

Table of Contents

15.3.5 CLKOUT and READY/READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

15.3.6 External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

15.3.7 External Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

15.3.8 Synchronous Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

16 PACKAGE MECHANICAL DAT A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

17 ORDERING IN FORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3/68

4/68

P3.12/BHE/WRH

P3.15/CLKOUT

P 3 .1 /T 6 OUT

P 3 .3 /T 3 OUT

P 3 .4 /T 3 EUD

P3.11/RxD0

P 4 .0 /A16

P 4 .1 /A17

P 4 .2 /A18

Figure 1 TQFP-100 pin con figuration (top view)

P4.3/A19

WR/W RL

ALE

V V

RPD

P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7

V V

DD SS

P4.4/A20/SSPCE1 P4.5/A21/SSPCE0 P4.6/A22/SSPDAT P4.7/A23/SSPCLK

READY/READY

26 2728 293031 323334 3536 373839 404142434445464748 4950

P3.10/TxD0

P3.13

P 3 .6 /T 3 IN

P 3 .7 /T 2 IN

P3.8

P3.9

ST10R 172L

P3.2/CAPIN

P 3 .5 /T 4 IN

XTAL2

P3.0

P5.14/T4EUD

P5.15/T2EUD

P 5 .1 3 /T 5IN

XTAL1

100999897969594939291908988878685848382818079787776

P5.12/T6IN P5.11/T5EUD P5.10/T6EUD P7.3/POUT3 P7.2 P7.1 P7.0 P2.11/EX3IN P2.10/EX2IN P2.9/EX1IN P2.8/EX0IN P6.7/BREQ P6.6/HLDA P6.5/HOLD P6.4/CS4 P6.3/CS3 P6.2/CS2 P6.1/CS1 P6.0/CS0 NMI RSTOUT RSTIN V

P1H.7/A15

1 PIN DESCRIPTION

ST10R172L - PIN DESCR IPTION

P0H.0/AD8

SSVDD

P1H.6/A14

P1H.5/A13

P1H.4/A12

P1H.3/A11

P1H.2/A10

P1H.1/A9

P1H.0/A8

P1L.7/A7

P1L.6/A6

P1L.5/A5

P1L.4/A4

P1L.3/A3

P1L.2/A2

P1L.1/A1

P1L.0/A0

P0H.7/AD15

P0H.6/AD14

P0H.5/AD13

P0H.4/AD12

P0H.3/AD11

P0H.2/AD10

P0H.1/AD9

ST10R172L - PIN DESCR IPTION

Symbol

P5.10

–P5.15

XTAL1

XTAL2

Pin Number

(TQFP)

98-100 1- 3

Input (I)

Output (O)

Kind

Function

I I

5S5S6-bit input-only port with Schmitt-Trigger characteristics.

Port 5 pins also serve as timer inputs:

98 I 5S P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down

Ctrl.Input

99 I 5S P5.11 T5EUD GPT2 Timer T5 Ext.Up/Down

Ctrl.Input 100 I 5S P5.12 T6IN GPT2 Timer T6 Count Input 1 I 5S P5.13 T5IN GPT2 Timer T5 Count Input 2 I 5S P5.1 4 T4 EUD GPT1 Timer T4 Ex t. Up / Down

Ctrl.Input 3 I 5S P5.1 5 T2 EUD GPT1 Timer T2 Ex t. Up / Down

Ctrl.Input 5 I 3T X TAL1: Input to the oscillator amplifier and internal clock

generator

6 O 3T XTAL2: Output of the oscillator amplifier circuit.

To clock the device from an external source, drive XTA L1, while leaving XTAL2 unconnected. Observe minimum and maximum high/low and rise/fall times specified in the AC Characteristics.

Table 1 Pin definitions

5/68

ST10R172L - PIN DESCR IPTION

Symbol

P3.0 – P3.13

P3.15

Pin Number

(TQFP)

8-21

Input (I)

I/O

Output (O)

Kind

Function

5T 5TA 15-bit (P3.14 is missing) bidirectional I/O port. Port 3 is bit-

wise programmable for input or output via direction bits. For a

I/O

pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/ pull or open drain drivers. The following pins have alternate

functions: 9 O 5T P3.1 T6OUT GPT2 Timer T6 toggle latch output 10 I 5T P3. 2 CAPIN GPT2 Register CAPREL capture

input 11 O 5T P3.3 T3OUT GPT1 Timer T3 toggle latch output 12 I 5T P3. 4 T3EUD GPT1 Timer T3 ext.up/down ctrl.input 13 I 5T P3. 5 T4IN GPT1 Timer T4 input for count/gate/

reload/capture 14 I 5T P 3.6 T3IN GPT1 Timer T3 count/ gate input 15 I 5T P3. 7 T2IN GPT1 Timer T2 input for count/gate/

reload/capture

6/68

18 O 5T P3.10 TxD0 ASC0 clock/data output (asyn./syn.) 19 I/O 5T P3. 11 RxD0 ASC0 data input (asyn.) or I/O (syn.) 20 O 5T P3.12 BHE

O5T WRH

Ext. Memory High Byte Enable Signal

Ext. Memory High Byte Write Strobe 22 O 5T P3.15 CLKOUT System clock output (=CPU clock)

Table 1 Pin definitions

ST10R172L - PIN DESCR IPTION

Symbol

P4.0– P4.7

Pin Number

(TQFP)

23-26 29-32-

Input (I)

Output (O)

Kind

Function

I/O 5T An 8-bit bidirectional I/O port. Port 8 is bit-wise programmable

for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 4 can be used to output the segment address lines for

external bus configuration. 23 O 5T P4.0 A16 Least Significant Segment Addr. Line

... ... ... ... ... ...

26 O 5T P4.3 A19 Segment Address Line 29 O 5T P4.4 A20 Segment Address Line

O 5T SSPCE1 Chip Enable Line 1

30 O 5T P4.5 A21 Segment Address Line

O 5T SSPCE0 SSPChip Enable Line 0

31 O 5T P4.6 A22 Segment Address Line

I/O 5T SSPDAT SSP Data Input/O utpu t Line

WR/ WRL

READY/ READY

32 O 5T P4.7 A23 Most Significant Segment Addr. Line

O 5T SSPCLK SSP Clock Output Line

33 O 5T External Memory Read Strobe. RD is activated for every exter-

nal instruction or data read access. 34 O 5T External Memory Write Strobe. In WR-mode, this pin is acti-

vated for every external data write access. In WRL-mode, this

pin is activated for low byte data write accesses on a 16-bit

bus, and for every data write access on an 8-bit bus.

See WRCFG in the SYSCON register for mode selection. 35 I 5T Ready Input. Active level is programmable. When the Ready

function is enabled, the selected inactive level at this pin dur-

ing an external memory access will f orce t he insertion of mem-

ory cycle time waitstates until the pin returns to the selected

active level. Polarity is pro gram mable.

Table 1 Pin definitions

7/68

ST10R172L - PIN DESCR IPTION

Symbol

Pin Number

(TQFP)

Input (I)

Output (O)

Kind

Function

ALE 36 O 5T Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the multi-

plexed bus modes.

37 I 5T E xt ernal Access Enable pin. Low level at this pin during and

after reset forces the ST10R172L to begin instruction execu-

tion out of external memory. A high level forces execution out

of the internal ROM. The ST10R172L must have this pin tied

to ‘0’.

PORT0: P0L.0–

P0L.7, P0H.0 -

P0H.7

41 - 48

51 - 58

I/O 5T PORT0 has two 8-bit bidirectional I/O ports P0L and P0H. It is

bit-wise programmable for input or output via direction bits. For

a pin configured as input, the output driver is put into high-

impedance state.

For exter nal bus configuration, PORT0 acts as address (A)

and address/data (AD) bus in multiplexed bus modes and as

the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 - D7 P0H.0 – P0H.7: I/O D8 - D15

PORT1: P1L.0–

P1L.7, P1H.0 -

P1H.7

8/68

59- 66

67, 68 71-76

Multiplexed bus modes

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7 P0H.0 – P0H.7: A8 – A15 AD8 – AD15

I/O 5T PORT1 has two 8-bit bidirectional I/O ports P1L and P1H. It is

bit-wise programmable for input or output via direction bits. For

a pin configured as input, the output driver is put into high-

impedance state. PORT1 acts as a 16-bit address bus (A) in

demultiplexed bus modes and also after switching from a

demultiplexed bus mode to a multiplexed bus mode.

Table 1 Pin definitions

ST10R172L - PIN DESCR IPTION

Symbol

Pin Number

(TQFP)

Input (I)

Output (O)

Kind

Function

RSTIN 79 I 5T Reset Input with Schmitt-Trigger characteristics. Resets the

device when a low level is applied for a specified duration while

the oscillator is running. An internal pullup resi stor enables

power-on reset using only a capacitor connected to

a bonding option, the RSTIN

pin can also be pulled-down for

. With

512 internal clock cycles for hardware, software or watchdog

timer triggered resets

RSTOUT

80 O 5T Internal Reset Indication Output. This pin is set to a low level

when the part is executes hardware-, software- or watchdog

timer reset. RSTOUT

remains low until the EINIT (end of ini-

tialization) instruction is executed.

NMI

81 I 5S Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine.

P6.0P6.7

If it is not used, NMI 82-89 I/O 5T An 8-bit bidirectional I/O port. Port 6 is bit-wise programmable

for input or output via direction bits. For a pin configured as

should be pulled high externally.

input, the output driver is put into high-impedance state. Port 6

outputs can be configured as push/pull or open drain drivers.

The following Port 6 pins have alternate functions: 82 O 5T P6.0 CS0

Chip Select 0 Output

... ... ... ... ... ...

86 O 5T P6.4 CS4 87 I 5T P 6. 5 HOL D

Chip Select 4 Output

External Master Hold Request Input

(Master mode: O, Slave mode: I) 88 I/O 5T P6.6 HLDA 89 O 5T P6.7 BRE Q

Hold Acknowledge Output

Bus Request Output

Table 1 Pin definitions

9/68

ST10R172L - PIN DESCR IPTION

Symbol

P2.8 – P2.11

Pin Number

(TQFP)

Input (I)

Output (O)

Kind

Function

90 - 93 I/O 5T Por t 2 is a 4-bit bidirectional I/O port. It is bit-wise programma-

ble for input or output via di rection bits. For a pin configured as input, the output driver is put into high-impedance state. Port 2 outputs can be configured as push/pull or open drain drivers.

The following Port 2 pins have alternate functions: 90 I 5T P 2.8 EX0IN Fast External Interrupt 0 Input

... ... ... ... ... ...

93 I 5T P 2.11 EX 3IN Fast Externa l Interrupt 3 Input

P7.0 – P7.3

94 - 97 I/O 5T Por t 7 is a 4-bit bidirectional I/O port. It is bit-wise programma-

ble for input or output via di rection bits. For a pin configured as

input, the output driver is put into high-impedance state. Port

7outputs can be configured as push/pull or open drain drivers.

The following Port 7 pins have alternate functions: 97 O 5T P7.3 POUT3 PWM (Channel 3) Output

RPD 40 I/O 5T Input timing pin for the return from powerdown circuit and

power-up asynchronous reset.

7, 28,

- PO Di gital supply voltage. 38, 49, 69, 78

4, 27,

- PO Di gital ground. 39, 50, 70, 77

Table 1 Pin definitions

1) The following I/O kinds are used. Refer to

page 31 for a detailed description. PO: Power pin 3T: 3 V tolerant pin (voltage max. respect to Vss is -0.5 to VDD + 0.5) 5V: 5 V tolerant pin (voltage max. respect to Vss is -0.5 to 5.5 only if chip is powered) 5S: 5 V tolerant and f ail-safe pin (-0.5-5.5 ma x. voltage w.r.t. Vss ev en if chip is n ot pow-

ered).

10/68

ELECTRICAL CHARACTERISTICS

ST10R172L - FUNCTIONAL DESCRIPTION

2 FUNCTIONAL DESCRIPTION

ST10R172L architecture combines the advantages of both RISC and CISC processors wi th an advanced peripheral subsystem. The following block diagram overviews the different onchip components and the internal bus structure.

XTAL1

XTAL2

EA, ALE, RD, WR/WRL, READY, NMI, RSTIN, RSTOUT

dedicated

pins

OSC

DPRAM

I/O

CS(4:0)

HOLD

HLDA

BREQ

Port 6

8-bit

WDT

PLL

1KByte

ASC GPT1/2

I/O A(23:16), SSPCLK, SSPDAT, SSPCE(1:0)

A(15:0)

Port 4

8-bit

XSSP

4-bit

ST10 CO RE

Interrupt Controller

PEC

PWM

I/O

Port 1

2x8-bit

I/O

I/O, D(7:0)

D(15:8), D(7:0)

A(15:8), AD(7:0)

AD(15:8), AD(7:0)

Port 0

2x8-bit

Port 3

15-bit

I/O CLKOUT, BHE/WRH TxD0, T2IN, T3IN, T4IN, T3EUD, T3OUT, CAPIN, T6OUT

, RxD0,

Figure 2 Block diagram

Port 5

6-bit

I T2EUD, T4EUD, T5IN, T6IN, T5EUD, T6EUD

Port 7

4-bit

I/O

POUT3

Port 2

4-bit

I/O

EXIN(3:0)

11/68

ST10R172L - MEMORY MA PPING

3 MEMORY MAPPING

The ST10R172L is a ROMless device, the internal RAM space is 1 KByte. The RAM address

space is used for variables, register banks, the system stack, the PEC pointers (in 00’FCE0h

- 00’FCFFh) and the bit-addressable space (in 00’FD00h - 00’FDFFh).

00’EFFFh

256 Byte

00’EF00h

00’1FFFh

8K-byte

00’0000h

RAM/SFR

XSSP

External memory

internal memory

System Segment 0 64 K-Byte

00’FFFFh 00’F000h

Data Page 3

00’F000h

Data Page 2

00’8000h

Data Page 1

Block 1

00’4000h

Data Page 0

Block 0

00’0000h

00’FF3Fh 00’FF20h

00’FE3Fh 00’FE20h

00’FF3Fh 00’FF20h

00’F03Fh

00’F020h

SFR Area (reserved)

RAM

ESFR Area (reserved)

DPRAM / SFR Area 4 K-Byte

00’FFFFh

00’FE00h

1K-Byte

00’FA00h

00’F200h

00’F000h

12/68

Figure 3 Memory map

ST10R172L - CENTRAL PROCESSING UNIT

4 CENTRAL PROCESSING UNIT

The main core of the CPU contains a 4-stage instruction pipeline, a separate multiply and divide unit, a bit-mask generator and a barrel shifter . Most instructions can be ex ecuted in one machine cycle requiring 40ns at 50MHz CPU clock.

The CPU includes an actual register context consisting of 16 wordwide GPRs physically located in the on-chip RAM area. A Context Pointer (CP) register determines the base address of the activ e register bank to be ac cessed b y the CPU . T he number of r egister banks is only restricted by the available internal RAM space. For easy parameter passing, one register bank may overlap others.

A system stack of up to 1024 bytes is provided as a storage for temporary data. The system stack is al located in the on-chip RAM area, and it i s accessed by the C PU via the stac k pointer (SP) register. Two separate SFR s, STKOV and STKUN, are compared against the stack pointer value during each stack access to detect stack overflow or underflow.

STKOV STKUN

Exec. Unit

Instr. Ptr Instr. Reg

4-Stage

Pipeline

PSW

SYSCON

BUSCON 0 BUSCON 1

BUSCON 2 BUSCON 3 BUSCON 4

Data Pg. Ptrs

CPU

MDH

MDL

Mul./Div.-HW Bit-Mask Gen.

ALU

16-Bit

Barrel-Shift Context Ptr

ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4

Code Seg. Ptr.

R15

General

Purpose

Registers

IDX0

QR0

IDX1 QX1QX0

QR1

Figure 4 CPU block diagram

Internal

RAM

1KByte

R15

13/68

ST10R172L - INTERRUPT AND TRAP FUNCTIONS

5 INTERRUPT AND TRAP FUNCTI ONS

The architecture of the ST10R172L supports s everal mechanisms for fast and flexible response to the service requests that can be generated from various sources, internal or external to the microcontroller. Any of these interrupt requests can be programmed to be serviced, either by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In a standard interrupt service, program executi on is suspended and a branch to the interrupt

service routine is performed. For a PEC service, just one cycle is ‘stolen’ from the current CPU activity. A PEC service is a single, byte or word data transfer between any two memory locations, with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is decremented for each PEC servic e, except in the continuous transfer mode. When this counter reaches zero , a standard interrupt is performed to the corresponding source-related vector location. PEC services are very well suited, for example, to the transmission or reception of blocks of data. The ST10R172L has 8 PEC channels, each of which offers fast interrupt-driven data transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield, exists f or each of the possib le interrupt sources. Via it s related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher priority service request. For standard interrupt processing, each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs, feature programmable edge detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruc tion in combination with an individual trap (interrupt) number.

14/68

5.1 Interrupt Sources

ST10R172L - INTERRUPT AND TRAP FUNCTIONS

Source of Interru pt or PEC Service Request

External Interrupt 0 CC8IR CC8IE CC8INT 60h 18h External Interrupt 1 CC9IR CC9IE CC9INT 64h 19h External Interrupt 2 CC10IR CC10IE CC10INT 68h 1Ah External Interrupt 3 CC11IR CC11IE CC11INT 6Ch 1Bh GPT1 Timer 2 T2IR T2IE T2INT 88h 22h GPT1 Timer 3 T3IR T3IE T3INT 8Ch 23h GPT1 Timer 4 T4IR T4IE T4INT 90h 24h GPT2 Timer 5 T5IR T5IE T5INT 94h 25h GPT2 Timer 6 T6IR T6IE T6INT 98h 26h GPT2 CAPREL Register CRIR CRIE CRINT 9Ch 27h ASC0 T ransmit S0TIR S0TIE S0TINT A8h 2Ah ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 11Ch 47h

Request Flag

Enable Flag

Interrupt Vector

Vector Location

Trap Number

ASC0 Receive S0RIR S0RIE S0RINT ACh 2Bh ASC0 Error S0EIR S0EIE S0EINT B0h 2Ch PWM Channel 3 PWMIR PWMIE PWMINT FCh 3Fh SSP Interrupt XP1IR X P 1IE X P1I NT 104h 41h PLL Unlock XP3I R XP3IE X P3I NT 10Ch 43h

Table 2 List of possible interrupt sources, flags, vector and trap numbers

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ST10R172L - INTERRUPT AND TRAP FUNCTIONS

5.2 Hard w are traps

Exceptions or error conditions that arise during run-time are called Hardware T raps. Hardware traps cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual progr am ex ecution. In turn, hardware trap services can not normally be interrupted by standard or PEC interrupts. The following tab le shows all of the possible ex ceptions or error conditions that can arise during run-time:

Exception Condition T rap Flag Trap Vector

Vector Location

Reset Functions:

Hardware Reset RESET 00’0000

Software Reset RESET 00’0000 Watchdog Timer Overflow RESET 00’0000

Class A Hardware Traps:

Non-Maskable Interrupt NMI NMITRAP 00’ 0008 Stack Overflow STKOF STOTRAP 00’0010 Stack Underflow STKUF STUTRAP 00’0018

Class B Hardware Traps:

Undefined opcode UNDOPC BTRAP 00’0028h 0A Protected instruction fault PRTFLT BTRAP 00’0028h 0A Illegal word operand access ILLOPA BTRAP 00’0028h 0A Illegal instruction access ILLINA BTRAP 00’0028h 0A

Trap Number

h 00h III h 00h III h 00h III

h 02h II h 04h II h 06h II

h I h I h I h I

Trap Priority

Illegal external bus access ILLBUS BTRAP 00’0028h 0A

Reserved [2C

h – 3Ch][0Bh – 0Fh]

Software Traps

TRAP Instruction Any [00’0000

– 00’01FC steps of 4

Table 3 Exceptions or error conditions

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h I

Any [00

h – 7Fh]

Current CPU Priority

ST10R172L - PARALLEL PORTS

6 PARALLEL PORTS

The ST10R172L provides up to 77 I/O lines organized into 7 input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs by direction registers. The I/O ports are true bi directional ports which are switched to high impedance state when configured as inputs. The output drivers of three I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation by control registers. During the internal reset, all port pins are configured as inputs.

All port lines have programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing external memory , while P ort 4 outputs the additional segment address bits A23/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 6 provides optional bus arbitration signals (BREQ alternate functions of timers, serial interfaces, the optional bus control signal BHE system clock output (CLKOUT). Port 5 is used for timer control signals. Port 2 lines can be used as fast external interrupt lines. Port 7 includes alternate function for the PWM signal. All port lines that are not used for these alternate functions may be used as general purpose I/O lines.

, HLDA, HOLD) and chip select signals. Port 3 includes

and the

7 EXTE RNAL BUS CONTROLLER

All external memory accesses are performed by the on-chip External B us Controller which can be programmed either to single chip mode when no external memory is required, or to the following external memor y ac ces s modes:

16-bit data, demultiplexed 16-/18-/20-/24-bit addresses 16-bit data, multiplexed 16-/18-/20-/24-bit addresses 8-bit data, multiplexed 16-/18-/20-/24-bit addresses 8-bit data, demultiplexed 16-/18-/20-/24-bit addresses

In the demultiplex ed b us modes, addresses are output on PORT1 and data is input/output on PORT0/P0L, respectively. In the multiplex ed bus modes both addresses and data use PORT0 for input/output.

Memory cycle time, memory tri-state time, length of ALE and read write delay are programmable so that a wide range of different memory types and external peripherals can be used. Up to 4 independent address windows can be defined (via ADDRSELx / BUSCONx register pairs) to access different resources with different bus characteristics. These address windows are arranged hier archically where BUSCON4 ov errides BUSCON3 etc. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5 exte r nal CS Access to very slow memories is supported by the READY function.

signals (4 windows plus default) can be generated to reduce external glue logic.

A HOLD

/HLDA protocol is available for bus arbitration so that external resources can be shared with other bu s masters. In slav e mode, the s lave controller can be connec ted to another master controller without glue logic. For applications which require less than 16 MBytes

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ST10R172L - PWM MODULE

of external memory space, the address space can be restricted to 1 MByte, 256 KByte or to 64 KByte.

8PWM MODULE

A 1-channel Pulse Width Modulation (PWM) Module operates on channel 3. The pulse width modulation module can generate up to four PWM output signals using edge-aligned or centrealigned PWM. In addition, the PWM module can generate PWM burst signals and single shot outputs. The table below shows the PWM frequencies for different resolutions. The level of the output signals is selectable and the PWM module can generate interrupt requests.

Mode 0 edge aligned

CPU clock/1 20ns 195.3 KHz 48.83KHz 12.21KHz 3.052KHz 762.9Hz CPU clock/64 1.28ns 3.052KHz 762.9Hz 190.7Hz 47.68Hz 11.92Hz

Mode 1 center aligned

CPU clock/1 20ns 97.66KHz 24.41KHz 6.104KHz 1.525KHz 381.5Hz CPU clock/64 1.28ns 1.525Hz 381.5 Hz 95.37Hz 23.84Hz 0Hz

Resolution 8-bit 10-bit 12-bit 14-bit 16-bit

Table 4 PWM unit frequencies and resolution at 50MHz CPU clock

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ST10R172L - GENERAL PURPOSE TIMERS

9 GEN ERAL PURPOSE TIM ERS

The GPTs are flexible multifunctional timer/counters used f or time-related tasks such as e vent timing and counting, pulse width and duty cycle measurements, pulse generation or pulse multiplication. The GPT unit contains five 16-bit timers, organized in two separate modules, GPT1 and GPT2. Each timer in each module m ay operate independently in a number of different modes, or may be concatenated with another timer of the same module.

9.1 GPT1

Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually f or one of four basic modes of operation: timer, gated timer, counter mode and incremental interface mode. In timer mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler. In counter mode, the timer is clocked in reference to external events. Pulse width or duty cycle measurement is supported in gated timer mode

where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. Table 5 GPT1 timer input frequencies, resolution and periods lists the timer input frequencies, resoluti on and periods f or eac h pre-s caler option at 50MHz CPU cl oc k. T his al so applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in Timer and Gated Timer Mode

The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD).

In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has output toggle latches (TxOTL) which changes state on each timer over-flow/ underflow. The state of this latch may be output on port pins (TxOUT) e. g. for time out monitoring of external hardware components, or ma y be used internally to clock timers T2 and T4 for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers f or timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an ex ternal signal or by a selectabl e state transiti on of its toggle latch T3O TL. When both T2 and T4 are configured to alternately reload T3 on opposite state tr ansitions of T 3O T L with the low and high times of a PWM signal, this signal can be constantly generated without software intervention.

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ST10R172L - GENERAL PURPOSE TIMERS

Timer input selection

=50MHz

CPU

000b 001b 010b 011b 100b 101b 110b 111b

Prescaler

8 16 32 64 128 256 512 1024

Factor Input

Frequency

6.25 MHz 3.125 MHz

1.5625 MHz

781 KHz

391 KHz

195 KHz

97.5 KHz

48.83

KHz Resolution 160ns 320ns 640ns 1.28 us 2. 56 us 5.12 us 10.24 us 20.48 us Period 10.49ms 20 .97 ms 41 .94 ms 83 .88ms 168ms 336m s 672ms 1. 342s

Table 5 GPT1 timer input frequencies, resolution and periods

T2EUD

CPU Clock

T2IN

CPU Clock

T3EUD

T3IN

T4IN

CPU Clock

T4EUD

2n n= 3 ...10

n= 3 ...10

T2 Mode

T3 Mode

T4 Mode

GPT1 Timer T2

Reload Capture

GPT1 Timer T3

U/D

Capture

Reload

GPT1 Timer T4

U/D

Interrupt Request

T3OUT

T3OTL

Interrupt Request

U/D

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Figure 5 GPT1 block diagram

ST10R172L - GENERAL PURPOSE TIMERS

9.2 GPT2

The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock derived from the CPU clock via a programmable prescaler or with e xternal signals. The count direction (up/down) for each timer is programmable by software or altered dynamically by an exter nal signal on a port pin (TxEUD). Concatenation of the timers is supported by the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow.

The state of T6OT L may be used to cloc k timer T5, or ma y be output on a port pin T6OUT. The overflow s/underflows of timer T6 reload the CAPREL register. The CAPREL register captures the contents of T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performedwithout software overhead.

Timer input selection

=50MHz

CPU

000b 001b 010b 011b 100b 101b 110b 111b

Prescaler Factor

Input Frequency

Resolution 80ns 160 ns 320ns 640ns 1.28 us 2.56 us 5.12 us 10.24 us Period 5.24ms 10.49ms 20.97ms 41.94ms 8 3.88 ms 167.7ms 335.5m s 671m s

4 8 16 32 64 128 256 512

12.5 MHz 6.25 MHz 3.125 MHz

1.563 MHz

781 KHz

391 KHz

195 KHz

97.6 KHz

Table 6 GPT2 timer input frequencies, resolution and periods

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