SGS Thomson Microelectronics ST10R172L-B0 Datasheet

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ST10R172L-B0

16-BIT LOW VOLTAGE ROMLESS MCU

ERRATA SHEET

1 INTRODUCTION

This errata sheet describes the functional problems known in the step B0 of the
ST10R172L-B0. This is the erratasheet of the ST10R172L datasheet version 1.1 of apr il

2000.

2 FUNCTIONAL PROBLEMS

The following malfunctions are known in this step:

2.1 ST_PWRDN.1: EXECUTION OF PWRDN INSTRUCTION WHILE NMI PIN IS HIGH

When PWRDN instruction is executed while NMI pin is at a high level, power-down mode
should not be entered, and the PW RDN instruction should be ignored. Howe ver, under the
conditions described below, the PWRDN instruction may not be ignored, and no further in­structions are fetched from external memory, i.e. the CPU is in a quasi-idle state. This prob­lem will only occur in the following situations:

1) the instructions following the PWRDN instruction are located in an external memory, and a multi­plexed bus configuration

2) the instruction preceding the PWRDN instruction writes
(XRAM, CAN), and the instructions following the PWRDN instruction are located in external memory. In
this case, the problem will occur for any bus configuration.

with memory tristate waitstate (bit MTTCx= 0) is used,

to external memory or an XPeripheral

Note: the on- chip per ipherals s ti ll w ork corr ectly: i f the Watchdog Timer is not disabled, it will
reset the device upon an overflow. Interrupts and PEC transfers, however, can not be proc­essed. If NMI is asserted low while the device is i n thi s quasi-idl e state, power-down mode is
entered.

No problem will occur if the NMI

pin is low: the chip will normally enter power-down mode.

Workaround: Ensure that no instruction which writes to external memory or an XPeripheral
precedes th e PWRDN ins truc tion, o therwi se inse rt e.g. a NOP i nstr uct ion in f ro nt of PWRD N.
When a multiplexed bus with memory tristate waitstate is used, the PWRDN instruction
should be executed from internal RAM or XRAM.

Rev. 1.0

April 2000

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ST10R172L-B0 Errata Sheet

2.2 CORE.4: INCORRECT INSTRUCTION FETCH ON JUMP TO ITSELF

The bug happens In the following program sequence:

...
...
Label_A: JMPR cc_XX, Lab el_A
Word Intruction 1;

Word Intruction 2

Word Intruction 3
...
...
...

In the following conditions:

- code is fetched from External Memory,

- the loop JMPR cc_XX, Label_A is being executed,

- a PEC transfer with PSW as destination triggers a change of the condition cc_XX and so, the loop
is finished,

never

the Word Intruction1 is

executed.

Workaround: If JMPA is used instead of JMPR, the bug does not occur.

2.3 EBC.3: VISIBLE MOD E

When visible mode is enabled (syscon.1 = 1), data of a read access to an XBUS peripheral
is not driven to the external bus (Port 0). Instead, Port 0 is tri-stated during these read
accesses.

If all external devices are configured in 8-bit demultiplexed mode, an XBUS-peripheral write can cause
a conflict on P0H (Port 0 [8:15])

.

2.4 EBC.4: XPERS ACCESS IN XPERSHARE/EMULATION MODE

In emulation mode and if the Startup Configuration 8-bit multiple xed mode is selected, P0H
(Port 0 [8:15]) is always an output and write accesses to XPERs cannot be done as these
would cause a conflict.

Workaround: Use a Startup Configuration other than 8-bit multiplexed mode.
If HOLD mode is entered (P6.5 = 0) following an 8-bit multiplexed mode access and if

Xpershare is enabled, Xper accesses will cause a conflict on the internal XBUS xb_data
[15:7] bus.

Workaround: None.

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