SGS Thomson Microelectronics ST10R167 Datasheet

1/63August 1999

■ HIGH PERFORMANCE CPU

– 16-BIT CPU WITH 4-STAGE PIPELINE
– 80ns INSTRUCTION CYCLE TIME @ 25MHz CLK
– 400ns 16 X 16-BIT MULTIPLICATION
– 800ns 32 / 16-BIT DIVISION
– ENHANCED BOOLEAN BIT MANIPULATION

FACILITIES

– ADDITIONAL INSTRUCTIONS TO SUPPORT HLL

AND OPERATING SYSTEMS

– SINGLE-CYCLE CONTEXT SWITCHING SUPPORT

■ MEMORY ORGANIZATION

– UP TO16M BYTE LINEAR ADDRESS SPACE FOR

CODE AND DATA (5M BYTE WITH CAN)
– 2K BYTE ON-CHIP INTERNAL RAM (IRAM)
– 2K BYTE ON-CHIP EXTENSION RAM (XRAM)

■ FAST AND FLEXIBLE BUS

– PROGRAMMABLE EXTERNAL BUS

CHARACTERISTICS FOR DIFFERENT ADDRESS

RANGES
– 8-BIT OR 16-BIT EXTERNAL DATA BUS
– MULTIPLEXED OR DEMULTIPLEXED EXTERNAL

ADDRESS/DATA BUSES
– FIVE PROGRAMMABLE CHIP-SELECT SIGNALS
– HOLD-ACKNOWLEDGE BUS ARBITRATION

SUPPORT

■ INTERRUPT

– 8-CHANNEL PERIPHERAL EVENT CONTROLLER

FOR SINGLE CYCLE, INTERRUPT DRIVEN DATA

TRANSFER
– 16-PRIORITY-LEVEL INTERRUPT SYSTEMWITH

56 SOURCES, SAMPLE-RATE DOWN TO 40ns

■ TIMERS

– TWO MULTI-FUNCTIONAL GENERAL PURPOSE

TIMER UNITS WITH 5 TIMERS
– TWO 16-CHANNEL CAPTURE/COMPARE UNITS

■ A/D CONVERTER

– 16-CHANNEL10-BIT
– 7.76µs CONVERSION TIME

■ FAIL-SAFE PROTECTION

– PROGRAMMABLE WATCHDOG TIMER
– OSCILLATOR WATCHDOG

■ ON-CHIP CAN 2.0B INTERFACE

■ ON-CHIP BOOTSTRAP LOADER

■ CLOCK GENERATION

– ON-CHIP PLL
– DIRECT OR PRESCALEDCLOCK INPUT

■ UP TO 111GENERAL PURPOSE I/O LINES

– INDIVIDUALLY PROGRAMMABLE AS INPUT,

OUTPUT OR SPECIAL FUNCTION
– PROGRAMMABLE DRIVE STRENGTH
– PROGRAMMABLE THRESHOLD (HYSTERESIS)

■ IDLE AND POWER DOWN MODES

– IDLECURRENT <95mA
– POWER-DOWN SUPPLY CURRENT<400µA

■ 4-CHANNEL PWM UNIT

■ SERIAL CHANNELS

– SYNCHRONOUS/ASYNCSERIAL CHANNEL
– HIGH-SPEED SYNCHRONOUS CHANNEL

■ DEVELOPMENT SUPPORT

– C-COMPILERS, MACRO-ASSEMBLER PACKAGES,

EMULATORS, EVAL BOARDS, HLL-DEBUGGERS,

SIMULATORS, LOGIC ANALYZER DISASSEM-

BLERS, PROGRAMMING BOARDS

■ 144-PIN PQFP PACKAGE

PQFP144 (28 x 28 mm)

(Plastic Quad Flat Pack)

Port 0Port 1Port 4

Port 6

Port 5 Port 3

Port 2

GPT1

GPT2

ASC usart

BRG

ROM-

CPU-Core

Internal

RAM

Watchdog

Interrupt Controller

8

815

16

32

16

PEC

16

16

CAN

Port 7 Port 8

External Bus

10-Bit ADC

BRG

SSC

PWM

CAPCOM2

CAPCOM1

8

16

16

OSC.

XRAM

16

Controller

16

8

16

LESS

ST10R167

16-BIT ROMLESS MCU

This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

ST10R167

2/63

TABLE OF CONTENTS Page

I INTRODUCTION......................................................................................................... 4

II PIN DATA .................................................................................................................. 5

III FUNCTIONAL DESCRIPTION.................................................................................... 10

IV MEMORY ORGANIZATION........................................................................................ 11

V CENTRAL PROCESSING UNIT (CPU)...................................................................... 12

VI EXTERNAL BUS CONTROLLER............................................................................... 13

VII INTERRUPT SYSTEM................................................................................................ 14

VIII CAPTURE/COMPARE (CAPCOM) UNIT................................................................... 17

IX GENERAL PURPOSE TIMER UNIT........................................................................... 18

IX.1 GPT1 .......................................................................................................................... 18

IX.2 GPT2 .......................................................................................................................... 19

X PWM MODULE........................................................................................................... 21

XI PARALLEL PORTS.................................................................................................... 22

XII A/D CONVERTER...................................... ................................................................. 23

XIII SERIAL CHANNELS .............................................................................. .................... 24

XIV CAN MODULE............................................................................................................ 26

XV WATCHDOG TIMER................................................................................................... 26

XVI INSTRUCTION SET SUMMARY ............................................................................... . 27

XVII SYSTEM RESET......................................................................................................... 29

XVIII POWER REDUCTION MODES .................................................................................. 30

XIX SPECIAL FUNCTION REGISTER OVERVIEW.......................................................... 31

XIX.1 IDENTIFICATION REGISTERS ............................................................. .................... 37

XX ELECTRICAL CHARACTERISTICS ......................................................................... . 38

XX.1 ABSOLUTE MAXIMUM RATINGS ............................................................................. 38

XX.2 PARAMETER INTERPRETATION ............................................................................. 38

XX.3 DC CHARACTERISTICS ........................................................................................... 39

XX.3.1 A/D converter characteristics ...................................................................................... 40

XX.4 AC CHARACTERISTICS ............................................................................................ 41

XX.4.1 Definition of internal timing ......................................................................................... 42

XX.4.2 Clock generation modes ............................................................................................. 42

ST10R167

3/63

XX.4.3 Prescaler operation .................................................................................................... 43

XX.4.4 Direct drive ................................................................................................................. 43

XX.4.5 Oscillator watchdog (OWD) ........................................................................................ 43

XX.4.6 Phase locked loop ...................................................................................................... 43

XX.4.7 Memory cycle variables .............................................................................................. 44

XX.4.8 External clock drive XTAL1 .......................................... .............................................. 45

XX.4.9 Multiplexed bus ........................................................................................................... 45

XX.4.10 Demultiplexed bus ...................................................................................................... 52

XX.4.11 CLKOUT and READY ................................................................................................. 58

XX.4.12 External bus arbitration ........................................................................... .................... 60

XXI PACKAGE MECHANICAL DATA ........................................................................... 62

XXII ORDERING INFORMATION....................................................................................... 62

TABLE OF CONTENTS (continued) Page

ST10R167

4/63

I - INTRODUCTION

The ST10R167 is a derivative of the
STMicroelectronics ST10 family of 16-bit
single-chip CMOS microcontrollers. It combines
high CPU performance (up to 12.5 million

instructions per second) with high peripheral
functionality and enhanced I/O capabilities.

It also provides on-chip high-speed RAM and
clock generation viaPLL.

Figure 1 : Logic Symbol

XTAL1

RSTIN

XTAL2

RSTOUT

NMI
EA

READY
ALE

RD
WR/WRL

Port 5
16-bit

Port 6

8-bit

Port 4

8-bit

Port 3

15-bit

Port 2

16-bit

Port 1

16-bit

Port 0

16-bit

V

DD

V

SS

Port 7
8-bit

Port 8

8-bit

V

AREF

V

AGND

ST10R167

RPD

ST10R167

5/63

II - PIN DATA
Figure 2 : Pin Configuration (top view)

P6.0/CS0
P6.1/CS1
P6.2/CS2
P6.3/CS3
P6.4/CS4

P6.5/HOLD

P6.6/HLDA

P6.7/BREQ
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO

P8.6/CC22IO
P8.7/CC23IO

V

DD

V

SS

P7.0/POUT0
P7.1/POUT1
P7.2/POUT2
P7.3/POUT3

P8.5/CC21IO

RPD

P7.4/CC28I0
P7.5/CC29I0
P7.6/CC30I0
P7.7/CC31I0

P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.6/AN6
P5.7/AN7
P5.8/AN8
P5.9/AN9

P0H.0/AD8
P0L.7/AD7
P0L.6/AD6
P0L.5/AD5
P0L.4/AD4
P0L.3/AD3
P0L.2AD2
P0L.A/AD1
P0L.0/AD0
EA

ALE
READY
WR/WRL
RD
V

SS

V

DD

P4.7/A23
P4.6A22/CAN_TxD
P4.5A21/CAN_RxD
P4.4/A20
P4.3/A19
P4.2/A18
P4.1/A17
P4.0/A16

V

SS

V

DD

P3.15/CLKOUT
P3.13/SCLK
P3.12/BHE/WRH
P3.11/RXD0
P3.10/TXD0
P3.9/MTSR
P3.8/MRST
P3.7/T2IN

P3.6/T3IN

V

AREF

V

AGND

P5.10/AN10/T6EUD

P5.11/AN11/T5EUD

P5.12/AN12/T6IN

P5.13/AN13/T5IN

P5.14/AN14/T4EUD

P5.15/AN15/T2EUD

V

SS

V

DD

P2.0/CC0IO

P2.1/CC1IO

P2.2/CC2IO

P2.3/CC3IO

P2.4/CC4IO

P2.5/CC5IO

P2.6/CC6IO

P2.7/CC7IO

V

SS

V

DD

P2.8/CC8IO/EX0IN

P2.9/CC9IO/EX1IN

P2.10/CC10IOEX2IN

P2.11/CC11IOEX3IN

P2.12/CC12IO/EX4IN

P2.13/CC13IO/EX5IN

P2.14/CC14IO/EX6IN

P2.15/CC15IO/EX7IN/T7IN

P3.0/T0IN

P3.1/T6OUT

P3.2/CAPIN

P3.3/T3OUT

P3.4/T3EUD

P3.5/T4IN

V

SS

V

DD

VSSNMI

VDDRSTOUT

RSTIN

VSSXTAL1

XTAL2

VDDP1H.7/A15/CC27IO

P1H.6/A14/CC26IO

P1H.5/A13/CC25IO

P1H.4/A12/CC24IO

P1H.3/A11

P1H.2/A10

P1H.1/A9

P1H.0/A8

VSSVDDP1L.7/A7

P1L.6/A6

P1L.5/A5

P1L.4/A4

P1L.3/A3

P1L.2/A2

P1L.1/A1

P1L.0/A0

P0H.7/AD15

P0H.6/AD14

P0H.5/AD13

P0H.4/AD12

P0H.3/AD11

P0H.2/AD10

P0H.1/AD9

VSSV

DD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

3738394041424344454647484950515253545556575859606162636465666768697071

72

108
107
106
105
104
103
102
101
100

99
98

97
96
95

94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

ST10R167

ST10R167

6/63

Table 1 : Pin list

Symbol Pin Type Function

P6.0 - P6.7 1 - 8 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via

direction bits. Programming an I/O pin as input forces the corresponding
output driver tohigh impedance state. Port 6 outputs can be configured as
push/pull or open drain drivers.
The following Port 6 pins have alternate functions:

1

...

5
6
7
8

O
...
O

I
O
O

P6.0 CS0 Chip Select 0Output

... ... ...

P6.4 CS4 Chip Select 4Output
P6.5 HOLD External Master Hold Request Input
P6.6 HLDA Hold Acknowledge Output
P6.7 BREQ Bus Request Output

P8.0 - P8.7 9 - 16 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via

direction bits. Programming an I/O pin as input forces the corresponding
output driver tohigh impedance state. Port 8 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 8 is selectable
(TTL or special).
The following Port 8 pins have alternate functions:

9

...

16

I/O

...

I/O

P8.0 CC16IO CAPCOM2: CC16 Capture Input/Compare Output

... ... ...

P8.7 CC23IO CAPCOM2: CC23 Capture Input/Compare Output

P7.0 - P7.7 19 - 26 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via

direction bits. Programming an I/O pin as input forces the corresponding
output driver tohigh impedance state. Port 7 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 7 is selectable
(TTL or special).
The following Port 7 pins have alternate functions:

19

...
22
23

...
26

O
...
O

I/O

...

I/O

P7.0 POUT0 PWM Channel 0 Output

... ... ...

P7.3 POUT3 PWM Channel 3 Output
P7.4 CC28IO CAPCOM2: CC28 Capture Input/Compare Output

... ... ...

P7.7 CC31IO CAPCOM2: CC31 Capture Input/Compare Output

P5.0 - P5.9

P5.10 - P5.15

27 - 36
39 - 44

I
I

Port 5 is a 16-bit input-only port with Schmitt-Trigger characteristics. The
pins of Port 5 also serve as the (up to 16) analoginput channels for the A/
D converter, where P5.x equals ANx (Analog input channel x), or they
serve as timer inputs:

39
40
41
42
43
44

I
I
I
I
I
I

P5.10 T6EUD GPT2 Timer T6External Up/Down Control Input
P5.11 T5EUD GPT2 Timer T5External Up/Down Control Input
P5.12 T6IN GPT2 Timer T6Count Input
P5.13 T5IN GPT2 Timer T5Count Input
P5.14 T4EUD GPT1 Timer T4External Up/Down Control Input
P5.15 T2EUD GPT1 Timer T2External Up/Down Control Input

II - PIN DATA(continued)

ST10R167

7/63

P2.0 - P2.7

P2.8 - P2.15

47 - 54
57 - 64

I/O 16-bit bidirectional I/O port, bit-wise programmable for input or output via

direction bits. Programming an I/O pin as input forces the corresponding
output driver tohigh impedance state. Port 2 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 2 is selectable
(TTL or special).
The following Port 2 pins have alternate functions:

47

...
54
57

...
64

I/O

...
I/O
I/O

I

...
I/O

I
I

P2.0 CC0IO CAPCOM: CC0 Capture Input/Compare Output

... ... ...

P2.7 CC7IO CAPCOM: CC7 Capture Input/Compare Output
P2.8 CC8IO CAPCOM: CC8 Capture Input/Compare Output
EX0IN Fast External Interrupt 0 Input

... ... ...

P2.15 CC15IO CAPCOM: CC15 Capture Input/Compare Output
EX7IN Fast External Interrupt 7 Input
T7IN CAPCOM2 Timer T7 Count Input

P3.0 - P3.5

P3.6 - P3.13

P3.15

65 - 70
73 - 80

81

I/O
I/O
I/O

15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for
input or output via direction bits. Programming an I/O pin as input forces
the corresponding output driver to high impedance state. Port 3 outputs
can be configured as push/pull or open drain drivers. The input threshold
of Port 3 is selectable (TTL or special).
The following Port 3 pins have alternate functions:

65
66
67
68
69
70
73
74
75
76
77
78
79

80
81

I

O

I

O

I
I
I

I
I/O
I/O
I/O

O
O

I/O

O

P3.0 T0IN CAPCOM Timer T0 Count Input
P3.1 T6OUT GPT2 TimerT6 Toggle Latch Output
P3.2 CAPIN GPT2 Register CAPREL Capture Input
P3.3 T3OUT GPT1 TimerT3 Toggle Latch Output
P3.4 T3EUD GPT1 TimerT3 External Up/Down Control Input
P3.5 T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture
P3.6 T3IN GPT1 Timer T3 Count/Gate Input
P3.7 T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture
P3.8 MRST SSC Master-Receive/Slave-Transmit I/O
P3.9 MTSR SSC Master-Transmit/Slave-Receive O/I
P3.10 TxD0 ASC0 Clock/Data Output (Asynchronous/Synchronous)
P3.11 RxD0 ASC0 Data Input (Asyn.) or I/O (Synchronous)
P3.12 BHE External Memory High Byte Enable Signal,

WRH External Memory High Byte Write Strobe
P3.13 SCLK SSC Master Clock Output/Slave Clock Input
P3.15 CLKOUT System Clock Output (=CPU Clock)

P4.0 - P4.7 85 - 92 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via

direction bits. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. For external bus configuration,
Port 4 can be used to output the segment address lines:

85 - 89

90
91
92

O
O

I
O
O
O

P4.0 - P4.4 A16 - A20 Least Significant Segment Address Line
P4.5 A21 Segment Address Line

CAN_RxD CAN Receive Data Input

P4.6 A22 Segment Address Line,

CAN_TxD CAN Transmit Data Output

P4.7 A23 Most Significant Segment Address Line

RD 95 O External Memory Read Strobe. RD is activated for every external instruc-

tion or data read access.

Table 1 : Pin list (continued)

Symbol Pin Type Function

II - PIN DATA(continued)

ST10R167

8/63

WR/WRL 96 O External Memory Write Strobe. In WR-mode this pin is activated for every

external data write access. In WRL-mode this pin is activated for low byte
data write accesses on a 16-bit bus, and for every data write access onan
8-bit bus. See WRCFG in register SYSCON for mode selection.

READY/READY 97 I Ready Input. The active level is programmable. When the Ready function

is enabled, the selected inactive level at this pin during an external mem­ory access will force the insertion of memory cycle time waitstates until
the pin returns to the selected active level.

ALE 98 O Address Latch Enable Output. Can be used for latching the address into

external memory or an address latch in the multiplexed bus modes.

EA 99 I External Access Enable pin. A low level at this pin during and after Reset

forces the ST10R167 to begin instruction execution out of external mem­ory. A high level forces execution out of the internal Flash Memory.

P0L.0 - P0L.7

P0H.0

P0H.1 - P0H.7

100 - 107

108

111 - 117

I/O Port 0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is

bit-wise programmable for input or output via direction bits. For a pin con­figured as input, the outputdriver is put into high-impedance state. In case
of an external bus configuration, Port 0 serves as the address (A) and
address/data (AD) bus in multiplexed bus modes and as the data (D) bus
in demultiplexed bus modes.

Demultiplexed bus modes:

Data Path Width : 8-bit 16-bit
P0L.0 – P0L.7 : D0 – D7 D0 - D7
P0H.0 – P0H.7 : I/O D8 - D15

Multiplexed bus modes:

Data Path Width : 8-bit 16-bit
P0L.0 – P0L.7 : AD0 – AD7 AD0 - AD7
P0H.0 – P0H.7 : A8 - A15 AD8 - AD15

P1L.0 - P1L.7

P1H.0 - P1H.7

118 - 125
128 - 135

I/O Port 1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is

bit-wise programmable for input or output via direction bits. For a pin con­figured as input, the output driver is put into high-impedance state. Port 1
is used as the 16-bit address bus (A) in demultiplexed bus modes and
also after switching from a demultiplexed bus mode to a multiplexed bus
mode.
The following PORT1 pins also serve foralternate functions:

132
133
134
135

I

I

I

I

P1H.4 CC24IO CAPCOM2: CC24 Capture Input
P1H.5 CC25IO CAPCOM2: CC25 Capture Input
P1H.6 CC26IO CAPCOM2: CC26 Capture Input

P1H.7 CC27IO CAPCOM2: CC27 Capture Input
XTAL1 138 I Input to the oscillator amplifier and input to the internal clock generator
XTAL2 137 O Output of the oscillator amplifier circuit.

To clock the device from an external source, drive XTAL1, while leaving

XTAL2 unconnected. Minimum and maximum high/low and rise/fall times

specified in the AC Characteristics must be observed.
RSTIN 140 I Reset Input with Schmitt-Trigger characteristics. A low level atthis pin for

a specified duration while the oscillator is running resets the ST10R167.

An internal pullup resistor permits power-on reset using only a capacitor

connected to V

SS

.
In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON
register), the RSTIN line is pulled low for the duration of the internal reset
sequence.

Table 1 : Pin list (continued)

Symbol Pin Type Function

II - PIN DATA(continued)

ST10R167

9/63

RSTOUT 141 O Internal Reset Indication Output. This pin is set to a low level when the

part is executing either a hardware-, a software- or a watchdog-timer
reset. RSTOUT remains low until the EINIT (end of initialization) instruc­tion is executed.

NMI 142 I Non-Maskable Interrupt Input. A high to low transition at this pin causes

the CPU to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in
SYSCON register, when the PWRDN (power down) instruction is exe­cuted, the NMI pin must be low in order to force the ST10R167 to go into
power down mode. If NMI is high and PWDCFG =’0’, when PWRDN is
executed, the part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.

V

AREF

37 - Reference voltage for the A/D converter.

V

AGND

38 - Reference ground for the A/D converter.

RPD 84 - This pin is used as the timing pin for the return from powerdown circuit

and power-up asynchronous reset.

V

DD

17, 46, 56,
72, 82, 93,

109, 126,

136, 144

- Digital Supply Voltage:
= + 5V during normal operation and idle mode.
> + 2.5V during power down mode

V

SS

18, 45, 55,
71, 83, 94,

110, 127,

139, 143

- Digital Ground.

Table 1 : Pin list (continued)

Symbol Pin Type Function

II - PIN DATA(continued)

ST10R167

10/63

III - FUNCTIONAL DESCRIPTION

The architecture of the ST10R167 combines
advantages of both RISC and CISC processors
and an advanced peripheral subsystem. The

block diagram gives an overview of the different
on-chip componentsand thehigh bandwidth inter­nal bus structureof the ST10R167.

Figure 3 : Block diagram

Port 0Port 1Port 4

Port 6

Port 5

Port 3

Port 2

GPT1

GPT2

ASC usart

BRG

CPU-Core

Internal

RAM

Watchdog

Interrupt Controller

32

16

PEC

16

16

CAN

Port 7

Port 8

External Bus

10-Bit ADC

BRG

SSC

PWM

CAPCOM2

CAPCOM1

OSC.

2K Byte

16

Controller

16

16

ROMLESS

XRAM

XTAL1
XTAL2

CAN_RXD

CAN_TXD

External
Memory

8

16

16

8

15 8 8

16

ST10R167

11/63

IV - MEMORY ORGANIZATION

The memory space of the ST10R167 is
configured in a Von-Neumann architecture. Code
memory, data memory, registers and I/O ports are
organized within the samelinear address spaceof
16M Byte.

The entire memory space can be accessed Byte­wise or Wordwise. Particular portions of the
on-chip memory have additionally been made
directly bit addressable.

ROM : 32KByte of on-chip ROM.
RAM : 2K Byte of on-chip internal RAM

(dual-port) is provided as a storage for data, sys­tem stack, general purpose register banks and
code. The register bank can consist of up to 16
wordwide (R0 to R15) and/or Bytewide (RL0,
RH0, …, RL7, RH7)general purpose registers.

XRAM : 2K Byte of on-chip extension RAM (sin­gle port XRAM) is provided as a storage for data,
user stack and code.

The XRAM isconnected to the internal XBUS and
is accessed like an external memory in 16-bit
demultiplexed bus-mode without waitstate or
read/write delay (80ns access at 25MHz CPU
clock). Byte and Word access is allowed.

The XRAM address range is 00’E000h ­00’E7FFh if the XRAM is enabled (XPEN bit 2 of
SYSCON register). As the XRAM appears like
external memory, it cannot be used for the
ST10R167’s system stack or register banks. The

XRAM is not provided for single bit storage and
therefore is not bit addressable. If bit XRAMEN is
cleared, then any access in the address range
00’E000h - 00’E7FFh will be directed to external
memory interface, using the BUSCONx register
corresponding to address matching ADDRSELx
register.

SFR/ESFR : 1024 Byte (2 * 512 Byte) of address
space is reserved for the special function register
areas. SFRs are wordwide registers which are
used for controlling and monitoring functions of
the different on-chipunits.

CAN : Address range 00’EF00h - 00’EFFFh is
reserved forthe CAN Module access. TheCAN is
enabled by setting XPEN bit 2 of the SYSCON
register. Accesses to the CAN Module use demul­tiplexed addresses and a 16-bit data bus (Byte
accesses are possible). Two wait states give an
access time of 160ns at 25MHz CPU clock. No
tristate waitstate isused.

Note If the CAN module is used, Port 4 can not

be programmed to output all 8 segment
address lines. Thus, only 4 segment
address lines can be used, reducing the
external memory space to 5M Byte (1M
Byte per CS line).

In orderto meet the needs ofdesigns where more
memory is required than is provided on chip, up to
16M Byte of external RAM and/or ROM can be
connected to the microcontroller.

ST10R167

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V - CENTRAL PROCESSING UNIT (CPU)

The CPUincludes a4-stage instruction pipeline, a
16-bit arithmetic and logic unit (ALU) and dedi­cated SFRs. Additionalhardware hasbeen added
for a separate multiply and divide unit, a bit-mask
generator and a barrel shifter.

Most of the ST10R167’s instructions can be exe­cuted in oneinstruction cycle which requires 80ns
at 25MHz CPU clock. For example, shift and
rotate instructions are processed in one instruc­tion cycle independent of the number of bits to be
shifted. Multiple-cycle instructionshave been opti­mized: branches are carried out in 2 cycles, 16 x
16 bit multiplication in 5 cycles and a 32/16 bit
division in 10 cycles.The jump cache reduces the
execution time of repeatedly performed jumps in a
loop, from 2 cycles to 1 cycle.

The CPU uses an actual register context
consisting of up to16 Word wide GPRs physically
allocated within the on-chip RAM area. A Context
Pointer (CP) register determines the base
address ofthe active register bank to beaccessed
by the CPU. The number of register banks is only
restricted by the available internal RAM space.
For easy parameter passing, a register bank may
overlap others.

A systemstack of up to 1024 Byte is provided as a
storage for temporary data. The system stack is
allocated in the on-chip RAM area, and it is
accessed by the CPU via the stack pointer (SP)
register. Two separate SFRs, STKOV and
STKUN, are implicitly compared against the stack
pointer value upon each stack access for the
detection of a stack overflow orunderflow.

Figure 4 : CPU Block Diagram

32

Internal

RAM

2K Byte

General

Purpose

Registers

R0

R15

MDH

MLD

Barrel-Shift

Mul./Div.-HW

Bit-Mask Gen.

ALU

16-Bit

CP

SP

STKOV
STKUN

Exec. Unit

Instr. Ptr
Instr. Reg

4-Stage
Pipeline

PSW

SYSCON

BUSCON 0
BUSCON 1

BUSCON 2
BUSCON 3
BUSCON 4

ADDRSEL 1
ADDRSEL 2

ADDRSEL 3
ADDRSEL 4

Data Pg. Ptrs

Code Seg. Ptr.

CPU

External
Memory

16

16

Bank

n

Bank

i

Bank

0

ST10R167

13/63

VI - EXTERNAL BUS CONTROLLER

All of the external memory accesses are per­formed by the on-chip external bus controller. The
EBC can be programmed to single chip mode
when no external memory is required,or to one of
four different external memory access modes:

– 16-/18-/20-/24-bit addresses and 16-bit data,

demultiplexed.

– 16-/18-/20-/24-bit addresses and 16-bit data,

multiplexed.

– 16-/18-/20-/24-bit addresses and 8-bit data,

multiplexed.

– 16-/18-/20-/24-bit addresses and 8-bit data, de-

multiplexed.

In demultiplexed bus modes addresses are output
on Port1 and data is input/output on Port0 or P0L,
respectively. In the multiplexed bus modes both
addresses and data use Port0 for input/output.

Timing characteristics of the external bus inter­face (memory cycle time, memory tri-state time,
length of ALE and read/write delay) are program­mable giving the choice of a wide range of memo­ries and external peripherals. Up to 4 independent
address windows may be defined (using register
pairs ADDRSELx / BUSCONx) to access different
resources and bus characteristics. These address
windows are arranged hierarchically where
BUSCON4 overrides BUSCON3 and BUSCON2
overrides BUSCON1. All accesses to locations
not covered by these 4 address windows are con­trolled by BUSCON0. Up to 5 external CS signals
(4 windows plus default) can be generated in
order to save external glue logic. Access to very
slow memoriesis supportedby a ‘Ready’ function.

A HOLD/HLDA protocol is available for bus arbi­tration which shares external resources with other
bus masters. The bus arbitration is enabled by
setting bit HLDEN in register SYSCON. After set­ting HLDEN once, pins P6.7...P6.5 (BREQ,
HLDA, HOLD) are automatically controlled by the
EBC. In master mode (default after reset) the
HLDA pin is an output. By setting bit DP6.7 to’1’
the slave mode is selected where pin HLDA is
switched to input. This directly connects the slave
controller to another master controller without
glue logic.

For applications which require less external mem­ory space, the address space can be restricted to
1M Byte, 256K Byte or to64K Byte.Port 4 outputs
all 8 address lines if an address space of
16M Byte is used, otherwise four, two or no
address lines.

Chip select timing can be made programmable.
By default (after reset), the CSx lines change half
a CPU clock cycle after the rising edge of ALE.
With the CSCFG bit set in the SYSCON register
the CSx lines change with the rising edge of ALE.

The active level of the READY pin can be set by
bit RDYPOLin the BUSCONx registers.When the
READY function is enabled for a specific address
window, each bus cycle within the window must
be terminated with the active level defined by bit
RDYPOL in theassociated BUSCON register.

ST10R167

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VII - INTERRUPT SYSTEM

The interrupt response time for internal program
execution is from 200ns to 480ns.

The ST10R167 architecture supports several
mechanisms for fast and flexible response to ser­vice requests that can be generated from various
sources internal or external tothe microcontroller.
Any of these interrupt requests can be serviced by
the Interrupt Controller or by the Peripheral Event
Controller (PEC).

In contrast to a standard interrupt service where
the current program execution is suspended and
a branch to the interrupt vector table is performed,
just one cycle is ‘stolen’ from the current CPU
activity to perform a PEC service. A PEC service
implies a single Byte or Word data transfer
between any two memory locations with an addi­tional increment of either the PEC source or the
destination pointer. An individual PEC transfer
counter is implicitly decremented for each PEC
service except when performing in the continuous
transfer mode. When this counter reaches zero, a
standard interrupt is performed to the correspond­ing source related vector location. PEC services
are very well suited, for example, for supporting
the transmission or reception of blocks of data.
The ST10R167 has 8 PEC channels each of

which offers such fast interrupt-driven data trans­fer capabilities.

A interrupt control register which contains an
interrupt request flag, an interrupt enable flag and
an interrupt priority bitfield is dedicated to each
existing interrupt source. Thanks to its related
register, each source can be programmed to one
of sixteen interrupt priority levels. Once starting to
be processed by the CPU, an interrupt service
can only be interrupted by a higher prioritized
service request. For the standard interrupt
processing, each of the possible interruptsources
has a dedicated vector location.

Fast external interrupt inputs are provided to ser­vice external interrupts with high precision
requirements. These fast interrupt inputs feature
programmable edge detection (rising edge, falling
edge or both edges).

Software interruptsare supportedbymeans of the
‘TRAP’ instruction in combination with an individ­ual trap (interrupt)number.

Table 2 shows all the available ST10R167 inter­rupt sources and the corresponding hard­ware-related interrupt flags, vectors, vector
locations and trap (interrupt) numbers :

Table 2 : Interrupt sources

Source of Interrupt or PEC

Service Request

Request

Flag

Enable

Flag

Interrupt

Vector

Vector

Location

Trap

Number

CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040h 10h
CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044h 11h
CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048h 12h
CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004Ch 13h
CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050h 14h
CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054h 15h
CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058h 16h
CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005Ch 17h
CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060h 18h
CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064h 19h
CAPCOM Register 10 CC10IR CC10IE CC10INT 00’0068h 1Ah
CAPCOM Register 11 CC11IR CC11IE CC11INT 00’006Ch 1Bh
CAPCOM Register 12 CC12IR CC12IE CC12INT 00’0070h 1Ch
CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074h 1Dh
CAPCOM Register 14 CC14IR CC14IE CC14INT 00’0078h 1Eh
CAPCOM Register 15 CC15IR CC15IE CC15INT 00’007Ch 1Fh
CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0h 30h
CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4h 31h

ST10R167

15/63

CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8h 32h
CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CCh 33h
CAPCOM Register 20 CC20IR CC20IE CC20INT 00’00D0h 34h
CAPCOM Register 21 CC21IR CC21IE CC21INT 00’00D4h 35h
CAPCOM Register 22 CC22IR CC22IE CC22INT 00’00D8h 36h
CAPCOM Register 23 CC23IR CC23IE CC23INT 00’00DCh 37h
CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0h 38h
CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4h 39h
CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8h 3Ah
CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00ECh 3Bh
CAPCOM Register 28 CC28IR CC28IE CC28INT 00’00E0h 3Ch
CAPCOM Register 29 CC29IR CC29IE CC29INT 00’0110h 44h
CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114h 45h
CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118h 46h
CAPCOM Timer 0 T0IR T0IE T0INT 00’0080h 20h
CAPCOM Timer 1 T1IR T1IE T1INT 00’0084h 21h
CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4h 3Dh
CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8h 3Eh
GPT1 Timer 2 T2IR T2IE T2INT 00’0088h 22h
GPT1 Timer 3 T3IR T3IE T3INT 00’008Ch 23h
GPT1 Timer 4 T4IR T4IE T4INT 00’0090h 24h
GPT2 Timer 5 T5IR T5IE T5INT 00’0094h 25h
GPT2 Timer 6 T6IR T6IE T6INT 00’0098h 26h
GPT2 CAPREL Register CRIR CRIE CRINT 00’009Ch 27h
A/D Conversion Complete ADCIR ADCIE ADCINT 00’00A0h 28h
A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4h 29h
ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8h 2Ah
ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011Ch 47h
ASC0 Receive S0RIR S0RIE S0RINT 00’00ACh 2Bh
ASC0 Error S0EIR S0EIE S0EINT 00’00B0h 2Ch
SSC Transmit SCTIR SCTIE SCTINT 00’00B4h 2Dh
SSC Receive SCRIR SCRIE SCRINT 00’00B8h 2Eh
SSC Error SCEIR SCEIE SCEINT 00’00BCh 2Fh
PWM Channel 0...3 PWMIR PWMIE PWMINT 00’00FCh 3Fh
CAN Interface XP0IR XP0IE XP0INT 00’0100h 40h
X-Peripheral Node XP1IR XP1IE XP1INT 00’0104h 41h
X-Peripheral Node XP2IR XP2IE XP2INT 00’0108h 42h
PLL Unlock XP3IR XP3IE XP3INT 00’010Ch 43h

Table 2 : Interrupt sources (continued)

Source of Interrupt or PEC

Service Request

Request

Flag

Enable

Flag

Interrupt

Vector

Vector

Location

Trap

Number

VII - INTERRUPT SYSTEM (continued)

ST10R167

16/63

Hardware traps are exceptions or error conditions
that arise during run-time. They cause immediate
non-maskable system reaction similar to a stan­dard interrupt service (branching to a dedicated
vector table location).

The occurrence of a hardware trap is additionally
signified by an individual bit in the trap flag regis-

ter (TFR). Except when another higher prioritized
trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn,
hardware trap services can normally not be inter­rupted by standard or PEC interrupts.

Table 3 shows all of the possible exceptions or
error conditions that can arise during run-time:

Table 3 : Exceptions or error conditions that can arise during run time

Exception Condition

Trap
Flag

Trap

Vector

Vector

Location

Trap

Number

Trap

Priority

Reset Functions:

Hardware Reset
Software Reset
Watchdog Timer Overflow

RESET
RESET
RESET

00’0000h
00’0000h
00’0000h

00h
00h
00h

III
III
III

Class A Hardware Traps:

Non-Maskable Interrupt
Stack Overflow
Stack Underflow

NMI
STKOF
STKUF

NMITRAP
STOTRAP
STUTRAP

00’0008h
00’0010h
00’0018h

02h
04h
06h

II
II
II

Class B Hardware Traps:

Undefined Opcode
Protected Instruction Fault
Illegal Word Operand
Access
Illegal Instruction Access
Illegal External Bus
Access

UNDOPC

PRTFLT

ILLOPA

ILLINA

ILLBUS

BTRAP
BTRAP
BTRAP
BTRAP
BTRAP

00’0028h
00’0028h
00’0028h
00’0028h
00’0028h

0Ah
0Ah
0Ah
0Ah
0Ah

I
I
I
I
I

Reserved [2Ch –3Ch] [0Bh – 0Fh]

Software Traps

TRAP Instruction

Any [00’0000h– 00’01FCh]

in steps of 4h

Any

[00h – 7Fh]

Current CPU

Priority

VII - INTERRUPT SYSTEM (continued)

ST10R167

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VIII - CAPTURE/COMPARE (CAPCOM) UNIT

The ST10R167 has two 16 channel CAPCOM
units. They support generation and control of
timing sequences on up to 32 channels with a
maximum resolution of 320ns at 25MHz CPU
clock. The CAPCOM units are typically used to
handle high speed I/O tasks such as pulse and
waveform generation, pulse width modulation
(PMW), Digital to Analog (D/A) conversion,
software timing, or time recording relative to
external events.

Four 16-bit timers (T0/T1, T7/T8) with reload
registers provide two independent time bases for
the capture/compare register array.

The input clock for the timers is programmable to
several prescaled values of the internal system
clock, or may be derived from an overflow/
underflow of timer T6 in module GPT2. This
provides a wide range of variation for the timer
period and resolution and allows precise
adjustments to application specific requirements.
In addition, external count inputs for CAPCOM
timers T0 and T7 allow event scheduling for the
capture/compare registers relative to external
events.

Each of the two capture/compare register arrays
contain 16 dual purpose capture/compare
registers, each of which may be individually
allocated to either CAPCOM timer T0 or T1 (T7 or
T8, respectively), and programmed for capture or
compare functions. Each register has one
associated port pin which serves as an input pin

for triggering the capture function, or as an output
pin (except for CC24...CC27) to indicate the
occurrence of acompare event.

When a capture/compare register has been
selected forcapture mode, thecurrent contents of
the allocated timer will be latched (captured) into
the capture/compare register in response to an
external event at the port pin which is associated
with this register. In addition, a specific interrupt
request for this capture/compare register is
generated. Either a positive, a negative, or both a
positive and a negative external signal transition
at the pin can be selected as the triggering event.
The contents of all registers which have been
selected for one of the five compare modes are
continuously compared with the contents of the
allocated timers. When a match occurs between
the timer value and the value in a capture/
compare register, specific actions will be taken
based on the selected compare mode (see
Table 4).

The input frequencies fTxforTx aredetermined as
a function of the CPU clocks. The formulas are
detailed in the user manual. The timer input fre­quencies, resolution and periods which result
from the selected pre-scaler option in TxI when
using a 25MHz CPU clock are listed in the table
below. The numbers for the timer periods are
based ona reload value of0000H. Note that some
numbers may be rounded to 3 significant figures
(see Table5).

Table 4 : Compare modes

Compare Modes Function

Mode 0 Interrupt-only compare mode ; several compare interrupts per timer period are possible
Mode 1 Pin toggles on each compare match ; several compare events per timer period are possible
Mode 2 Interrupt-only compare mode ; only one compare interrupt per timer period is generated
Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow ; only one compare event per

timer period is generated

Double Register Mode Two registers operate on one pin; pin toggles on each compare match ; several compare

events per timer period are possible.

Table 5 : CAPCOM timer input frequencies, resolution and periods

f

CPU

= 25MHz

Timer Input Selection TxI

000

B

001

B

010

B

011

B

100

B

101

B

110

B

111

B

Pre-scaler for f

CPU

8 16 32 64 128 256 512 1024

Input Frequency 3.125MHz 1.56MHz 781KHz 391KHz 195KHz 97.7KHz 48.8KHz 24.4KHz
Resolution 320ns 640ns 1.28µs 2.56µs 5.12µs 10.24µs 20.48µs 40.96µs
Period 21.0ms 41.9ms 83.9ms 167ms 336ms 671ms 1.34s 2.68s

ST10R167

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IX - GENERAL PURPOSE TIMER UNIT

The GPT unit is a flexible multifunctional timer/
counter structure which is used for time related
tasks such as event timing and counting, pulse
width and duty cycle measurements, pulse
generation, or pulse multiplication. The GPT unit
contains five 16-bit timers organized into two
separate modules GPT1and GPT2.Each timer in
each module may operate independently in
several different modes, or may be concatenated
with another timer of the same module.

IX.1 - GPT1

Each of the three timers T2, T3, T4 of the GPT1
module can be configured individually for one of
four basic modes of operation: timer, gated

timer, counter mode and incremental interface
mode. In timer mode, the inputclock for a timer is

derived from the CPU clock, divided by a pro­grammable prescaler. In counter mode, the timer
is clocked in reference to external events. Pulse
width or duty cycle measurement is supported in
gated timermode where theoperation ofa timer is
controlled by the ‘gate’ level on an external input
pin. For these purposes, each timer has oneasso­ciated port pin (TxIN) which is the gate or the
clock input.

The table below lists the timer input frequencies,
resolution and periods for each pre-scaler option
at 25MHz CPU clock. This also applies to the
Gated Timer Mode of T3 and to the auxiliary
timers T2 and T4 inTimer and Gated Timer Mode
(see Table6).

The count direction (up/down) for each timer is
programmable by software or may additionally be

altered dynamically by an external signal ona port
pin (TxEUD).

In Incremental Interface Mode, the GPT1 timers
(T2, T3, T4) can be directly connected to the
incremental position sensor signals A and B by
their respective inputs TxIN and TxEUD. Direction
and count signals are internally derived from
these two input signals so that the contentsof the
respective timer Tx corresponds to the sensor
position. The third position sensor signal TOP0
can be connected to an interrupt input.

TimerT3 hasoutput toggle latches (TxOTL)which
changes state on each timer over-flow/underflow.
The state of this latch may be output on port pins
(TxOUT) e. g. for time out monitoring of external
hardware components, or may be used internally
to clock timers T2 and T4 for high resolution mea­surement of long timeperiods.

In addition to their basic operating modes, timers
T2 andT4 maybe configured as reload or capture
registers for timer T3. When used as capture or
reload registers, timers T2 and T4 are stopped.
The contents of timer T3 is captured into T2 or T4
in response to a signal at their associated input
pins (TxIN). Timer T3 is reloaded with the
contents of T2 or T4 triggered either by an
external signal or by a selectable state transition
of its toggle latch T3OTL. When both T2 and T4
are configured to alternately reload T3 on
opposite state transitions of T3OTL with the low
and high times of a PWM signal, this signal
can be constantly generated without software
intervention.

Table 6 : GPT1 timer input frequencies, resolution and periods

f

CPU

= 25MHz

Timer Input Selection T2I / T3I / T4I

000

B

001

B

010

B

011

B

100

B

101

B

110

B

111

B

Pre-scaler factor 8 16 32 64 128 256 512 1024
Input Frequency 3.125MHz 1.563MHz 781.3KHz 390.6KHz 195.3KHz 97.66KHz 48.83KHz 24.41KHz
Resolution 320ns 640ns 1.28µs 2.56µs5.12µs 10.24µs 20.48µs 40.96µs
Period 21.0ms 41.9ms 83.9ms 167ms 336ms 671ms 1.34s 2.68s

ST10R167

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IX.2 - GPT2

The GPT2 module provides precise event control
and timemeasurement. Itincludes two timers (T5,
T6) and a capture/reload register (CAPREL). Both
timers can be clocked with an input clock which is
derived from the CPU clock via a programmable
prescaler or with external signals. The count
direction (up/down) for each timer is programma­ble by software or may additionally be altered
dynamically by an external signal on a port pin
(TxEUD). Concatenation of the timers is sup­ported via the output toggle latch (T6OTL) of timer
T6 which changes its state on each timer over­flow/underflow.

The state of this latch may be used to clock timer
T5, orit may be output on a port pin (T6OUT). The
overflows/underflows of timer T6 can additionally
be used to clock the CAPCOM timers T0 or T1,
and to cause a reload from the CAPREL register.

The CAPREL register may capture the contentsof
timer T5 based on an external signal transition on
the corresponding port pin (CAPIN), and timer T5
may optionallybe cleared after the capture proce­dure. This allows absolute time differences to be
measured or pulse multiplication to be performed
without software overhead.

The capture trigger (timer T5 to CAPREL) may
also be generated upon transitions of GPT1 timer
T3 inputs T3IN and/or T3EUD. This is advanta­geous when T3 operates in Incremental Interface
Mode.

Table 7 lists thetimer input frequencies, resolution
and periods for each pre-scaler option at 25MHz
CPU clock.

This also applies to the Gated Timer Mode of T6
and to the auxiliary timer T5 in Timer and Gated
Timer Mode.

Figure 5 : Block diagram of GPT1

2nn=3...10

2nn=3...10

2nn=3...10

T2EUD

T2IN

CPU Clock

CPU Clock

CPU Clock

T3EUD

T4IN

T3IN

T4EUD

T2
Mode
Control

T3
Mode
Control

T4
Mode
Control

GPT1 Timer T2

GPT1 Timer T3

GPT1 Timer T4

T3OTL

Reload
Capture

U/D

U/D

Reload

Capture

Interrupt

Request

Interrupt

Request

Interrupt

Request

T3OUT

U/D

IX - GENERAL PURPOSE TIMER UNIT (continued)