SGS Thomson Microelectronics ST10F168 Datasheet
ST10F168
16-BIT MCU WITH 256K BYTE FLASH MEMORY AND 8K BYTE RAM
PRELIMINARY DATA
■ HIGH PERFORMANCE CPU
– 16-BIT CPU WITH 4-STAGE PIPELINE
– 80ns INSTRUCTION CYCLETIME AT25MHz CPU
CLOCK
– 400ns 16 X 16-BIT MULTIPLICATION
– 800ns 32 / 16-BIT DIVISION
– ENHANCED BOOLEAN BIT MANIPULATION FA-
CILITIES
– ADDITIONAL INSTRUCTIONS TOSUPPORT HLL
AND OPERATING SYSTEMS
– SINGLE-CYCLE CONTEXT SWITCHING SUP-
PORT
■ MEMORY ORGANIZATION
– 256K BYTE ON-CHIP FLASH MEMORY
– 1K ERASING / PROGRAMMING CYCLES
– UP TO 16M BYTE LINEAR ADDRESS SPACE
FOR CODE AND DATA (5M BYTE WITH CAN)
– 2K BYTE ON-CHIP INTERNAL RAM (IRAM)
– 6K BYTE ON-CHIP EXTENSION RAM (XRAM)
■ FAST AND FLEXIBLE BUS
– PROGRAMMABLE EXTERNAL BUSCHARACTE-
RISTICS FOR DIFFERENT ADDRESS RANGES
– 8-BIT OR16-BIT EXTERNAL DATA BUS
– MULTIPLEXED OR DEMULTIPLEXED EXTER-
NAL ADDRESS / DATA BUSES
– FIVE PROGRAMMABLE CHIP-SELECT SIGNALS
– HOLD-ACKNOWLEDGE BUS ARBITRATION
SUPPORT
■ INTERRUPT
– 8-CHANNEL PERIPHERAL EVENT CONTROL-
LER FOR SINGLE CYCLE, INTERRUPT DRIVEN
DATA TRANSFER
– 16-PRIORITY-LEVELINTERRUPTSYSTEMWITH
56 SOURCES, SAMPLE-RATE DOWN TO40ns
■ TIMERS
– TWO MULTI-FUNCTIONAL GENERAL PURPOSE
TIMER UNITS WITH 5 TIMERS
– TWO16-CHANNELCAPTURE/ COMPAREUNITS.
■ 4-CHANNEL PWM UNIT
■ SERIAL CHANNELS
– SYNCHRONOUS / ASYNCHRONOUS SERIAL
CHANNEL
– HIGH-SPEED SYNCHRONOUS CHANNEL
■ A/D CONVERTER
– 16-CHANNEL 10-BIT
– 7.76µS CONVERSIONTIME
■ FAIL-SAFE PROTECTION
– PROGRAMMABLE WATCHDOG TIMER
– OSCILLATOR WATCHDOG
■ ON-CHIP CAN 2.0B INTERFACE
■ ON-CHIP BOOTSTRAP LOADER
■ CLOCK GENERATION
– ON-CHIP PLL
– DIRECT OR PRESCALED CLOCK INPUT.
■ UP TO 111 GENERAL PURPOSE I/OLINES
– INDIVIDUALLY PROGRAMMABLE AS INPUT,
OUTPUT OR SPECIAL FUNCTION.
– PROGRAMMABLE THRESHOLD (HYSTERESIS)
■ IDLE AND POWER DOWN MODES
■ 144-PIN PQFP PACKAGE
FLASH
XRAM
CAN
P.0
P.1
P.4
P.6 P.5
PQFP144 (28 x 28 mm)
(Plastic Quad Flat Pack)
CPU Core
Interrupt controller
ADC
EBC
GPTs
BRG
P.3
ASC
PEC
SSC
BRG
RAM
Watchdog
OSC
PWM
CAPCOM1
CAPCOM2
P.7 P.8
P..2
This is advance information on a new product now in development or undergoing evaluation. Details are subject tochange without notice.
1/76March 2000
ST10F168
TABLE OF CONTENTS Page
1 INTRODUCTION......................................................................................................... 4
2 PIN DATA ................................................................................................................... 5
3 FUNCTIONAL DESCRIPTION.................................................................................... 10
4 MEMORY ORGANIZATION........................................................................................ 11
5 FLASH MEMORY................................................................................... .................... 13
5.1 PROGRAMMING / ERASING WITH ST EMBEDDED ALGORITHM KERNEL .......... 14
5.2 PROGRAMMING EXAMPLES .................................................................................... 16
5.3 FLASH MEMORY CONFIGURATION......................................................................... 18
5.4 FLASH PROTECTION............................... ................................................................. 18
5.5 BOOTSTRAP LEADER MODE................................................................................... 18
6 CENTRAL PROCESSING UNIT (CPU)...................................................................... 19
6.1 INSTRUCTION SET SUMMARY................................................................................. 20
7 EXTERNAL BUS CONTROLLER............................................................................... 22
8 INTERRUPT SYSTEM ................................................................................................ 23
9 CAPTURE / COMPARE (CAPCOM) UNIT................................................................. 26
10 GENERAL PURPOSE TIMER UNIT........................................................................... 28
10.1 GPT1 ........................................................................................................................... 28
10.2 GPT2 ........................................................................................................................... 28
11 PWM MODULE ................ ........................................................................................... 31
12 PARALLEL PORTS.................................................................................................... 32
13 A/D CONVERTER...................................... ................................................................. 33
14 SERIAL CHANNELS .............................................................................. .................... 34
15 CAN MODULE............................................................................................................ 36
16 WATCHDOG TIMER................................................................................................... 36
17 SYSTEM RESET......................................................................................................... 37
17.1 ASYNCHRONOUS RESET (LONG HARDWARE RESET) ........................................ 37
17.2 SYNCHRONOUS RESET (WARM RESET) ............................................................... 38
17.3 SOFTWARE RESET ................................................................................................... 39
17.4 WATCHDOG TIMER RESET..................................................................................... . 39
17.5 RESET CIRCUITRY................................................................................................... 39
2/76
ST10F168
18 POWER REDUCTION MODES .................................................................................. 43
19 SPECIAL FUNCTION REGISTER OVERVIEW.......................................................... 44
19.1 IDENTIFICATION REGISTERS .................................................................................. 50
20 ELECTRICAL CHARACTERISTICS ......................................................................... . 51
20.1 ABSOLUTE MAXIMUM RATINGS............. ................................................................. 51
20.2 PARAMETER INTERPRETATION.............................................................................. 51
20.3 DC CHARACTERISTICS............................................................................................ 51
20.4 A/D CONVERTER CHARACTERISTICS.................................................................... 54
20.5 AC CHARACTERISTICS............................................................................................. 55
20.5.1 Test Waveforms ........................................................................................................ 55
20.5.2 Definition of Internal Timing......................................................................................... 55
20.5.3 Clock Generation Modes............................................................................................. 56
20.5.4 Prescaler Operation..................................................................................................... 57
20.5.5 Direct Drive................................................................................................................. . 57
20.5.6 Oscillator Watchdog (OWD)........................................................................................ 57
20.5.7 Phase Locked Loop..................................................................................................... 57
20.5.8 External Clock Drive XTAL1....................... ................................................................. 58
20.5.9 Memory Cycle Variables.......................................................................... .................... 59
20.5.10 Multiplexed Bus ............................................................. ..............................................59
20.5.11 Demultiplexed Bus....................................................................................................... 65
20.5.12 CLKOUT and READY.............................................................................. .................... 71
20.5.13 External Bus Arbitration............................................................................................... 73
21 PACKAGE MECHANICAL DATA ................................ .............................................. 75
22 ORDERING INFORMATION....................................................................................... 75
3/76
ST10F168
1 - INTRODUCTION
The ST10F168 is a derivative of the ST Microelectronics 16-bit single-chip CMOS microcontrollers.
It combines high CPU performance (up to
12.5 million instructions per second) with high
Figure 1 : Logic Symbol
peripheral functionality and enhanced I/O capabilities. It also provides on-chip high-speed
Flash memory, on-chip high-speed RAM, and
clock generation via PLL.
XTAL1
XTAL2
RSTIN
RSTOUT
V
PP
V
AREF
V
AGND
NMI
EA
READY
ALE
RD
WR/WRL
Port 5
16-bit
V
DD
ST10F168
V
SS
Port 0
16-bit
Port 1
16-bit
Port 2
16-bit
Port 3
15-bit
Port 4
8-bit
Port 6
8-bit
Port 7
8-bit
Port 8
8-bit
4/76
2 - PIN DATA
Figure 2 : Pin Configuration (top view)
ST10F168
P6.0/CS0
P6.1/CS1
P6.2/CS2
P6.3/CS3
P6.4/CS4
P6.5/HOLD
P6.6/HLDA
P6.7/BREQ
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO
P8.5/CC21IO
P8.6/CC22IO
P8.7/CC23IO
V
DD
V
P7.0/POUT0
P7.1/POUT1
SS
P7.2/POUT2
P7.3/POUT3
P7.4/CC28I0
P7.5/CC29I0
P7.6/CC30I0
P7.7/CC31I0
P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.6/AN6
P5.7/AN7
P5.8/AN8
P5.9/AN9
VSSNMI
VDDRSTOUT
144
1
143
142
141
RSTIN
140
VSSXTAL1
XTAL2
VDDP1H.7/A15/CC27IO
137
139
138
136
135
P1H.6/A14/CC26IO
P1H.5/A13/CC25IO
P1H.4/A12/CC24IO
P1H.3/A11
P1H.2/A10
P1H.1/A9
P1H.0/A8
VSSVDDP1L.7/A7
134
133
132
131
130
129
128
127
126
P1L.6/A6
125
124
123
P1L.5/A5
P1L.4/A4
P1L.3/A3
122
121
P1L.2/A2
P1L.1/A1
P1L.0/A0
120
119
118
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
117
116
115
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
ST10F168
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
3738394041424344454647484950515253545556575859606162636465666768697071
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
P0H.1/AD9
114
113
112
111
VSSV
110
72
DD
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P0H.0/AD8
P0L.7/AD7
P0L.6/AD6
P0L.5/AD5
P0L.4/AD4
P0L.3/AD3
P0L.2AD2
P0L.1/AD1
P0L.0/AD0
EA
ALE
READY
WR/WRL
RD
V
SS
V
DD
P4.7/A23
P4.6/A22/CAN_TxD
P4.5/A21/CAN_RxD
P4.4/A20
P4.3/A19
P4.2/A18
P4.1/A17
P4.0/A16
V
/RPD
PP
V
SS
V
DD
P3.15/CLKOUT
P3.13/SCLK
P3.12/BHE/WRH
P3.11/RXD0
P3.10/TXD0
P3.9/MTSR
P3.8/MRST
P3.7/T2IN
P3.6/T3IN
AREF
AGND
V
V
P5.12/AN12/T6IN
P5.13/AN13/T5IN
P5.10/AN10/T6EUD
P5.11/AN11/T5EUD
SS
DD
V
V
P2.0/CC0IO
P2.1/CC1IO
P2.2/CC2IO
P2.3/CC3IO
P5.14/AN14/T4EUD
P5.15/AN15/T2EUD
V
P2.4/CC4IO
P2.5/CC5IO
P2.6/CC6IO
P2.7/CC7IO
SS
DD
V
P2.8/CC8IO/EX0IN
P2.9/CC9IO/EX1IN
P2.10/CC10IOEX2IN
P2.11/CC11IOEX3IN
P3.0/T0IN
P3.2/CAPIN
P3.1/T6OUT
P3.3/T3OUT
P2.12/CC12IO/EX4IN
P2.13/CC13IO/EX5IN
P2.14/CC14IO/EX6IN
P2.15/CC15IO/EX7IN/T7IN
SS
DD
V
V
P3.5/T4IN
P3.4/T3EUD
5/76
ST10F168
Table 1 : Pin Description
Symbol Pin Type Function
P6.0 - P6.7 1 - 8 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output viadirection bit.
Programming an I/O pin as input forces the corresponding output driver to high
impedance state. Port 6 outputs can be configured as push-pull or open drain
drivers. The following Port 6 pins have alternate functions:
1 O P6.0 CS0 Chip Select 0 Output
... ... ... ... ...
5 O P6.4 CS4 Chip Select 4 Output
6 I P6.5 HOLD External Master Hold Request Input
7 O P6.6 HLDA Hold Acknowledge Output
8 O P6.7 BREQ Bus Request Output
P8.0 - P8.7 9-16 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output viadirection bit.
9 I/O P8.0 CC16IO CAPCOM2: CC16 Capture Input / Compare Output
... ... ... ... ...
16 I/O P8.7 CC23IO CAPCOM2: CC23 Capture Input / Compare Output
P7.0 - P7.7 19-26 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit.
19 O P7.0 POUT0 PWM Channel 0 Output
... ... ... ... ...
22 O P7.3 POUT3 PWM Channel 3 Output
23 I/O P7.4 CC28IO CAPCOM2: CC28 Capture Input / Compare Output
... ... ... ... ...
26 I/O P7.7 CC31IO CAPCOM2: CC31 Capture Input / Compare Output
P5.0 - P5.9
P5.10 - P5.15
27-36
39-44
39 I P5.10 T6EUD GPT2 TimerT6 External Up / Down Control Input
40 I P5.11 T5EUD GPT2 TimerT5 External Up / Down Control Input
41 I P5.12 T6IN GPT2 Timer T6 Count Input
42 I P5.13 T5IN GPT2 Timer T5 Count Input
43 I P5.14 T4EUD GPT1 TimerT4 External Up / Down Control Input
44 I P5.15 T2EUD GPT1 TimerT2 External Up / Down Control Input
Programming an I/O pin as input forces the corresponding output driver to high
impedance state. Port 8 outputs can be configured as push-pull or open drain
drivers. The input threshold of Port 8 is selectable (TTL or special).
The following Port 8 pins have alternate functions:
Programming an I/O pin as input forces the corresponding output driver to high
impedance state. Port 7 outputs can be configured as push-pull or open drain
drivers. The input threshold of Port 7 is selectable (TTL or special).
The following Port 7 pins have alternate functions:
II16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can be
the analog input channels (up to 16) for the A/D converter, where P5.x equals ANx
(Analog input channel x), or they are timer inputs:
6/76
Table 1 : Pin Description (continued)
Symbol Pin Type Function
ST10F168
P2.0 - P2.7
P2.8 - P2.15
P3.0 - P3.5
P3.6 - P3.13,
P3.15
47-54
57-64
47 I/O P2.0 CC0IO CAPCOM: CC0 Capture Input / Compare Output
... ... ... ... ...
54 I/O P2.7 CC7IO CAPCOM: CC7 Capture Input / Compare Output
57 I/O P2.8 CC8IO CAPCOM: CC8 Capture Input / Compare Output
... ... ... ... ...
64 I/O P2.15 CC15IO CAPCOM: CC15 Capture Input / Compare Output
65-70,
73-80,
81
65 I P3.0 T0IN CAPCOM Timer T0 Count Input
66 O P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output
67 I P3.2 CAPIN GPT2 Register CAPREL Capture Input
68 O P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output
69 I P3.4 T3EUD GPT1 Timer T3 External Up /Down Control Input
70 I P3.5 T4IN GPT1 Timer T4 Input for Count / Gate / Reload / Capture
73 I P3.6 T3IN GPT1 Timer T3 Count / Gate Input
74 I P3.7 T2IN GPT1 Timer T2 Input for Count / Gate / Reload / Capture
75 I/O P3.8 MRST SSC Master-Receiver / Slave-Transmitter I/O
76 I/O P3.9 MTSR SSC Master-Transmitter / Slave-Receiver O/I
77 O P3.10 TxD0 ASC0 Clock / Data Output (Asynchronous / Synchronous)
78 I/O P3.11 RxD0 ASC0 Data Input (Asynchronous) or I/O (Synchronous)
79 O P3.12 BHE External Memory High Byte Enable Signal
80 I/O P3.13 SCLK SSC Master Clock Output / Slave Clock Input
81 O P3.15 CLKOUT System Clock Output (=CPU Clock)
I/O 16-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to high
impedance state. Port 2 outputs can be configured as push-pull or open drain
drivers. The input threshold of Port 2 is selectable (TTL or special).
The following Port 2 pins have alternate functions:
I EX0IN Fast External Interrupt 0 Input
I EX7IN Fast External Interrupt 7 Input
I T7IN CAPCOM2 TimerT7 Count Input
I/O
15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or
I/O
output via direction bit. Programming an I/O pin as input forces the corresponding
I/O
output driver to high impedance state. Port 3 outputs can be configured as push-pull
or open drain drivers. The input threshold of Port 3 is selectable (TTL or special).
The following Port 3 pins have alternate functions:
WRH External Memory High Byte Write Strobe
7/76
ST10F168
Table 1 : Pin Description (continued)
Symbol Pin Type Function
P4.0 - P4.7 85-92 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit.
Programming an I/O pin as input forces the corresponding output driver to high
impedance state. For external bus configuration, Port 4 can be used to output the
segment address lines:
85-89 O P4.0-P4.4 A16-A20 Segment Address Line
90 O P4.5 A21 Segment Address Line
I CAN_RxD CAN Receiver Data Input
91 O P4.6 A22 Segment Address Line
O CAN_TxD CAN Transmitter Data Output
92 O P4.7 A23 Most Significant Segment Addrress Line
RD 95 O External Memory Read Strobe. RD is activated for every external instruction or data
WR/WRL 96 O External Memory Write Strobe. In WR-mode this pin is activated for every external
READY/
READY
ALE 98 O Address Latch Enable Output. In case of use of external addressing or of multi-
EA 99 I External Access Enable pin. A low level at this pin during and after Reset forces the
P0L.0 - P0L.7
P0H.0
P0H.1 - P0H.7
97 I Ready Input. The active level is programmable. When the Ready function is
100 - 107,
108,
111 - 117
read access.
data write access. In WRL mode this pin is activated for low Byte data write
accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See
WRCFG in the SYSCON register for mode selection.
enabled, the selected inactive level at this pin, during an external memory access,
will force the insertion of wait state cycles until the pin returns to the selected active
level.
plexed mode, this signal is the latch command of the address lines.
ST10F168 to start the program in internal memory space. A high level forces the
ST10F168 to start in the external memory space.
I/O Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state.
In case of an external bus configuration, Port0 serves as the address (A) and as the
address / data (AD)bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.
8/76
Demultiplexed bus modes
Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: D0 – D7 D0 - D7
P0H.0 – P0H.7: I/O D8 - D15
Multiplexed bus modes
Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7
P0H.0 – P0H.7: A8 – A15 AD8 – AD15
Table 1 : Pin Description (continued)
Symbol Pin Type Function
ST10F168
P1L.0 - P1L.7
P1H.0 - P1H.7
118-125
128-135
I/O Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. Port1 is used as the 16-bit address bus (A) in
demultiplexed bus modes and also after switching from a demultiplexed bus mode
to a multiplexed bus mode.
The following Port1 pins have alternate functions:
132 I P1H.4 CC24IO CAPCOM2: CC24 Capture Input
133 I P1H.5 CC25IO CAPCOM2: CC25 Capture Input
134 I P1H.6 CC26IO CAPCOM2: CC26 Capture Input
135 I P1H.7 CC27IO CAPCOM2: CC27 Capture Input
XTAL1 138 I XTAL1 Oscillator amplifier and internal clock generator input
XTAL2 137 O XTAL2: Oscillator amplifier circuit output.
To clock the device from an external source, drive XTAL1 while leaving XTAL2
unconnected. Minimum and maximum high / low and rise / fall times specified in the
AC Characteristics must be observed.
RSTIN 140 I Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified
duration while the oscillator is running resets the ST10F168. An internal pullup
resistor permits power-on reset using only a capacitor connected to V
. In bidirec-
SS
tional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the
RSTIN line is pulled low for the duration of the internal reset sequence.
RSTOUT 141 O Internal Reset Indication Output. This pin is set to a low level during hardware, soft-
ware or watchdog timer reset.
RSTOUT remains low until the EINIT (end of initial-
ization) instruction is executed.
NMI 142 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to
vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the
PWRDN (power down) instruction is executed, the NMI pin must be low in order to
force the ST10F168 to go into power down mode. If NMIis high and PWDCFG =’0’,
when PWRDN is executed, the part will continue to run in normal mode.
If it is not used, pin NMI should be pulled high externally.
V
AREF
V
AGND
V
/RPD 84 - Flash programming voltage. Programming voltage of the on-chip Flash memory
PP
37 - A/D converter reference voltage.
38 - A/D converter reference ground.
must be supplied to this pin.
It is used also as the timing pin for the return from interruptible powerdown mode.
V
DD
17,46,
56,72,
82,93,
109, 126,
Digital Supply Voltage:
= + 5V during normal operation and idle mode.
> 2.5V during power down mode.
136, 144
V
SS
18,45,
55,71,
83,94,
Digital Ground.
110, 127,
139, 143
9/76
ST10F168
3 - FUNCTIONAL DESCRIPTION
The architecture of the ST10F168 combines
advantages of both RISC and CISC processors
and an advanced peripheral subsystem.
Figure 3 : Block Diagram
256KByte
Flash
memory
32
The block diagram gives an overview of the
different on-chip components and the high
bandwidth internal bus structure of the ST10F168.
16
CPU-Core
16
Internal
RAM
CAN_RxD P4.5
CAN_TxDP4.6
6K Byte
XRAM
CAN
16
16
8
Port0Port1Port4
Port 6
8
Controller
ExternalBus
16
10-BitADC
Port 5
16
16
Interrupt Controller
GPT1
GPT2
BRG
Port 3
PEC
16
ASCusart
15 8 8
SSC
BRG
PWM
CAPCOM2
Port7
Watchdog
OSC.
+PLL
CAPCOM1
Port 8
Port2
XTAL1
XTAL2
16
10/76
4 - MEMORY ORGANIZATION
The memory space of the ST10F168 is configured
in a Von Neumann architecture. Code memory,
data memory, registers and I/O ports are organized within the same linear address space of
16M Byte. The entire memory space can be
accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally
been made directly bit addressable.
FLASH: 256K Byte of on-chip Flash memory. See
Flash Memory
on page13
IRAM: 2K Byte of on-chip internal RAM
(dual-port) is provided as a storage for data, system stack, general purpose register banks and
code. A register bank is 16 wordwide (R0 to R15)
and / or bytewide (RL0, RH0, …, RL7, RH7) general purpose registers.
XRAM: 6K Byte of on-chip extension RAM (single
port XRAM) is provided asa storage for data, user
stack and code. The XRAM is connected to the
internal XBUS and is accessed like an external
memory in16-bit demultiplexed bus-mode without
wait state or read / write delay (80ns access at
25MHz CPU clock). Byte and Word access are
allowed.
The XRAM address range is 00’D000h 00’E7FFh if the XRAM is enabled (XPEN bit 2 of
SYSCON register). As the XRAM appears like
external memory, it cannot be used for the
ST10F168’s system stack or register banks. The
XRAM is not provided for single bit storage and
ST10F168
therefore is not bit addressable. If bit XPEN is
cleared, then any access in the address range
00’D000h - 00’E7FFh will be directed to external
memory interface, using the BUSCONx register
corresponding to address matching ADDRSELx
register.
SFR/ESFR: 1024 Byte (2 x 512 Byte) of address
space is reserved for the Special Function Register areas. SFRs are wordwide registers which are
used for controlling and monitoring functions of
the different on-chip units.
CAN: Address range 00’EF00h - 00’EFFFh is
reserved for the CAN Module access. The CAN is
enabled by setting XPEN bit 2 of the SYSCON
register. Accesses to the CANModule use demultiplexed addresses and a 16-bit data bus (Byte
accesses are possible). Two wait states give an
access time of 160ns at 25MHz CPU clock. No
tristate wait state is used.
Note If the CAN module is used, Port 4 can not
be programmed to output all 8 segment
address lines. Therefore, only 4 segment
address lines can be used, reducing the
external memory space to 5M Byte (1M
Byte per CS line)
To meet the needs of designs where more memory is requiredthan is provided on chip, up to 16M
Byte of external RAM and / or ROM can be connected to the microcontroller.
11/76
ST10F168
Figure 4 : ST10F168 on-chip memory mapping
0x5’00000x14
0x4’FFFF
0x4’C0000x13
0x4’80000x12
Segment 4Segment 3Segment 2Segment 1Segment 0
0x4’40000x11
0x4’00000x10
0x3’C0000x0F
0x3’80000x0E
0x3’7FFF
0x3’40000x0D
0x3’00000x0C
0x2’C0000x0B
0x2’80000x0A
0x2’40000x09
0x2’00000x08
0x1’FFFF
0x1’C0000x07
0x1’80000x06
0x1’7FFF
0x1’40000x05
0x1’3FFF
0x04
0x1’0000
Bank 3 : 96K Byte
Bank 2 : 96K Byte
Bank 1H : 32K Byte
Bank 1L : 16K Byte
Bank 0 : 16K Byte
RAM, SFR and X-pheripherals are
mapped into the address space.
SYSCON.XPEN=1enables CAN
and XRAM (before EINIT)
0x0’FFFF
SFR Area
0x0’FE00
0x0’FDFF
IRAM : 2K Byte
0x0’F600
0x0’EFFF
CAN Module
0x0’EF00
0x02 0x0’8000
0x0’7FFF
0x0’40000x01
0x0’3FFF
0x00
Data
Page
Number
0x0’0000
Absolut
Memory
Address
Bank 1L : 16K Byte
Bank 0 : 16K Byte
0x0’E7FF
XRAM : 6K Byte
0x0’D000
* Bank 0 and Bank 1 L may be remapped from segment 0
to segment 1 by setting SYSCON.ROMS1 (before EINIT)
12/76
5 - FLASH MEMORY
The ST10F168 provides 256K Byte of an
electrically erasable and reprogrammable Flash
Memory on-chip.
The Flash Memory can be used both forcode and
data storage. It is organized into four 32-bit wide
blocks allowing even double Word instructions to
be fetched in one machine cycle. The four blocks
of size16K, 48K,96K and 96KByte can be erased
and reprogrammed individually (see Table 2 and
Table 3).
The Flash Memory can be programmed in a programming board or in the target system which
provides high system flexibility. The algorithms to
program or erase the flash memory are embedded in the Flash Memory itself (ST Embedded
Algorithm Kernel, or STEAKTM).
To start a program / erase operation, the user’s
software has just to load GPRs with the address
and data to be programmed, or sector to be
erased. STEAK uses embedded routines, which
ST10F168
check the validity of the programmed parameters,
decode and then execute the programming or
erase command. During operation, the STEAK
routines carry out checks and retries to verify
proper cell programming or erasing. When an
error occurs, STEAK returns an error-code which
identifies the cause of the error.
A Flash Memory protection option prevents the
read-back of the Flash Memory contents from
external memory, or from on-chip RAM. Code
operation from within the Flash continues as normal.
The first bank (16K Byte) and part of the second
bank (16K Byte out of 48K Byte) of the on-chip
Flash Memory of the ST10F168 can be mapped
to either segment 0 (addresses 00000h to
07FFFh) or to segment 1 (addresses 10000h to
17FFFh) during the initialization phase. External
memory can be used for additional system
flexibility.
VDD=5V±10%, VPP=12V ± 5%, VSS=0V,f
= 25MHz, for Q6 version : TA=-40, +85°C and for Q2
CPU
version TA = -40, +125°C.
Table 2 : Flash Memory Characteristics
Symbol Parameter Test Conditions Min. Typ. Max. Unit
CPU Frequency during
CPU
erasing / programming operation
= 25MHz
Erasing /Programming Cycles
Single Word Programming Time
Double Word Programming Time
Sector Erasing Time
Data Retention Time Defectivity below 1ppm / year
RET
1. Typical value for a non cycled flash. Maximum value is a software limit put inside STEAK. Can be changed after flash
characterization by STMicroelectronics.
f
CPU
f
CPU
f
CPU
f
CPU
= 25MHz
= 25MHz
= 25MHz
Note
f
Cyc
t
SPRG
t
DPRG
t
EBNK
t
5 - 25 MHz
--
-10
-10
-0.8
10 - - year
1000
80
80
60
1
1
1
1
Table 3 : Flash Memory Bank Organisation
Bank Addresses (segment 0) Addresses (segment 1) Size (Byte)
0
000000h to 003FFFh
1
004000h to 007FFFh + 018000h to 01FFFFh
2
020000h to 037FFFh
3
038000h to 04FFFFh
010000h to 013FFFh
014000h to 01FFFFh
020000h to 03FFFFh
038000h to 04FFFFh
16K
48K
96K
96K
µs
µs
s
13/76
ST10F168
5.1 - Programming / Erasing with ST
Embedded Algorithm Kernel
There are three stages to run STEAK :
– To load the registers R0 to R4 with the STEAK
command, the address and the data to be programed, or sector to be erased. Table 4 gives
the STEAK parameters for each type of Flash
programming / erasing operation. Table 5 defines the codes used in Table 4.
– To initiatethe Unlock Sequence.The Unlock Se-
quence is composed of two consecutive writes
to an even address in the Flash active address
space - the first write has direct addressing
mode (MOV mem, Rwn) - the second write has
– To read the return values in R0. When the em-
bedded programming / erasing algorithm returns to trigger point, return values are given in
R0. Table 6 gives the error-code definitions,
Table 7 gives the return values in each register
for each type of Flash programming / erasing
command.
Note The Flash Embedded STEAK Algorithms
require at least 50 words on the Internal
System Stack. STEAK verifies that there is
enough free space on the System Stack,
before performing a programming or erasing operation.The MDH, MDL and MDC
register content are modified.
indirect addressing mode (MOV [Rwm], Rwn).
Rwn can be any unused Word-GPR (R6to R15)
loaded with a value resulting in the same even
address as “mem”.
Code examples for programming and erasing the
Flash Memory using STEAK are given in
Section 5.2.
Table 4 : STEAK parameters
Command R0 R1 R2 R3 R4
Single Word programming 55Ash AddOff W nu 2TCL
Double Word programming DD4sh AddOff DWL DWH 2TCL
Multiple (block) programming AA5sh BegAddOff EndAddOff SourceAddr 2TCL
Sector Erasing EEEEh 5555h Bnk Bnk 2TCL
Read Status 7777h nu nu nu 2TCL
Table 5 : Programming / erasing code definition
s Segment of the Target Flash Memory cell,
AddOff Segment Offset of the Target Flash Memory cell. Must be even value (Word-aligned address).
W Data (Word) to be written in Flash.
DWL,DWH Data (double Word, DHL = low Word, DWH = high Word) to be written in Flash.
BegAddOff
EndAddOff
SourceAdd
Bnk Number of the Bank to be erased. For security, R2 and R3 must hold the same value.
2TCL CPU clock period innano-seconds (eg. R4 = 50d means CPU frequency is 20MHz).
Segment Offset of the FIRST Target Flash Memory Word to be written in a Multiple programming
command. Must be even value (Word-aligned address).
Segment Offset of the LAST Target Flash Memory Word to be written in a Multiple programming
command.
Must be even value (Word-aligned address). The value D = (EndAddOff - BegAddOff) must be: 0 <= D <
16384 (ie. up to one page (16K Byte) can be written in the flash with one multi-Word programming
command).
Start address for the block to be programmed.
This address is using implicitly the data paging mechanism of the CPU. SourceAdd value must respect
the following rules :
- SourceAdd + (EndAddOff - BegAddOff) < 16384.
- Page 0 and 1can NOT be used for source data if bit ROMS1 = ‘1’ (in SYSCON register).
Note that source data can be located in Flash (In pages 0, 1, 6 to 19 if bit ROMS1 = ‘0’, or in pages 4 to19
if bit ROMS1 = ‘1’).
14/76
Table 6 : Error Code Definition (R0 content after STEAK execution)
Error Code Meaning
00h Operation was successful
01h Flash Protection is active
02h Vpp voltage not present
03h Programming operation failed
04h Address value (R1) incorrect: not in Flash address area or odd
05h CPU period out of range (must be between 30 ns to 500 ns)
06h Not enough free space on system stack for proper operation
07h Incorrect bank number (R2,R3) specified
08h Erase operation failed (phase 1)
09h Bad source address for Multiple Word programming command
0Ah Bad number of words to be copied in Multiple Word programming command: one destination will be
out of flash.
0Bh PLL Unlocked or Oscillator watchdog overflow occured during programming or erasing the flash.
0Ch Erase operation failed (phase 2)
FFh Unknown or bad command
ST10F168
Table 7 : Return values for each programming / erase command
Programming
Command
Single or
double Word
programming
Block
programming
Erasing Error
After status
read
Note The Flash Embedded STEAK Algorithms
require at least 50 words on the Internal
System Stack for proper operation. The
program itself verifies that there is enough
free space on the System Stack before
performing a programming or erasing
operation, by computing the Word number
between Stack Pointer (SP) and Stack
Overflow register (STKOV ).
The MDH, MDL and MDC register content
are modified.
Registers R0 to R4 are used as Input Data
for STEAK, and are modified as explained
R0 R1 R2 R3 R4-R15
Error
code
Error
The last segment offset address of the
code
last written Word in Flash (failing Flash
address if R0 is not equal to zero)
code
Error
Flash embedded rev
code
MSByte = major release
LSByte = minor revision
Unchanged Data in Flash for
location Segment +
Segment Offset
(R0.[3:0] with R1)
Undefined Unchanged
Undefined Unchanged
Circuit identifiers :
R2 = #0787h
R3 = #0101h for this device
above (Return Values).
Registers R5 to R15 are used internally by
STEAK, but preserved on entry and
restore on exit of STEAK.
IT IS VERY IMPORTANT TO TAKE INTO
ACCOUNT THE FACT THAT STEAK
USES UP TO 50 WORDS ON THE SYSTEM STACK. TO PREVENT ANY
ABNORMAL SITUATION, IT IS VERY
IMPORTANT TO INITIALIZE CORRECTLY THE STACKSIZE TO AT LEAST
64 WORDS, AND TO CORRECTLY INITIALIZE REGISTER STKOV.
Data in Flash for
location Segment +
Segment Offset + 2
(R0[3:0] with R1+2)
Unchanged
Unchanged
15/76
ST10F168
5.2 - Programming Examples
Programming a double Word
; code shown below assumes that Flash is mapped in segment 1
; ie. bit ROMS1 = ‘1’ in SYSCON register
; Flash must be enabled, ie. bit ROMEN = ‘1’ in SYSCON.
MOV R0, #0DD40h ; DD4xh : Double Word programming command
OR R0, #01h ; Selects segment 1 in flash memory
MOV R1, #00224h ; Address to be programmed is 01’0224h
MOV R2, #03456h ; Data to be programmed at 01’0224h
MOV R3, #04567h ; Data to be programmed at 01’0226h
MOV R4, #050d ; 50ns is 20MHz CPU clock frequency
MOV R7, #08000h ; R7 used for Flash trigger sequence
#define FCR 08000h
; Flash Unlock Sequence consists in two consecutive writes, with the direct
addressing mode and then the indirect addressing mode. FCR must represent an
even address in the active address space of the Flash memory, and Rwn can be
any unused Word GPR (R6 to R15)loaded with a value resulting in the same even
address than FCR
EXTS #1, #2 ; Flash can be mapped in segment 0 or 1
MOV FCR, R7 ; first part
MOV [R7], R7 ; second part
NOP ; WARNING: place 2 NOP operations after
NOP ; the Unlock sequence to avoid all possible
; pipeline conflicts in STEAK programs
Note For easier coding, the standard data paging addressing scheme is overriden for the two MOV
instructions of the Flash Trigger Sequence (EXTS instruction). However this coding also locks
both standard and PEC interrupts and class A hardware traps. This override can be replaced by
an ATOMIC instruction if thestandard DPP addressing scheme must be preserved.
16/76
ST10F168
Programming a block of data
The following code is provided as an example to program ablock of data. Flash to be programmed is from
address 01’9000h to 01’9FFEh (included). Source data (data to be copied into flash)is located in external
RAM from address 05’1000h (to 05’1FFEh, implicitly) :
; code shown below assumes that flash is mapped in segment 1
; ie. bit ROMS1 = ‘1’ in SYSCON register
; Flash must be enabled, ie. bit ROMEN = ‘1’ in SYSCON.
MOV R0, #0AA50h ; AA5xh : Multi Word programming command
OR R0, #01h ; Selects segment 1 in Flash memory
MOV R1, #09000h ; First Flash Segment Offset Address
MOV R2, #09FFEh ; Last Flash Segment Offset Address
MOV R3, #09000h ; Source data address: use DPP2 as
; data page pointer
SCXT DPP2,#20d ; Source is in page 20 (first page of
; segment 5): save previous DPP2 value
; and load it with source page number
MOV R4, #050d ; 50ns is 20MHz CPU clock frequency
MOV R7, #08000h ; R7 used for Flash trigger sequence
#define FCR 08000h
EXTS #1, #2 ; Flash can be mapped in segment 0 or 1
MOV FCR, R7 ; first part
MOV [R7], R7 ; second part
NOP ; WARNING: place 2 NOP operations after
NOP ; the Unlock sequence to avoid all possible
; pipeline conflicts in STEAK programs
POP DPP2 ; restore DPP2
17/76
ST10F168
5.3 - Flash Memory Configuration
The default memory configuration of the
ST10F168 Memory is determined by the state of
the EA pin at reset. This value is stored in the
Internal ROM Enable bit : ROMEN of the
SYSCON Register.
When ROMEN = 0, the internal FLASH is disabled
and external ROM is used for startup control.
Flash memory can be enabled later by setting the
ROMEN bit of SYSCON to 1. Ensure that the
code which performs this setting is NOT running
from external ROM in a segment that will be
replaced by FLASH memory, otherwise unexpected behaviour may occur.
For example, if the external ROM code is located
in the first 32K Byte of segment 0, the first
32K Byte of the FLASH must then be enabled in
segment 1. This is done by setting the ROMS1 bit
of SYSCON to 0, before or simultaneously with
setting the ROMEN bit. This must be done in the
externally supplied program, before the execution
of the EINIT instruction. If program execution
starts from external memory, but the Flash memory mapped in segment 0 is accessed later, then
the code that sets the ROMEN bit must be executed either in segment 0 but above address
00’8000h, or from the internal RAM.
Bit ROMS1 only affects the mapping of the first
32K Byte of the Flash memory. All other parts of
the Flash memory (addresses 01’8000h 04’FFFFh) remain unaffected.
Note: TheSGTDIS Segmentation Disable / Enable
must also be set to 0 to enable the use of the full
256K Byte of on-chip memory in addition to the
external boot memory. The correct procedure for
changing the segmentation registers must be
observed to prevent an unwanted trap condition :
– Instructions that configure the internal memory
must onlybe executed from external memoryor
from the internal RAM.
– An Absolute Inter-Segment Jump (JMPS)
instructionmust beexecuted after Flash enabling,
before the next instruction, even if the next
instruction is locatedin the consecutive address.
– Whenever the internalmemory is disabled, ena-
bled or remapped, the DPPs must be explicitly
(re)loaded to enable correct data accesses to
the internal memory and / or external memory.
5.4 - Flash Protection
If Flash Protection is active, data operands in the
on-chip Flash Memory area can only be read by a
program executed from the Flash Memory itself.
Program branches from or into the on-chip Flash
memory are possible in the Flash protection mode.
Erasing and programming of the Flash memory is
not possible as long as protection is active.
Flash protection is controlled by the Protection
UPROM Programming Bit (UPROG). UPROG is a
’hidden’ one-time programmable bit only accessible in a special mode which can be entered via a
Flash EPROM programming board for example. If
UPROG is set to ”1”, Flash protection is active
after reset. By default Flash Protection is disabled
(UPROG=0).
When flash protection is active (the default after
reset if UPROG bit is set), then any read accessin
the flash by a code executed from external or
internal RAM (IRAM or XRAM) will return the
value 0B88Bh. Any call of STEAK will return the
error code ‘01’ (Protected flash).
Normally Flash protection should never be deactivated, once activated. If this has to be done, for
example because the Flash memory has to be
reprogrammed with updated program / variables,
a zero value has to be written at any even address
in the active address space of the Flash memory.
This write can be done only by an instruction executed from the internal Flash Memory itself.
For example:
MOV FLASH,ZEROS ; Deactivate Flash
Protection.
; Flash is any even address in Flash
memory space. This instruction MUST
be executed from Flash memory itself.
After this instruction, the flash is temporarily
de-protected, thus any read access of the flash
from code executed from external memory or
internal RAMs will be correctly executed, and calls
of STEAK can be correctly performed (programming, erasing or status reading).
Notes 1. That all STEAK commands re-activate
the flash protection if bit UPROG is set
when completed.
2. Currently the only way to program the
UPROG one-time programmable bit is by
using an external ST10F167 / ST10F168
EPB kit.
5.5 - Bootstrap Leader Mode
Pin P0L.4 (BSL) activates the on-chip bootstrap
loader, when low during hardware reset. The
bootstrap loader allows moving the start code into
the internal RAM of the ST10F168 via the serial
interface ASC0. The ST10F168 will remain in
bootstrap loader mode until a hardware reset with
P0L.4 high or a software reset. The bootstraps
loader acknowledge byte is D5h.
18/76
6 - CENTRAL PROCESSING UNIT (CPU)
The CPU includes a4-stage instruction pipeline, a
16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been added
for a separate multiply and divide unit, a bit-mask
generator and a barrel shifter.
Most of the ST10F168’s instructions can be executed in one instruction cycle which requires 80ns
at 25MHz CPU clock. For example, shift and
rotate instructions are processed in one instruction cycle independent of the number of bit to be
shifted. Multiple-cycle instructionshave been optimized: branches are carried out in 2 cycles, 16 x
16-bit multiplication in 5 cycles and a 32/16 bit
division in 10 cycles.The jump cache reduces the
execution timeof repeatedly performed jumps in a
loop, from 2 cycles to 1 cycle.
Figure 5 : CPU Block Diagram
ST10F168
The CPU uses a bank of 16 word registers to run
the current context. This bank of General Purpose
Registers (GPR) is physically stored within the
on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU. The
number of register banks is only restricted by the
available internal RAM space. Foreasy parameter
passing, one register bank may overlap others.
A system stack of up to 2048 Byte stores temporary data. The system stack is allocated in the
on-chip RAM area, and it is accessed by the CPU
via the stack pointer (SP) register. Two separate
SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value on each
stack access, for the detection of a stack overflow
or underflow.
256K Byte
Flash
memory
32
SP
STKOV
STKUN
Exec. Unit
Instr. Ptr
Instr. Reg
4-Stage
Pipeline
PSW
SYSCON
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
Data Pg. Ptrs
CPU
MDH
MLD
Mul./Div.-HW
Bit-Mask Gen.
ALU
16-Bit
Barrel-Shift
CP
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Code Seg. Ptr.
R15
General
Purpose
Registers
R0
16
16
Internal
RAM
2K Byte
Bank
n
Bank
i
Bank
0
19/76
ST10F168
6.1 - Instruction Set Summary
The Table8 liststhe instructions of the ST10F168.
The various addressing modes, instruction operation, parameters for conditional execution of
Table 8 : Instruction set summary
Mnemonic Description Bytes
ADD(B) Add Word (Byte) operands 2 / 4
ADDC(B) Add Word (Byte) operands with Carry 2 / 4
SUB(B) Subtract Word (Byte) operands 2 / 4
SUBC(B) Subtract Word (Byte) operands with Carry 2 / 4
MUL(U) (Un)Signed multiply direct GPRby direct GPR (16 x 16-bit) 2
DIV(U) (Un)Signed divide register MDL by direct GPR (16 / 16-bit) 2
DIVL(U) (Un)Signed long divide register MD by direct GPR (32 / 16-bit) 2
CPL(B) Complement direct Word (Byte) GPR 2
NEG(B) Negate direct Word (Byte) GPR 2
AND(B) Bitwise AND, (Word / Byte operands) 2 / 4
OR(B) Bitwise OR, (Word / Byte operands) 2 / 4
XOR(B) Bitwise XOR, (Word / Byte operands) 2 / 4
BCLR Clear direct bit 2
BSET Set direct bit 2
BMOV(N) Move (negated) direct bit to direct bit 4
BAND, BOR, BXOR AND / OR / XOR direct bit with direct bit 4
BCMP Compare direct bit to direct bit 4
BFLDH/L Bitwise modify masked high / low Byte of bit-addressable direct Word memory with
immediate data
CMP(B) Compare Word (Byte) operands 2 / 4
CMPD1/2 Compare Word data to GPR and decrement GPR by 1/2 2 / 4
CMPI1/2 Compare Word data to GPR and increment GPR by 1/2 2 / 4
PRIOR Determine number of shift cycles to normalize direct Word GPR and store result in
direct Word GPR
SHL/SHR Shift left / right direct Word GPR 2
ROL/ROR Rotate left / right direct Word GPR 2
ASHR Arithmetic (sign bit) shift right direct Word GPR 2
MOV(B) Move Word (Byte) data 2 / 4
MOVBS Move Byte operand to Word operand with sign extension 2 / 4
MOVBZ Move Byte operand to Word operand. with zero extension 2 / 4
JMPA, JMPI, JMPR Jump absolute / indirect / relative if condition ismet 4
JMPS Jump absolute to a code segment 4
J(N)B Jump relative if direct bit is (not) set 4
JBC Jump relative and clear bit if direct bit is set 4
instructions, opcodes and a detailed description of
each instructioncan be found in the“ST10 Family
Programming Manual”.
4
2
20/76
ST10F168
Table 8 : Instruction set summary
Mnemonic Description Bytes
JNBS Jump relative and set bit if direct bit is not set 4
CALLA, CALLI, CALLR Call absolute / indirect / relative subroutine if condition is met 4
CALLS Call absolute subroutine in any code segment 4
PCALL Push direct Word register onto system stack and call absolute subroutine 4
TRAP Call interrupt service routine via immediate trap number 2
PUSH, POP Push / pop direct Word register onto / from system stack 2
SCXT
RET Return from intra-segment subroutine 2
RETS Return from inter-segment subroutine 2
RETP Return from intra-segment subroutine and pop direct Word register from system
RETI Return from interrupt service subroutine 2
SRST Software Reset 4
IDLE Enter Idle Mode 4
PWRDN Enter Power Down Mode (supposes NMI-pin being low) 4
SRVWDT Service Watchdog Timer 4
DISWDT Disable Watchdog Timer 4
EINIT
ATOMIC Begin ATOMIC sequence 2
EXTR Begin EXTended Register sequence 2
EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4
EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4
NOP Null operation 2
Push direct Word register onto system stack and update register with Word operand 4
stack
Signify End-of-Initialization on
RSTOUT-pin
2
4
21/76
ST10F168
7 - EXTERNAL BUS CONTROLLER
All external memory accesses are performed by
the on-chip external bus controller. The EBC can
be programmed to single chip mode when no
external memory is required, or to one of four different external memory access modes :
– 16 / 18 / 20 / 24-bit addresses and 16-bit data,
demultiplexed.
– 16 / 18 / 20 / 24-bit addresses and 16-bit data,
multiplexed.
– 16 / 18 / 20 / 24-bit addresses and 8-bit data,
multiplexed.
– 16 / 18 / 20 / 24-bit addresses and 8-bit data,
demultiplexed.
In demultiplexed busmodes addresses areoutput
on Port1 and data are input / output on Port0 or
P0L, respectively. In the multiplexed bus modes
both addresses and data use Port0 for input/ output.
Timing characteristics of the external bus interface (memory cycle time, memory tri-state time,
length of ALE and read / write delay) areprogrammable giving the choice of a wide range of memories and external peripherals.Up to 4 independent
address windows may be defined (using register
pairs ADDRSELx / BUSCONx) to access different
resources and bus characteristics. These address
windows are arranged hierarchically where
BUSCON4 overrides BUSCON3 and BUSCON2
overrides BUSCON1. All accesses to locations
not covered by these 4 address windows are controlled by BUSCON0. Up to 5 external CS signals
(4 windows plus default) can be generated in
order to save external glue logic. Access to very
slow memories is supported by a ‘Ready’ function.
A HOLD/HLDA protocol is available for bus arbitration which shares external resources with other
bus masters. The bus arbitration is enabled by
setting bit HLDEN in register SYSCON. After setting HLDEN once, pins P6.7...P6.5 (BREQ,
HLDA, HOLD) are automatically controlled by the
EBC. In master mode (default after reset) the
HLDA pin is an output. By setting bit DP6.7 to’1’
the slave mode is selected where pin HLDA is
switched to input. This directly connects the slave
controller to another master controller without
glue logic.
For applications which require less external
memory space, the address space can be
restricted to 1M Byte, 256K Byte or to 64K Byte.
Port4 outputs all 8 address lines if an address
space of 16M Byte is used, otherwise four, two or
no address lines.
Chip select timingcan be programmed. By default
(after reset), the CSx lines change half a CPU
clock cycle after the rising edge of ALE. With the
CSCFG bit set in the SYSCON register the CSx
lines can change with the rising edge of ALE.
The active level of the READY pin can be set by
bit RDYPOLx in the BUSCONx registers. When
the READY function is enabled for a specific
address window, each bus cycle within the window must be terminated with the active level
defined by bit RDYPOLx in the associated BUSCONx register.
22/76
8 - INTERRUPT SYSTEM
The interrupt response time for internal program
execution is from 200ns to 480ns at 25MHz CPU
clock.
The ST10F168 architecture supports several
mechanisms for fast and flexible response to service requests that can be generated from various
sources (internal or external) to the microcontroller. Any of these interrupt requests can be serviced by the Interrupt Controller or by the
Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where
the current program execution is suspended and
a branch to theinterrupt vector table is performed,
just one cycle is ‘stolen’ from the current CPU
activity to perform a PEC service. A PEC service
implies a single Byte or Word data transfer
between any two memory locations with an
additional increment of either the PEC source or
the destination pointer. An individual PEC transfer
counter is implicitly decremented for each PEC
service except when performing in the continuous
transfer mode. When this counter reaches zero, a
standard interrupt is performed to the
corresponding source related vector location.
PEC services are very well suited to perform the
transmission or the reception of blocks of data.
ST10F168
The ST10F168 has 8 PEC channels, each of
them offers such fast interrupt-driven data transfer
capabilities.
A interrupt control register which contains an
interrupt request flag, an interrupt enable flag and
an interrupt priority bitfield is dedicated to each
existing interrupt source. Thanks to its related
register, each source can be programmed to one
of sixteen interrupt priority levels. Once starting to
be processed by the CPU, an interrupt service
can only be interrupted by a higher prioritized
service request. For the standard interrupt
processing, each of the possible interrupt sources
has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs feature
programmable edge detection (rising edge, falling
edge or both edges). Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number.
Table 9 shows all the available ST10F168 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector
locations and trap (interrupt) numbers:
Table 9 : Interrupt sources
Source of Interrupt or PEC Service Request
CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040h 10h
CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044h 11h
CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048h 12h
CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004Ch 13h
CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050h 14h
CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054h 15h
CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058h 16h
CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005Ch 17h
CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060h 18h
CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064h 19h
CAPCOM Register 10 CC10IR CC10IE CC10INT 00’0068h 1Ah
CAPCOM Register 11 CC11IR CC11IE CC11INT 00’006Ch 1Bh
CAPCOM Register 12 CC12IR CC12IE CC12INT 00’0070h 1Ch
CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074h 1Dh
CAPCOM Register 14 CC14IR CC14IE CC14INT 00’0078h 1Eh
CAPCOM Register 15 CC15IR CC15IE CC15INT 00’007Ch 1Fh
CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0h 30h
CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4h 31h
CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8h 32h
CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CCh 33h
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
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