SGS Thomson Microelectronics ST10F167-Q6 Datasheet

May 1997 1/69

Thisispreliminaryinformation onanewproduct indevelopment orundergoing evaluation. Details are subjectto changewithout notice.

ST10F167

16-BIT MCU WITH 128K BYTE FLASH MEMORY

PRELIMINARY DATASHEET

■ High Performance 16-bit CPU with 4-Stage

Pipeline

■ 100 ns Instruction Cycle Time at 20MHz CPU

Clock

■ 500 ns Multiplication (16 × 16 bit), 1 µs Division

(32 / 16 bit)

■ Enhanced Boolean Bit Manipulation Facilities

■ Additional Instructions to Support HLL and

Operating Systems

■ Register-Based Design with Multiple Variable

Register Banks

■ Single-Cycle Context Switching Support

■ Clock Generation via on-chip PLL or via direct

clock input

■ Up to 16 MBytes Linear Address Space for

Code and Data

■ 2K Bytes On-Chip Internal RAM (IRAM)

■ 2K Bytes On-Chip Extension RAM (XRAM)

■ 128K Bytes On-Chip FLASH memory

■ FLASH Memory organized into 4 banks

independently erasable

■ Programmable External Bus Characteristics for

Different Address Ranges

■ 8-Bit or 16-Bit External Data Bus

■ Multiplexed or Demultiplexed External Address/

Data Buses

■ Five Programmable Chip-Select Signals

■ Hold- and Hold-Acknowledge Bus Arbitration

Support

■ 1024 Bytes On-Chip Special Function Register

Area

■ Idle and Power Down Modes

■ 8-Channel Interrupt-Driven Single-Cycle Data

Transfer Facilities via Peripheral Event
Controller (PEC)

■ 16-Priority-Level Interrupt System with 56

Sources, Sample-Rate down to 50 ns

■ 16-Channel 10-bit A/D Converter with 9.7µs

Conversion Time

■ Two 16-Channel Capture/Compare Units

■ 4-Channel PWM Unit

■ Two Multi-Functional General Purpose Timer

Units with 5 Timers

■ Two Serial Channels (Synchronous/

Asynchronous and High-Speed-Synchronous)

■ On-Chip CAN 2.0B Interface with 15 Message

Objects (Full-CAN/Basic-CAN)

■ Programmable Watchdog Timer

■ Up to 111 General Purpose I/O Lines, partly

with Selectable Input Thresholds and
Hysteresis

■ Supported by development tools: C-Compilers,

Macro-Assembler Packages, Emulators,
Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers,
Programming Boards

■ On-Chip Bootstrap Loader

■ 144-Pin PQFP Package

Port 0

Port 1Port 4

Port 6

Port 5 Port 3

Port 2

GPT1

GPT2

ASC usart

BRG

Internal
FLASH
Memory

CPU-Core

Internal

RAM

Watchdog

Interrupt Controller

8

8

15

16

32

16

PEC

16

16

CAN

Port 7

Port 8

External Bus

10-Bit ADC

BRG

SSC

PWM

CAPCOM2

CAPCOM1

8

16

16

OSC.

XRAM

16

Controller

16

8

16

1

2/62

Table of Contents

3

1 INTRODUCTION ......................................................4

2 PINDATA ........................................................... 5

3 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . ........................12

4 MEMORYORGANIZATION ............................................13

5 EXTERNALBUSCONTROLLER ........................................13

6 FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1 Flash Memory Programming And Erasure . . . . . . . . . . . . . . . . . . . . . . . .....14

6.2 Flash Control Register (FCR) . . . . . . . . . . . . . . . . . . . . . . . ...............15

6.3 Flash Memory Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............16

7 CENTRALPROCESSINGUNIT(CPU) ...................................19

8 INTERRUPTSYSTEM ................................................20

9 CAPTURE/COMPARE(CAPCOM)UNITS .................................24

10 GENERALPURPOSETIMER(GPT)UNIT ................................26

11 PWMMODULE ......................................................28

12 WATCHDOGTIMER..................................................29

13 A/DCONVERTER ....................................................29

14 SERIALCHANNELS ..................................................30

15 CAN-MODULE ......................................................30

16 PARALLELPORTS...................................................31

17 INSTRUCTION SET SUMMARY .........................................32

18 BOOTSTRAPLOADER................................................33

19 SPECIAL FUNCTION REGISTER OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

20 ELECTRICALCHARACTERISTICS ......................................41

20.1 Absolute Maximum Ratings .......................................41

20.2 Parameter Interpretation . . . . . . . . . .................................41

20.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .....................42

20.4 A/D Converter Characteristics . . . . . .................................45

20.5 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............47

20.5.1 Test Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . ............... 47

20.5.2 Definition of Internal Timing . . ..............................48

20.5.3 DirectDrive ............................................. 48

20.5.4 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . ..................49

20.5.5 ExternalClockDriveXTAL1 ................................50

20.5.6 Memory Cycle Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

20.5.7 Multiplexed Bus . . . .......................................51

2

3/62

20.5.8 Demultiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

20.5.9 CLKOUTandREADY.....................................63

20.5.10 External Bus Arbitration . . .................................65

21 PACKAGEMECHANICALDATA ........................................68

22 ORDERINGINFORMATION............................................68

4/69

ST10F167

1 INTRODUCTION

The ST10F167 is a flash derivative of the
SGS-THOMSON ST10 family of full featured sin­gle-chip CMOS microcontrollers. It combines high
CPU performance with high peripheral functionali-

ty and enhanced IO-capabilities. It also provides
on-chip high-speed RAM and clock generation via
PLL.

Figure 1.1 Logic Symbol

XTAL1

RSTIN

XTAL2

RSTOUT

NMI
EA

READY
ALE

RD
WR/WRL

Port 5
16-bit

Port 6

8-bit

Port 4

8-bit

Port 3

15-bit

Port 2

16-bit

Port 1

16-bit

Port 0

16-bit

V

DD

V

SS

ST10F167

Port 7

8-bit

Port 8
8-bit

V

AREF

V

AGND

3

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ST10F167

2 PIN DATA

ST10F167

P6.0/CS0
P6.1/CS1
P6.2/CS2
P6.3/CS3
P6.4/CS4

P6.5/HOLD

P6.6/HLDA

P6.7/BREQ
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO

P8.6/CC22IO
P8.7/CC23IO

V

DD

V

SS

P7.0/POUT0
P7.1/POUT1
P7.2/POUT2
P7.3/POUT3

P8.5/CC21IO

V

PP

P7.4/CC28I0
P7.5/CC29I0
P7.6/CC30I0
P7.7/CC31I0

P5.0AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.6/AN6
P5.7/AN7
P5.8/AN8
P5.9/AN9

POH.0/AD8
POL.7/AD7
POL.6/AD6
POL.5/AD5
POL.4/AD4
POL.3/AD3
POL.2AD2
POL.A/AD1
POL.0/AD0

EA
ALE
READY

WR/WRL
RD
V

SS

V

DD

P4.7/A23
P4.6/A22/CAN_T

X

D

P4.5/A21/CAN_R

X

D
P4.4/A20
P4.3/A19
P4.2/A18
P4.1/A17
P4.0/A16

V

SS

V

DD

P3.15/CLKOUT
P3.13/SCLK
P3.12/BHE/WRH
P3.11/RXD0
P3.10/TXD0
P3.9/MTSR
P3.8/MRST
P3.7/T2IN
P3.6/T3IN

V

AREF

V

AGND

P5.10/AN10/T6EUD

P5.11/AN11/T5EUD

P5.12/AN12/T6IN

P5.13/AN13/T5IN

P5.14/AN14/T4EUD

P5.15/AN15/T2EUD

V

SS

V

DD

P2.0/CC0IO

P2.1/CC1IO

P2.2/CC2IO

P2.3/CC3IO

P2.4/CC4IO

P2.5/CC5IO

P2.6/CC6IO

P2.7/CC7IO

V

SS

V

DD

P2.8/CC8IO/EX0IN

P2.9/CC9IO/EX1IN

P2.10/CC10IOEX2IN

P2.11/CC11IOEX3IN

P2.12/CC12IO/EX4IN

P2.13/CC13IO/EX5IN

P2.14/CC14IO/EX6IN

P2.15/CC15IO/EX7IN/T7IN

P3.0/T0IN

P3.1/T6OUT

P3.2/CAPIN

P3.3/T3OUT

P3.4/T3EUD

P3.5/T4IN

V

SS

V

DD

VSSNMI

V

DD

RSTOUT

RSTIN

VSSXTAL1

XTAL2

VDDP1H.7/A15/CC27IO

P1H.6/A14/CC26IO

P1H.5/A13/CC25IO

P1H.4/A12/CC24IO

P1H.3/A11

P1H.2/A10

P1H.1/A9

P1H.0/A8

VSSVDDP1L.7/A7

P1L.6/A6

P1L.5/A5

P1L.4/A4

P1L.3/A3

P1L.2/A2

P1L.1/A1

P1L.0/A0

POH.7/AD15

POH.6/AD14

POH.5/AD13

POH.4/AD12

POH.3/AD11

POH.2/AD10

POH.1/AD9

VSSV

DD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

3738394041424344454647484950515253545556575859606162636465666768697071

72

108
107
106
105
104
103
102
101
100

99
98
97

96
95

94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

3

6/69

ST10F167

Table 2.1 Pin Definitions and Functions

Symbol

Pin

Number

Input (I)

Output

(O)

Function

P6.0 –P6.7 1 - 8

1

...

5
6
7
8

I/O

O
...
O

I
O
O

Port 6 is an 8-bitbidirectional I/O port. It is bit-wiseprogrammable
for input or output via direction bits. Fora pinconfigured as input,
the output driver is put into high-impedance state. Port 6 outputs
can be configured as push/pull or open drain drivers.
The following Port 6 pins also serve for alternate functions:
P6.0 CS0 Chip Select 0 Output

... ... ...

P6.4 CS4 Chip Select 4 Output
P6.5 HOLD External Master Hold Request Input
P6.6 HLDA HoldAcknowledge Output
P6.7 BREQ BusRequest Output

P8.0 –P8.7 9 - 16

9

...

16

I/O

I/O

...

I/O

Port 8 is an 8-bitbidirectional I/O port. It is bit-wiseprogrammable
for input or output via direction bits. Fora pinconfigured as input,
the output driver is put into high-impedance state. Port 8 outputs
can be configured as push/pull or open drain drivers. The input
threshold of Port 8 is selectable (TTL or special).
The following Port 8 pins also serve for alternate functions:
P8.0 CC16IO CAPCOM2: CC16 Cap.-In/Comp.Out

... ... ...

P8.7 CC23IO CAPCOM2: CC23 Cap.-In/Comp.Out

P7.0 –P7.7 19 - 26

19

...
22
23

...
26

I/O

O
...
O

I/O

...

I/O

Port 7 is an 8-bitbidirectional I/O port. It is bit-wiseprogrammable
for input or output via direction bits. Fora pinconfigured as input,
the output driver is put into high-impedance state. Port 7 outputs
can be configured as push/pull or open drain drivers. The input
threshold of Port 7 is selectable (TTL or special).
The following Port 7 pins also serve for alternate functions:
P7.0 POUT0 PWM Channel 0 Output

... ... ...

P7.3 POUT3 PWM Channel 3 Output
P7.4 CC28IO CAPCOM2: CC28 Cap.-In/Comp.Out

... ... ...

P7.7 CC31IO CAPCOM2: CC31 Cap.-In/Comp.Out

3

7/69

ST10F167

P5.0-P5.15 27 – 36

39 – 44

39
40
41
42
43
44

I
I

I
I
I
I
I
I

Port 5 is a 16-bit input-only port with Schmitt-Trigger characteris­tics. The pins of Port 5 also serve as the (up to 16) analog input
channels for the A/D converter, where P5.x equals ANx (Analog
input channel x), or they serve as timer inputs:
P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down Ctrl.Input
P5.11 T5EUD GPT2 Timer T5 Ext.Up/Down Ctrl.Input
P5.12 T6IN GPT2 Timer T6 Count Input
P5.13 T5IN GPT2 Timer T5 Count Input
P5.14 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input
P5.15 T2EUD GPT1 Timer T2 Ext.Up/Down Ctrl.Input

P2.0-P2.15 47 – 54

57 - 64

47

...
54
57

...
64

I/O

I/O

...
I/O
I/O

I

...
I/O

I
I

Port 2 is a16-bit bidirectional I/Oport. It isbit-wise programmable
for input or output via direction bits. Fora pinconfigured as input,
the output driver is put into high-impedance state. Port 2 outputs
can be configured as push/pull or open drain drivers. The input
threshold of Port 2 is selectable (TTL or special).
The following Port 2 pins also serve for alternate functions:
P2.0 CC0IO CAPCOM: CC0 Cap.-In/Comp.Out

... ... ...

P2.7 CC7IO CAPCOM: CC7 Cap.-In/Comp.Out
P2.8 CC8IO CAPCOM: CC8 Cap.-In/Comp.Out,

EX0IN Fast External Interrupt 0 Input

... ... ...

P2.15 CC15IO CAPCOM: CC15 Cap.-In/Comp.Out,

EX7IN Fast External Interrupt 7 Input

T7IN CAPCOM2 Timer T7 Count Input

Table 2.1 Pin Definitions and Functions (cont’d)

Symbol

Pin

Number

Input (I)

Output

(O)

Function

3

8/69

ST10F167

P3.0­P3.13,
P3.15

65 – 70,
73 – 80,

81

65
66
67
68
69
70

73
74

75
76
77
78
79

80
81

I/O
I/O
I/O

I

O

I

O

I
I

I
I

I/O
I/O

O

I/O

O
O

I/O

O

Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port.It is bit­wise programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-impedance
state. Port 3 outputs can be configured aspush/pull or open drain
drivers. The input threshold of Port 3 is selectable (TTL or spe­cial).
The following Port 3 pins also serve for alternate functions:
P3.0 T0IN CAPCOM Timer T0 Count Input
P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output
P3.2 CAPIN GPT2 Register CAPREL Capture Input
P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output
P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input
P3.5 T4IN GPT1 Timer T4 Input for

Count/Gate/Reload/Capture
P3.6 T3IN GPT1 Timer T3 Count/Gate Input
P3.7 T2IN GPT1 Timer T2 Input for

Count/Gate/Reload/Capture
P3.8 MRST SSCMaster-Rec./Slave-Transmit I/O
P3.9 MTSR SSCMaster-Transmit/Slave-Rec. O/I
P3.10 T×D0 ASC0 Clock/Data Output (Asyn./Syn.)
P3.11 R×D0 ASC0 Data Input (Asyn.) or I/O (Syn.)
P3.12 BHE Ext. Memory High Byte Enable Signal,

WRH Ext. Memory High Byte Write Strobe
P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp.
P3.15 CLKOUT System Clock Output (=CPU Clock)

P4.0 –P4.7 85 - 92

85
90

91

92

I/O

O
O

I
O
O
O

Port 4 is an 8-bitbidirectional I/O port. It is bit-wiseprogrammable
for input or output via direction bits. Fora pinconfigured as input,
the output driver is put into high-impedance state.
In case ofan externalbus configuration, Port 4 can be used toout­put the segment address lines:
P4.0 A16 Least Significant Segment Addr. Line
P4.5 A21 Segment Address Line,

CAN_RxD CAN Receive Data Input

P4.6 A22 Segment Address Line,

CAN_TxD CANTransmit Data Output

P4.7 A23 Most Significant Segment Addr. Line

RD 95 O External Memory Read Strobe. RD is activated for every external

instruction or data read access.

Table 2.1 Pin Definitions and Functions (cont’d)

Symbol

Pin

Number

Input (I)

Output

(O)

Function

3

9/69

ST10F167

WR/WRL 96 O External Memory Write Strobe. In WR-mode this pin is activated

for every external data write access. In WRL-mode this pin is ac­tivated for low byte data write accesses on a 16-bit bus, and for
every data write access on an 8-bit bus. See WRCFG in register
SYSCON for mode selection.

READY 97 I Ready Input. When the Ready function is enabled, a high level at

this pin during an external memory access will force the insertion
of memory cycletime waitstates until the pin returns to a low level.

ALE 98 O Address Latch Enable Output. Can be used for latching the ad-

dress into externalmemory or an addresslatch inthe multiplexed
bus modes.

EA 99 I External Access Enable pin. A low level at thispin duringand after

Reset forces the ST10F167 to begin instruction execution out of
external memory. A high level forces execution out of the internal
Flash Memory.

PORT0:
P0L.0­P0L.7,
P0H.0­P0H.7

100-107

108,

111-117

I/O PORT0 consists of the two 8-bit bidirectional I/O ports P0L and

P0H. It is bit-wise programmable for input or output via direction
bits. Fora pin configured as input, the output driveris putinto high­impedance state.
In caseof an external bus configuration,PORT0 servesas the ad­dress (A) and address/data (AD) bus in multiplexed bus modes
and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes:

Data Path Width:8-bit 16-bit
P0L.0 – P0L.7:D0 – D7D0 - D7
P0H.0 – P0H.7:I/O D8 - D15

Multiplexed bus modes:

Data Path Width:8-bit 16-bit
P0L.0 – P0L.7:AD0 – AD7AD0 - AD7
P0H.0 – P0H.7:A8 - A15AD8 - AD15

Table 2.1 Pin Definitions and Functions (cont’d)

Symbol

Pin

Number

Input (I)

Output

(O)

Function

3

10/69

ST10F167

PORT1:
P1L.0 –
P1L.7,
P1H.0 ­P1H.7

118 –

125

128 –

135

132
133
134
135

I/O

I

I

I

I

PORT1 consists of the two 8-bit bidirectional I/O ports P1L and
P1H. It is bit-wise programmable for input or output via direction
bits. Fora pin configured as input, the output driveris putinto high­impedance state. PORT1is used as the 16-bit address bus (A)in
demultiplexed bus modes and also after switching from a demul­tiplexed bus mode to a multiplexed bus mode.
The following PORT1 pins also serve for alternate functions:
P1H.4 CC24IO CAPCOM2: CC24 Capture Input
P1H.5 CC25IO CAPCOM2: CC25 Capture Input
P1H.6 CC26IO CAPCOM2: CC26 Capture Input
P1H.7 CC27IO CAPCOM2: CC27 Capture Input

XTAL1

XTAL2

138

137

I

O

XTAL1: Input to theoscillator amplifier andinput to the internal
clock generator
XTAL2: Output of the oscillator amplifier circuit.
To clock the device from an external source, driveXTAL1, while
leaving XTAL2 unconnected. Minimum and maximum high/low
and rise/fall times specified in the AC Characteristics must be ob­served.

RSTIN 140 I Reset Input withSchmitt-Triggercharacteristics. A lowlevel at this

pin for a specifiedduration while the oscillatoris running resets the
ST10F167. An internal pullup resistor permits power-on reset us­ing only a capacitor connected to VSS.

RSTOUT 141 O Internal ResetIndicationOutput. This pin isset to alowlevel when

the part isexecuting, eithera hardware, asoftware ora watchdog
timer reset. RSTOUT remains low until the EINIT (end of initializa­tion) instruction is executed.

NMI 142 I Non-Maskable Interrupt Input. A high to low transition at this pin

causes the CPU to vector tothe NMI trap routine. When the
PWRDN (power down) instruction is executed, the NMI pin must
be low in order to force the ST10F167 to go into power down
mode. If NMI is high, when PWRDN is executed, the part willcon­tinue to run in normal mode.
If not used, pin NMI shouldbe pulled high externally.

V

AREF

37 - Reference voltage for the A/D converter.

V

AGND

38 - Reference ground for the A/D converter.

V

PP

84 - Flash programming voltage. This pin accepts the programming

voltage for the on-chip flash EPROM of the ST10F167.

Table 2.1 Pin Definitions and Functions (cont’d)

Symbol

Pin

Number

Input (I)

Output

(O)

Function

3

11/69

ST10F167

V

DD

46, 82,

136

- Digital Supply Voltage for internal circuitry:
+ 5 V during normal operation and idle mode.
≥ 2.5 V during power down mode

17, 56,
72, 93,

109,126,

144

- Digital Supply Voltage for port drivers:
+ 5 V during normal operation and idle mode

V

SS

45, 83,

139

- Digital Ground for internal circuitry.

18, 55,
71, 94,

110,127,

143

- Digital Ground for port drivers.

Table 2.1 Pin Definitions and Functions (cont’d)

Symbol

Pin

Number

Input (I)

Output

(O)

Function

3

12/69

ST10F167

3 FUNCTIONAL DESCRIPTION

The architecture of the ST10F167 combines the
advantages of both RISC and CISC processors
and an advanced peripheral subsystem. The fol­lowing block diagram gives an overview of the dif-

ferent on-chip components and of the advanced,
high bandwidth internal bus structure of the
ST10F167.

Figure 3.1 Block Diagram

Internal
FLASH
Memory

CPU-Core

Internal

RAM

32

16

16

16

16

16

16

16

16

8

8

8

8

16

15

InterruptController

CAN

Module

XRAM

Ext.
Bus

Con-

troller

10-Bit

ADC

Port 6 Port 5

Port 3 Port 7

Port 8

Port 2

Port 0

Port 1

Port 4

ASC

(USART)

SSC

PWM

CAPCOM2CAPCOM

1

GPT1

GPT2

BRG

BRG

Watchdog

OSC.

PEC

T2
T3

T4

T5
T6

T7
T8

T0
T1

...

...

...

VR02060C

3

13/69

ST10F167

4 MEMORY ORGANIZATION

Thememory spaceof the ST10F167 is configured
in a Von-Neumann architecture. Code memory,
data memory, registers and I/O ports are organ­ized within the same linear address space which
includes 16MBytes. The entirememory space can
be accessed bytewise or wordwise. Particular por­tions of the on-chip memory have additionally
been made directly bit addressable.

The ST10F167 provides 128KBytes of on-chip
flash memory.

2 KBytes of on-chip Internal RAM are provided as
astorage for user definedvariables, for the system
stack, general purpose register banks and even
for code. A register bank can consist of up to 16
wordwide(R0 to R15) and/or bytewide(RL0, RH0,
…, RL7, RH7) so-called General Purpose Regis­ters (GPRs).

1024 bytes (2 * 512 bytes) of the address space
are reserved for the Special Function Register ar­eas (SFR space and ESFR space). SFRs are
wordwide registers which are used for controlling
and monitoring functions of the different on-chip
units. Unused SFR addresses are reserved for
other/future members of the ST10 family.

2 KBytes of on-chip Extension RAM (XRAM) are
provided to store user data, user stacks or code.
The XRAM is accessed like external memory and
cannot be used for the system stack or register
banks, and is not bit-addressable. The XRAM al­lows 16-bit accesses with maximum speed.

In order to meet the needs of designs where more
memory is required than is provided on chip, upto
16 MBytes of external RAM and/or ROM can be
connected tothe microcontroller.

5 EXTERNAL BUS CONTROLLER

All of the external memory accesses are per­formed by a particular on-chip External Bus Con­troller (EBC). It can be programmed either to Sin­gle Chip Mode when no external memory is re­quired, or to one of four different external memory
access modes, which are as follows:

• 16-/18-/20-/24-bit Addresses, 16-bit Data,
Demultiplexed

• 16-/18-/20-/24-bit Addresses, 16-bit Data,
Multiplexed

• 16-/18-/20-/24-bit Addresses, 8-bit Data,
Multiplexed

• 16-/18-/20-/24-bit Addresses, 8-bit Data,
Demultiplexed

In the demultiplexed bus modes, addresses are
output on PORT1 and data is input/output on
PORT0. In the multiplexed bus modes both ad­dresses and data use PORT0 for input/output.

Important timing characteristics of theexternal bus
interface (Memory Cycle Time, Memory Tri-State
Time, Length of ALE and Read Write Delay) have
been made programmable. This gives the choice
of a widerange of different types of memories and
external peripherals. In addition, different address
ranges may be accessed with different bus char­acteristics. Up to5 externalCS signals (4windows
plus default) can be generated in order to save ex­ternal glue logic. Access to very slow memories is
supported via a particular ‘Ready’ function. A
HOLD/HLDA protocol is available for bus arbitra­tion.

For applications which require less than 16
MBytes of external memory space, this address
space can be restricted to 1 MByte, 256 KByte or
to 64 KByte. Inthis case Port 4 outputs four, twoor
no address lines. If an address space of 16
MBytes is used, it outputs all 8 address lines.

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6 FLASH MEMORY

The ST10F167 provides 128KBytes of on-chip,
electrically erasable and re-programmable Flash
EPROM. The flash memory is organized in 32 bit
wide blocks. This allows double word instructions
to be fetched in one machine cycle. The flash
memory can be used for both code and data stor­age. The flash memory is organised into four
banks of sizes 8K, 24K, 48K and 48Kbytes (table

6.1). Each of these banks can be erased inde­pendently. This prevents unnecessary re-pro­gramming of the whole flash memory when only a
partial re-programming is required.

The first 32K bytes of the FLASH memory are lo­cated in segment 0 (0h to 007FFFh) during reset,
and include the reset and interrupt vectors. The
rest of the FLASH memoryis mapped in segments
1 and 2 (018000h to 02FFFFh). For flexibility, the
first 32K bytes of the FLASH memorymay be rem­apped to segment 1 (010000h to 017FFFh) during
initialization. This allows the interrupt vectors to be
programmed from the external memory, while re­taining the common routines and constants that
are programmed into the FLASHmemory.

6.1 Flash Memory Programming And Erasure

The FLASH memory is programmed using the
PRESTO F Program Write algorithm. Erasure of
the FLASH memory is performed in the program
mode using the PRESTO F Erase algorithm.

Timing of the Write/Erase cycles is automatically
generated by a programmable timer and comple-

tion is indicated by a flag. A second flag indicates
that the VPPvoltage was correct for the whole pro­gramming cycle. This guarantees that a good
write/erase operation has been carried out.

The FLASH parameters are detailed below.

Table 6.1 FLASH Memory Bank Organisation

Bank Addresses (Segment 0) Size (bytes)

0
1
2
3

000000h to 07FFFh and 018000h to 01BFFFh
01C000h to 027FFFh
028000h to 02DFFFh
02E000h to 02FFFFh

48K
48K
24K

8K

Table 6.2 Flash Parameters

Parameter Units Min Typical Max

Word Programming Time µsec 12.8 12.8 1250
Bank Erasing Time sec 0.5 30
Endurance cycles 1000
Flash Vpp volts 11.4 12.6

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6.2 Flash Control Register (FCR)

Inthe standard operation mode,the FLASH mem­ory can be accessed in the same way as the nor­mal mask-programmable on-chip ROM. All, appro­priate, direct and indirect addressing modes can
be used for reading the FLASH memory.

All programming or erase operations are control­led via a 16-bit register, the FCR. The FCR is not
an SFR or GPR. To prevent inadvertent writing to
the FLASH memory, the FCR is locked and inac­tive during the standard operation mode. The
FLASH memory writing mode must be entered,
before a valid access to the FCR is provided. This
is done via a special key code instruction se­quence.

The FCR is virtually mapped into the active ad­dress space of the Flash memory. It can only be
accessed with direct 16-bit (mem) addressing
modes. Since the FCR is neither byte, nor bit-ad­dressable, only word operand instructions can be
used for FCR accesses. By default, the FCR can
be accessed with any even address from 000000h
to 07FFFEh and 018000h to 02FFFEh. If the first
32K byte Block of the FLASH memory is mapped
to segment 1, the corresponding even FCR ad­dresses are 010000h to 017FFEh. Note that DPP
referencing andDPP contents mustbe considered
for FCR accesses. If an FCR access is attempted
via an odd address, an illegal operand access
hardware trap will occur.

FCR

Flash Control Register
Reset Condition: 0000h (Read)

b15 = FWMSET:

Flash Writing Mode Set

. This bit
is set to ”1” automatically once the Flash writing
mode is entered. To exit from the Flash writing
mode, FWMSET must be set to ”0”. Since only
word values can be written to FCR, care must be
taken that FWMSET is not cleared inadvertently.
Therefore, for any command written to FCR (ex­cept for the return to the Flash standard mode),

FWMSET must be set to ”1”. Reset condition of
FWMSET is ”0”.

b14-b10 = Reserved: these bits are reserved for
future development, they must be written to ”0”.

b9-b8 = BE0,1:

Bank erase select.

These bits se­lect the Flash memory bank to be erased. The
physical addresses of bank 0 depends on the
which Flash memory map has been chosen. In
Flash operating modes, other than the erasing
mode, these bits arenot significant. At reset BE1,0
are set to ”00”.

b7 = WDWW:

Word/double word write.

Thisbit de­termines the word width used for programming op­erations: 16-bit (WDWW = 0) or 32-bit (WDWW =
”1”). In Flash operation modes, other than the pro­gramming mode, this bit is notsignificant. At reset,
WDWW is set to “0”.

b6-b5 = CKCTL0,1:

Flash Timer Clock Control.

These twobits control the width (TPRG) of the pro­gramming or erase pulses applied to the Flash
memory cells during theoperation. TPRGvaries in
an inverse ratio to the clock frequency. To avoid
putting theFlash memory under critical stress con­ditions, the width of one single programming or
erase pulse and the programming or erase time,
must not exceed defined values. Thus the maxi­mum number of programming or erase attempts,
depends on the system clock frequency.

RESET state: 00.
b4 = VPPRIV:

VPPRevelationbit.

Thisread-only bit
reflects the state of the VPPvoltage in the Flash
writing mode. If VPPRIV is set to ”0”, this indicates
that VPPis below the threshold necessary for relia­ble programming. The normal reaction to this indi­cation is to check the VPPpowersupply and to then
repeat the intended operation. If the VPPvoltage is
above a sufficient margin, VPPRIV will be set to
”1”. The reset state of the VPPRIV bit depends on
the state of the external VPPvoltage at the VPPpin.

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ST10F167

b3 = FCVPP:

Flash VPPcontrol bit.

This read-only
bit indicates that the VPPvoltage fell below the val­id threshold value during a Flash programming or
erase operation. If FCVPP is set to ”1” after such
an operation has finished, it can mean that the op­eration was not successful. The VPPpower supply
should be checked and the operation repeated. If
FCVPP is set to ”0”, no critical discontinuity in V

PP

occurred. At reset FCVPP is set to ”0”.
b2 = FBUSY:

Flash busy bit.

This read-only bit in­dicates that a Flash programming or erase opera­tion is in progress. FBUSY is set to ”1” by hard­ware, as soon as the programming or erase com­mand is given. At reset FBUSY is set to ”0”. Note
that this bit position is also occupied by the write­only bit RPROT.

b2 = RPROT:

Protection enable bit

. This bit set at
1,anded with the OTP protection bit, disables any
access to the Flash, by instructions fetched from
the external memory space, or from the internal
RAM. This write-only bit, is only significant if the
general Flash memory protection is enabled. If the
protectionis enabled, the setting of RPROT deter­mines whether the Flash protection is active
(RPROT=”1”) or inactive (RPROT=”0”). RPROT is
theonly FCRbit which can be modified evenin the
Flash standard operation mode, but only by anin-

struction executed from the Flash memory itself.
At reset,RPROT is set to ”1”. Note that this bit po­sition is alsooccupied by theread-only bit FBUSY.

b1 = FEE:

Flash erase/program selection.

This bit
selects the Flash write operation to be performed:
erase (FEE=”1”) or programming (FEE=”0”). To­gether with bits FWE and FWMSET,bit FEE deter­mined the operation mode of the Flash memory.
Note that setting bits FWE and FEE causes the
corresponding Flash operation mode to be select­ed but does not launch the execution of the select­ed operation. If bit FWE was set to ”0”, thesetting
of FEE is insignificant. At reset, FEE is set to ”0”.

b0 = FWE:

Flash write/read enable

. This bit deter­mines whether FLASH write operations are ena­bled (FWE=1) or disabled (FWE=0). By definition,
a FLASH write operation can be either program­ming or erasure. Together with bits FEE and
FWMSET, bit FWE determines the operation
mode of the Flash memory. Note that setting bits
FWE and FEE causes the corresponding Flash
operation modeto beselected but does not launch
the execution of the selected operation. If bit FWE
was set to ”1”, any read accesson a Flash memo­ry location means a particular program-verify or
erase-verify read operation. Flashwrite operations
are disabled at reset.

6.3 Flash Memory Security

Security and reliability have been enhanced by
built-in features: a key code sequence is used to
enter the Write/Erase mode preventing false write
cycles, a programmable option (set by the pro­gramming board) prevents access to the FLASH
memory from the internal RAM or from External

Memory. If the security option is set, the FLASH
memory can only be accessed from a program
within the FLASH memory area. This protection
can only bedisabled by instructions executed from
the FLASH memory.

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Figure 6.1 PRESTO F Write Algorithm

=0

PCOUNT=PNmax?

PCOUNT=PCOUNT+1

VR02057A

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ST10F167

Figure 6.2 PRESTO F Erase Algorithm

=0

PCOUNT=ENmax?

PCOUNT=PCOUNT+1

VR02057B

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7 CENTRAL PROCESSING UNIT (CPU)

Figure 7.1 CPU Block Diagram

Themain core of theCPU consists of a4-stage in­struction pipeline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. has been added for a
separate multiply and divide unit, a bit-mask gen­erator and a barrel shifter.

Based on these hardware provisions, most of the
ST10F167’s instructions can be executed in one
machine cycle. This requires 100ns at 20MHz
CPU clock. For example, shift and rotate instruc­tions are always processed during one machine
cycleindependent ofthe number of bits to be shift­ed. All multiple-cycle instructions have been opti­mized for speed: branches in 2 cycles, a 16 × 16
bit multiplication in 5 cycles and a 32-/16 bit divi­sion in 10 cycles. The ‘Jump Cache’ pipeline opti­mization,reduces theexecution timeof repeatedly
performed jumps in a loop, from 2 cycles to 1 cy­cle.

The CPU includes an actual register context. This
consists of up to 16 wordwide GPRs which are
physically allocated within the on-chip RAM area.
A Context Pointer (CP) register determines the
base address of the active register bank to be ac­cessed by the CPU at a time. The number of reg­ister banks is only restricted by the available inter­nal RAM space. For easy parameter passing, a
register bank may overlap others.

A system stack of up to 2048 bytes is provided as
a storage for temporary data. The system stack is
allocated in the on-chip RAM area, and it is ac­cessed by the CPU via the stack pointer (SP) reg­ister. Two separate SFRs, STKOV and STKUN,
are implicitly compared against the stack pointer
value upon each stack access for the detection of
a stack overflow or underflow.

16

16

32

FLASH

Internal

RAM

2KByte

R15

R0

General

Purpose

Registers

R0

R15

MDH
MLD

Barrel-Shift

Mul./Div.-HW
Bit-Mask Gen.

ALU

16-Bit

Context Ptr

SP

STKOV

STKUN

Exec. Unit

Instr. Ptr
Instr. Reg

4-Stage

Pipeline

PSW

SYSCON

BUSCON0
BUSCON1

BUSCON2
BUSCON3
BUSCON4

ADDRSEL 1
ADDRSEL 2

ADDRSEL 3
ADDRSEL 4

Data Pg. Ptrs

Code Seg. Ptr.

CPU

ROM

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ST10F167

An efficient instruction set allows maximum use of
the CPU. The instruction set is classified into the
following groups:

• Arithmetic Instructions

• Logical Instructions

• Boolean Bit Manipulation Instructions

• Compare and Loop Control Instructions

• Shift and Rotate Instructions

• Prioritize Instruction

• Data Movement Instructions

• System Stack Instructions

• Jump and Call Instructions

• Return Instructions

• System Control Instructions

• Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes.
Possible operand types are bits, bytes and words.
A variety of direct, indirect or immediate address­ing modes exist.

8 INTERRUPT SYSTEM

With an interrupt response time from 250ns to
600ns (in the case of internal program execution),
the ST10F167 reacts quickly to the occurrence of
non-deterministic events

The architecture of the ST10F167 supports sever­al mechanisms for fast and flexible response to
service requests that can be generated from vari­ous sources internal or external to the microcon­troller.Any of these interrupt requests can be pro­grammed to being serviced by the Interrupt Con­troller or by the Peripheral Event Controller (PEC).

Ina standard interrupt service, program execution
is suspended and a branch to the interrupt vector
tableis performed. For aPEC service, just one cy­cleis ‘stolen’ from the current CPU activity.A PEC
service is a single byte or word data transfer be­tween any two memory locations with an addition­al increment of either the PEC source or the desti­nation pointer. An individual PEC transfer counter
is decremented for each PEC service, except for
the continuous transfer mode. When this counter
reaches zero, a standard interrupt is performed to
the corresponding source related vector location.
PEC services are suitedto, for example, the trans­mission or reception of blocks of data. The

ST10F167 has 8 PEC channels, each of which of­fers fast interrupt-driven data transfer capabilities.

A separate control register which contains an in­terrupt request flag, an interrupt enable flag and
an interrupt priority bitfield, exists for each of the
possible interrupt sources. Via its related register,
each source canbe programmed to oneof sixteen
interrupt priority levels. Once having been accept­ed by the CPU, an interrupt service can only be in­terrupted by a higher prioritized service request.
For the standard interrupt processing, each of the
possible interrupt sources has a dedicated vector
location.

Fast external interrupt inputs are provided to serv­ice external interrupts with high precision require­ments. These fast interrupt inputs, feature pro­grammable edge detection (rising edge, falling
edge or both edges).

Software interrupts are supported by means of the
‘TRAP’ instruction in combination with an individu­al trap (interrupt) number.

Table 8.1 shows all of the possible ST10F167 in­terrupt sources and the corresponding hardware­related interrupt flags, vectors, vector locations
and trap (interrupt) numbers

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Table 8.1 Interrupt Sources, Flags, Vector and Trap Numbers

Source of Interrupt or

PEC Service Request

Request

Flag

Enable

Flag

Interrupt

Vector

Vector

Location

Trap

Number

CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040h 10h
CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044h 11h
CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048h 12h
CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004Ch 13h
CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050h 14h
CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054h 15h
CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058h 16h
CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005Ch 17h
CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060h 18h
CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064h 19h
CAPCOM Register 10 CC10IR CC10IE CC10INT 00’0068h 1Ah
CAPCOM Register 11 CC11IR CC11IE CC11INT 00’006Ch 1Bh
CAPCOM Register 12 CC12IR CC12IE CC12INT 00’0070h 1Ch
CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074h 1Dh
CAPCOM Register 14 CC14IR CC14IE CC14INT 00’0078h 1Eh
CAPCOM Register 15 CC15IR CC15IE CC15INT 00’007Ch 1Fh
CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0h 30h
CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4h 31h
CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8h 32h
CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CCh 33h
CAPCOM Register 20 CC20IR CC20IE CC20INT 00’00D0h 34h
CAPCOM Register 21 CC21IR CC21IE CC21INT 00’00D4h 35h
CAPCOM Register 22 CC22IR CC22IE CC22INT 00’00D8h 36h
CAPCOM Register 23 CC23IR CC23IE CC23INT 00’00DCh 37h
CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0h 38h
CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4h 39h
CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8h 3Ah
CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00ECh 3Bh
CAPCOM Register 28 CC28IR CC28IE CC28INT 00’00E0h 3Ch
CAPCOM Register 29 CC29IR CC29IE CC29INT 00’0110h 44h
CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114h 45h
CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118h 46h
CAPCOM Timer 0 T0IR T0IE T0INT 00’0080h 20h
CAPCOM Timer 1 T1IR T1IE T1INT 00’0084h 21h
CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4h 3Dh
CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8h 3Eh

3