SGS Thomson Microelectronics MK5027N, MK5027Q Datasheet

MK5027

SS7 SIGNALLING

LINK CONTROLLER

August 1989

CMOS
FULLY COMPATIBLE WITH BOTH 8 OR 16

BITSYSTEMS
SYSTEM CLOCK RATE TO 10MHz. DATA

RATE UP TO 2.5Mbps FOR SS7 PROTOCOL
PROCESSING,7Mbps FOR TRANSPARENT
HDLCMODE

COMPLETELEVEL 2 IMPLEMENTATION
COMPATIBLE WITH 1988 CCITT, AT&T,

ANSI, AND BELLCORE SIGNALLING SYS­TEMNUMBER 7 LINK LEVELPROTOCOLS

52 PIN PLCC AND 48-PIN DIP PIN-FOR-PIN
COMPATIBLE WITH THE SGS-THOMSON
X.25 CHIP (MK5025)AND NEARLY PIN-FOR­PIN COMPATIBLE WITH THE SGS-THOM­SON VLANCE CHIP (MK5032)

BUFFER MANAGEMENTINCLUDES:

- InitializationBlock

- SeparateReceive and TransmitRings

- VariableDescriptor Ring and Window Sizes.
ON CHIP DMA CONTROL WITH PROGRAM-

MABLEBURST LENGTH
SELECTABLE BEC OR PCR RETRANSMIS-

SION METHODS, INCLUDING FORCED RE­TRANSMISSIONFOR PCR

HANDLESALL 7 SS7 TIMERS
HANDLESALL SS7 FRAME FORMATTING:

- Zerobit insertand delete

- FCSgeneration and detection

- Framedelimiting with flags
PROGRAMMABLE MINIMUM SIGNAL UNIT

SPACING(number of flags between SU’s)
HANDLES ALL SEQUENCING AND LINK

CONTROL
SELECTABLEFCS OF 16 OR 32 BITS.
TESTINGFACILITIES:

- InternalLoopback

- Silent Loopback

- OptionalInternal Data Clock Generation

- SelfTest
ALL INPUTS AND OUTPUTS ARE TTL COM-

PATIBLE
PROGRAMMABLE FOR FULL OR HALF DU-

PLEX OPERATION

DESCRIPTION

The SGS-THOMSON Signalling System #7 Sig­nalling Link Controller (MK5027) is a VLSI semi-

conductor device which provides a complete link
control function conforming to the 1988 CCITT
version of SS7. This includes frame formatting,
transparency(so called ”bit-stufling”),error recov­ery by two types of retransmission, error monitor­ing, sequence number control, link status con­trol, and FISU generation. One of the outstanding
features of the MK5027 is its buffer management
which includes on-chip DMA. Thisfeature allows
users to handlq multiple packets of receive and
transmit data at a time. (A conventional data link­control chip plus a separate DMA chip wouldhan­dle data for only a single block at a time.) The
MK5027 maybe used with any of severalpopular
16 and 8 bit microprocessors, such as 68000,
6800, Z8000, Z80, LSI-11, 8086, 8088,8080, etc.

DIP48 PLCC52

VSS-GND

DAL07
DAL06

DAL05
DAL04

DAL03
DAL02

DAL01
DAL00

READ
INTR

DALI
DALO

DAS

BMO, BYTE, BUSREL

BMI, BUSAKO

HOLD, BUSRQ

ALE, AS

CS
ADR

READY
RESET

VSS-GND

24

HLDA

1
2

3
4
5
6

7
8
9
10

11
12

13
14

48
47

46
45

44
43
42
41

40
39
38
37

36

23

22

21

20

19

18

17

16

15

35
34

33
32

31
30

29
28

27
26

25

TCLK

A18
A19

A20
A21

A22
A23

RD
DSR, CTS

TD
SYSCLK

RCLK
DTR, RTS

VCC (+5V)
DAL08

DAL09
DAL10

DAL11
DAL12
DAL13
DAL14

DAL15
A16
A17

M

K
5
0
H
2
5

Figure 1: Pin Connection.

1/19

Table 1: PinDescription.
LEGEND:

I Input only O Output only
IO Input/Output 3S 3-State
OD Open Drain(no internal pull-up)

Signal Name Pin(s) Type Descriplion

DAL<15:00> 2-9

40-47

IO/3S The time multiplexedData Address bus.During the address portion of a

memory transfer, DALe15:00 contains the lower 16 bits ofthe memory
address.
Duringthe data portion of a memory transfer, DAL<15:00> contains the
read or write data, depending on thetype of transfer.

READ 10 IO/3S READ indicates the type of operationthat the bus controlleris performing

during a bus transaction. READ is driven by the MK5027 only while it is
the BUS MASTER. READ isvalid during the entire bus transactionand is
tristatedat all othertimes.
MK5027 as a Bus Slave:

READ = HIGH - Data is placed on the DAL lines by the chip.
READ = LOW- Data is taken off theDAL lines by the chip.

MK5027 as a Bus Master:

READ = HIGH- Data is taken off the DAL lines by the chip.
READ = LOW - Data is placed on the DAL lines by the chip.

INTR 11 O/OD INTERRUPT is an attention interruptline that indicates that one or moreof

the following CSR0 status flags isset: MISS, MERR,RINT, TINT or PINT.
INTERRUPT is enabled by CSR0<0.9>, INEA = 1.

DALI 12 O/3S DAL IN is an external bus transceiver control line. DALIis driven by the

MK5027 only whileit is the BUS MASTER. DALIis assertedby the
MK5027 when | ads from the DAL lines during the data portion of a READ
transfer. DALIis not asserted during a WRITE transfer.

DALO 13 O/3S DAL OUT isan external bus transceiver control line. DALOis driven by

the MK5027 onlywhile it is the BUS MASTER. DALOis asserted by the
MK5027 when itdrives the DAL linesduring theaddress portion of a
READ transfer orfor the duration of a WRITE transfer.

DAS 14 IO/3S DATA STROBE defines the dataportio,n ofa transaction. By definition,

data is stable and valid at the low to hightransition of DAS.This signal is
drivenby the MK5027 while it is the BUS MASTER.During the BUS
SLAVE operation, this pin is used as an input.At all other times the signal
is tristated.

BMO

BYTE

BUSREL

15 IO/3S I/O pins 15and 16 are programmable through CSR4. If bit 06 of CSR4 is

set to a one, pin 15 becomes inputBUSRELand is used by the hostto
signalthe MK5027 toterminate a DMA burst after thecurrent bus transfer
has completed. If bit 06 is clear the pin 15 is an output and behaves as
described below for pin16.

Note: Pin out shown is for 48 pin dip.

MK5027

2/19

Table 1: PinDescription (continued)

Signal Name Pin(s) Type Descriplion

BM1

BUSAKO

16 O/3S Pins 15 and 16 are programmable though bit 00 ofCSR4 (BCON).

If CSR4<00> BCON = 0,

I/O PIN 15 = BMO (O/3S)

I/O PIN 16 = BM1 (O/3S)
BYTE MASK<1:0> indicates the byte(s) on the DAL to be read or written
during this bus transaction. MK5027 drives these lines only as a Bus
Master. MK5027 ignores the BM lines whenit is a Bus Slave.
Byte selection is done as outlined inthe following table.

BM1 BM0 TYPE OF TRANSFER

LOW LOW ENTIRE WORD

LOW HIGH UPPER BYTE (DAL<15:08>)

HIGH LOW LOWER BYTE(DAL<07:00>)

HIGH HIGH NONE
If CSR4<00>BCON = 1,

I/O PIN 15 = BYTE (O/3S)

I/O PIN 16 = BUSAKO(O)
Byte selection is done using the BYTE line and DAL<00> latched during
the address portion of the bus transaction. MK5027drives BYTE only a
Bus Master and ignores it whena Bus Slave. Byte selectionis done as
outlined in the followingtable.

BYTE DAL<00> TYPE OF TRANSFER

LOW LOW ENTIRE WORD

LOW HIGH ILLEGAL CONDITION

HIGH LOW LOWER BYTE

HIGH HIGH UPPER BYTE
BUSAKOis a bus request daisy chain output. If MK5027 is notrequesting

the bus andit receives HLDA, BUSAKOwill bedriven low. If MK5027 is
requesting the bus when it receives HLDA, BUSAKOwill remain high.
Note: All transfers are entire word unlessthe MK5027 is configuredfor 8
bit operation.

HOLD

BUSRQ

17 IO/OD Pins 17is configuredthrough bit 0of CSR4.

If CSR4<00> BCON = 0,

I/O PIN 17 = HOLD
HOLD request is asserted by MK5027 when it requires a DMA cycle, if
HLDA is inactive, regardless of the previous state of the HOLD pin.
HOLD is heldlow for the entire ensuing bus transaction.
If CSR4<00> BCON = 1,

I/O PIN 17 = BUSRQ
BUSRQ is asserted by MK5027 when it requires a DMA cycleif the prior
state of theBUSRQpin was high and HLDA is inactive. BUSRQis held
low for the entire ensuing bus transaction.

ALE

AS

18 O/3S The active level of ADDRESS STROBE is programmable throughCSR4.

The address portion of a bustransfer occurs while this signal is at its
asserted level. This signal is driven by MK5027 while itis the BUS
MASTER. At all other times, the signal is tristated.
If CSR4<01> ACON = 0,

I/O PIN 18 = ALE
ADDRESSLATCHENABLE isused to demultiplex the DALlines and define
theaddress portion of thetransferand remains low during the data portion.
If CSR4<01> ACON = 1,

I/O PIN 18 = AS
As AS,the signalpulses lowduring the address portion of the bus
transfer. The low to hightransition of AScan be used by a slavedevice to
strobe the address into a register.
AS is effectively the inversion of ALE.

HLDA 19 I HOLD AKNOWLEDGE is theresponse to HOLD. Whe nHLDAis low inresponse

to MK5027’s assertion of HOLD, theMK5027 isthe BusMaster . HLDA should be
desasse rted ONLY a fter HOLDhas been re leased by the MK 5027.

MK5027

3/19

Table 1: PinDescription (continued)

Signal Name Pin(s) Type Descriplion

CS 20 I CHIP SELECT indicates, when low, that the MK5027 is the slave device

for the data transfer.CS must be valid througoutthe enture transaction.

ADR 21 I ADDRESS selects the Register Address Port or the Register Data Port. It

must be validthroughout thedata portion of thetransfer and is onlyused
by the chipwhen CS is low.

ADR PORT

LOW REGISTER DATA PORT

HIGH REGISTER ADDRESS PORT

READY 22 IO/OD When the MK5027 is a Bus Master, READYis an asynchronous

acknowledgement from the bus memory that memory will accept data in a
WRITE cycle or that memory has put data on the DAL lines in a READ
cycle.
As a bus Slave, the MK5027 asserts READYwhen it hasput data on the
DAL lines during a READcycle oris about to take datafrom the DAL lines
during WRITE cycle.READY is a response to DAS and it will be released
after DASor CS is negated.

RESET 23 I RESET isthe Bus signal that will cause MK5027 to cease operation, clear

its internal logic and enter an idle state with the Power Off bit of CSR0 set.

TCLK 25 I TRANSMIT CLOCK. A 1xclock input for transmitter timing. TD changes

on the falling edge of TCLK. The frequency of TCLKmay not be greater
than the frequency of SYSCLK.

DTR
RTS

26 IO DATA TERMINAL READY, REQUEST TO SEND. Modem controlpin. Pin

26 is configurablethrough CSR5. This pin can be programmed to behave
as output RTS or as programmable IO pin DTR. If configured as RTS, the
MK5027 will assert this pin if it has data to send and throughout the
transmission of a signal unit.

RCLK 27 I RECEIVE CLOCK. A 1x clock input for receiver timing. RD is sampled on

the rising edge of RCLK. The frequency of RCLK may not be greater than
the frequency of SYSCLK.

SYSCLK 28 I SYSTEM CLOCK. System clock used for internaltiming of the MK5027.

SYSCLK should be a square wave, of frequency up to 10MHz.

TD 29 O TRANSMIT DATA. Transmit serial dataoutput.

DSR
CTS

30 IO DATA SET READY, CLEAR TOSEND. Modem Control Pin. Pin 30 is

configurablethrough CSR5. This pin can beprogrammed to behave as
input CTS or as programmable IO pin DSR. If configured asCTS, the
MK5027 will transmit allones while CTS is high.

RD 31 I RECEIVE DATA. Received serialdata input.

A<23:16> 32-39 O/3S Address bits <23:16> used in conjunctionwith DAL <15:00> to produce a

24 bit address. MK5027 drives these lines only as a Bus Master.
A23-A20may be driven continuouslyas described in the CSR4<7>BAEN
bit.

VSS-GND 1, 24 GroundPins

VCC 48 Power Supply Pin

+5.0 VDC ± 5%

MK5027

4/19

Figure2: PossibleSystem Configurationfor the MK5027.

MK5027

5/19

OPERATIONALDECRIPTION

The SGS-THOMSON Signalling System #7 Sig­nalling Link Controller (MK5027) device is a VLSI
product intended for data communicationapplica­tionsrequiring SS7link level control. The MK5027
will perform all frame formatting, such as: frame
delimiting with flags, FCS generation and detec­tion. It will also perform all error recovery and link
control. The MK5027 also includes a buffer man­agement mechanism that allow the user to trans­mit and/or receive multiple MSU’s. Contained in
the buffer management is an on-chip dual chan-

nel DMA: one channel for receive and one chan­nel for transmit. The MK5027handles error recov­ery andlink statussignalling.

The MK5027 is intended to be used with any
popular 16 or 8 bit microprocessor. Possible sys­tem configurationfor the MK5027 is shown in Fig­ure 2. The MK5027 will move multiple blocks of
receive and transmit data directly into and out of
memory through the host’s bus. An I/O accelera­tion processor in Figure 2 is recommended, but
not required.

DALI

DALO

HLDA

HOLD

ALE, AS

BM0

BM1

DAS

READ

INTR

ADR

READY

DTR, RTS

DSR, CTS

CS

FIRMWARE

ROM

MICRO

CONTROLLER

TIMERS

DMA

CONTROLLER

CONTROL / STATUS
REGISTERS 0 - 5

SYSCLK

INTERNAL BUS

RECEIVER

FIFO

TRANSMITTER

FIFO

RECEIVER TRANSMITTER

LOOPBACK

TEST

RD

RCLK

TCLK

TD

VSS - GND
RESET

VCC

DAL<15:00>

A <23:16>

Figure3: MK5027 SimplifiedBlockDiagram.

MK5027

6/19