SGS Thomson Microelectronics M93S46-R, M93S56-R, M93S66-R Datasheet

1/32May 2003

M93S66, M93S56

M93S46

4Kbit, 2Kbit and 1Kbit (16-bit wide)

MICROWIRE Serial Access EEPROM with Block Protection

FEATURES SUMMARY

■ Industry Standard MICROWIRE Bus

■ Single Supply Voltage:

– 4.5V to 5.5V for M93Sx6 – 2.5V to 5.5V for M93Sx6-W – 1.8V to 5.5V for M93Sx6-R

■ Single Organization: by Word (x16)

■ Programming Instructions that work on: Word or

Entire Memory

■ Self-timed Programming Cycle with Auto-Erase

■ User Defined Write Protected Area

■ Page Write Mode (4 words)

■ Ready/Busy Signal During Programming

■ Speed:

– 1MHz Clock Rate, 10ms Write Time (Current

product, identified by process identification letter F or M)

– 2MHz Clock Rate, 5ms Write Time (New

Product, identified by process identification letter W)

■ Sequential Read Operation

■ Enhanced ESD/Latch-Up Behavior

■ More than 1 Million Erase/Write Cycles

■ More than 40 Year Data Retention

Figure 1. Packages

PDIP8 (BN)

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

TSSOP8 (DS)

3x3mm body size

M93S66, M93S56, M93S46

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SUMMARY DESCRIPTION

This specification covers a range of 4K, 2K, 1K bit serial Electrically Erasable Programmable Memory (EEPROM) products (respectively for M93S66, M93S56, M93S46). In this text, these products are collectively referred to as M93Sx6.

Figure 2. Logic Diagram

Table 1. Signal Names

The M93Sx6 is accessed through a serial input (D) and output (Q) us in g the MICROWIRE bus protocol. The memory is divided into 256, 128, 64 x16 bit words (respectively for M93S66, M93S56, M93S46).

The M93Sx6 is accessed by a set of instructions which includes Read, W rite, Page Write, Write All

and instructions used to set the memory protection. These are summarized in Table 2 and 3).

A Read Data from Memory (READ) instruction loads the address of the first word to be read into an internal address pointer. The data contained at this address is then clocked out serially. The address pointer is automatically incremented after the data is output and, if the Chi p S elect Input (S) is held High, the M93Sx6 can output a sequ ential stream of data words. In this way, the memory can be read as a data stream from 16 to 4096 bits (for the M93S66), or continuously as the address counter automatically rolls over to 0 0h when the highest address is reached.

Within the time required by a programming cycle (t

), up to 4 words may be written with help of the Page Write instruction. the whole memory may also be erased, or set to a predetermined pattern, by using the Write All instruction.

Within the memory, a us er defined area may be protected against further Write instructions. The size of this area is defined by the content of a Protection Register, located outside of the memory array. As a final protection step, data may be permanently protected by programm ing a One Time Programming bit (OT P bit) which l ocks t he Prote ction Register content.

Programming is internal ly self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle) and does not require an erase cycle prior to the Write instruction. The Write instruction writes 16 bits at a time into one of the word locations of the M93Sx6, the Page Write instruction writes up to 4 words of 16 bits to sequential locations, assum ing in both cases that all addresses are outside the Write Protected area. After the start of the programming cycle, a Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is driven High.

Figure 3. DIP, SO and TSSOP Connections

Note: 1. See page 26 (onwards) for package dimensions, and how

to identify pin-1.

S Chip Select Input D Serial Data Input Q Serial Data Output C Ser ial Clock PRE Protection Register Enable W Write Enable V

Supply Voltage

Ground

AI02020

M93Sx6

C Q

PRE

PREC

AI02021

M93Sx6

1 2 3 4

8 7 6 5

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M93S66, M93S56, M93S46

An internal Power-on Data P rot ection m ec hani sm in the M93Sx6 inhibits the device when the supply is too low.

POWER-ON DATA PROTECTION

To prevent data corruption and inadvertent write operations during power-up, a Power-On Reset (POR) circuit resets all internal programming circuitry, and sets the device in the Write Disable mode.

– At Power-up and P ower-down, the device must

not be selected (that is, Chip Select Input (S) must be driven Low) until the supply voltage reaches the operating value V

specified in

Table 5 to Table 6.

– When V

reaches its valid level, the d evice is properly reset (in the Write Disabl e mode) and is ready to decode and execute incoming instructions.

For the M93Sx6 devices (5V range) the POR threshold voltage is around 3 V. For the M 93Sx6W (3V range) and M93Sx6-R (2V range) the POR threshold voltage is around 1.5V.

INSTRUCTIONS

The instruction set of the M93Sx6 devices contains seven instructions, as summarized in Table 2 to Table 3. Each instruction consists of the following parts, as shown in Figure 4:

■ Each instruction is preceded by a rising edge on

Chip Select Input (S) with Serial Clock (C) being held Low.

■ A start bit, which is the first ‘1’ read on Serial

Data Input (D) during the rising edge of Serial Clock (C).

■ Two op-code bits, read on Serial Data Input (D)

during the rising edge of Serial Clock (C). (Some instructions also use the first two bits of the address to define the op-code).

■ The address bits of the byte or word that is to be

accessed. For the M93S46, the address is made up of 6 bits (see Table 2). For the M93S56 and M93S66, the address is made up of 8 bits (see Table 3).

The M93Sx6 devices are fabricated in CMOS technology and are therefore able to run as slow as 0 Hz (static input signals) or as fast as t he maximum ratings specified in Table 16 to Table 19.

M93S66, M93S56, M93S46

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Table 2. Instruction Set for the M93S46

Note: 1. X = Don’t Care bit.

Instruction Description W PRE

Start

bit

Op-

Code

Address

Data

Required

Clock

Cycles

Additional

Comments

READ

Read Data from Memory

X 0 1 10 A5-A0 Q15-Q0

WRITE

Write Data to Memory

1 0 1 01 A5-A0 D15-D0 25

Write is executed if the address is not inside the Protected area

PAWRITE

Page Write to Memory

1 0 1 11 A5-A0

N x

D15-D0

9 + N x 16

Write is executed if all the N addresses are not inside the Protected area

WRAL

Write All Memory with same Data

1 0 1 00 01 XXXX D15-D0 25

Write all data if the Protection Register is cleared

WEN Write Enable 1 0 1 00 11 XXXX 9 WDS Write Disable X 0 1 00 00 XXXX 9

PRREAD

Protection Register Read

X 1 1 10 XXXXXX

Q5-Q0

+ Flag

Data Output = Protection Register content + Protection Flag bit

PRWRITE

Protection Register Write

1 1 1 01 A5-A0 9

Data above specified address A5-A0 are protected

PRCLEAR

Protection Register Clear

1 1 1 11 111111 9

Protect Flag is also cleared (cleared Flag = 1)

PREN

Protection Register Enable

1 1 1 00 11XXXX 9

PRDS

Protection Register Disable

1 1 1 00 000000 9

OTP bit is set permanently

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M93S66, M93S56, M93S46

Table 3. Instruction Set for the M93S66, M93S56

Note: 1. X = Don’t Care bit.

2. Address bit A7 is not decoded by the M93S 56.

Instruction Description W PRE

Start

bit

Op-

Code

Address

1,2

Data

Required

Clock

Cycles

Additional

Comments

READ

Read Data from Memory

X 0 1 10 A7-A0 Q15-Q0

WRITE

Write Data to Memory

1 0 1 01 A7-A0 D15-D0 27

Write is executed if the address is not inside the Protected area

PAWRITE

Page Write to Memory

1 0 1 11 A7-A0

N x

D15-D0

11 + N x 16

Write is executed if all the N addresses are not inside the Protected area

WRAL

Write All Memory with same Data

1 0 1 00 01XXXXXX D15-D0 27

Write all data if the Protection Register is cleared

WEN Write Enable 1 0 1 00 11XXXXXX 11 WDS Write Disable X 0 1 00 00XXXXXX 11

PRREAD

Protection Register Read

X 1 1 10 XXXXXXXX

Q7-Q0

+ Flag

Data Output = Protection Register content + Protection Flag bit

PRWRITE

Protection Register Write

1 1 1 01 A7-A0 11

Data above specified address A7-A0 are protected

PRCLEAR

Protection Register Clear

1 1 1 11 11111111 11

Protect Flag is also cleared (cleared Flag = 1)

PREN

Protection Register Enable

1 1 1 00 11XXXXXX 11

PRDS

Protection Register Disable

1 1 1 00 00000000 11

OTP bit is set permane ntly

M93S66, M93S56, M93S46

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Figure 4. READ, WRITE, WEN and WDS Sequences

Note: For the mea ni ngs of An, Xn, Qn and Dn, see Ta bl e 2 and Table 3.

AI00889D

1 1 0 An A0

Qn Q0

DATA OUT

WRITE

ADDR

CODE

1 0An A0

DATA IN

CODE

Dn D01

BUSY READY

WRITE ENABLE

1 0XnX0D

CODE

101

WRITE DISABLE

1 0XnX0D

CODE

0 00

CHECK

STATUS

ADDR

PREREAD

PRE

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M93S66, M93S56, M93S46

Read

The Read Data from Memory (READ) instruction outputs serial data on Serial Data Output (Q). When the instruction is received, the op-code and address are decoded, and the data from the memory is transferred to an output shift register. A dummy 0 bit is output first, followed by the 16-bit word, with the most significant bit first. Output data changes are triggered by the rising edge of Serial Clock (C). The M93Sx6 au tomatically increments the internal address register and clocks out the next byte (or word) as long as the Chip Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read.

Write Enable and Write Disable

The Write Enable (WEN) instruction enables the future execution of write instructions, and the Write Disable (WDS) instruction disables it. When power is first app lied, the M9 3Sx6 initializes itse l f s o that write instructions are disabled. After an Write Enable (WEN) instruction has been executed, writing remains enabled until an Write Disable (WDS) instruction is exe cuted, or until V

falls below the power-on reset threshold voltage . To protect the memory contents from accidental corruption, it is advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read Data from Memory (READ) instruction is not affected by the Write Enable (WEN) or Write Disable (WDS) instructions.

Write

The Write Data to Memory (WRITE) instruction is composed of the Start bit plus the op-code followed by the address and the 16 data bits to be written.

Write Enable (W) mus t be held High before and during the instruction. Input a ddress and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C).

After the last data bit has been sampled, the C hip

Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input

(S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed.

While the M93Sx6 is performing a write cycle, but after a delay (t

SLSH

) before the s tatus inform ation becomes available, Chip S elect Input (S) can be driven High to monitor the status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle is complete, and the M93Sx6 is ready to receive a new instruction. The M93Sx6 ignores any data on the bus while it is busy on a wri te cycle. O nce t he M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low.

Programming is internally self-timed, so the external Serial Clock (C) may be disconnected o r left running after the start of a write cycle.

M93S66, M93S56, M93S46

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Figure 5. PA WR I TE and WRAL Sequence

Note: For the mea ni ngs of An, Xn an d Dn, please see Table 2 and Table 3.

Page Write

A Page Write to Memory (PAWRITE) instruction contains the first address to be written, followed by up to 4 data words.

After the receipt of each data w ord, bits A1-A 0 of the internal address register are incremented, the high order bits remaining unchanged (A7-A2 for M93S66, M93S56; A5-A2 for M93S46). Users must take care, in the software, to ensure that the last word address has the same upper order address bits as the initial address transmitted to avoid address roll-over.

The Page Write to Memory (PAWRITE) instruction will not be executed if any of the 4 words addresses the protected area.

Write Enable (W) mus t be held High before and during the instruction. Input a ddress and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C).

After the last data bit has been sampled, the C hip

Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input

(S) is brought Low before or after this specific time frame, the self-timed programming cycle will not

AI00890C

PAGE WRITE

1 1An A0

DATA IN

CODE

Dn D01

BUSY READY

CHECK

STATUS

ADDR

PRE

WRITE ALL

1 0XnX0

DATA IN

CODE

Dn D00

BUSY READY

CHECK

STATUS

ADDR

PRE

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M93S66, M93S56, M93S46

be started, and the addressed location will not be programmed.

While the M93Sx6 is performing a write cycle, but after a delay (t

SLSH

) before the s tatus inform ation becomes available, Chip S elect Input (S) can be driven High to monitor the status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle is complete, and the M93Sx6 i s ready to receive a new instruction. The M93Sx6 ignores any data on the bus while it is busy on a wri te cycle. O nce t he M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low.

Programming is internally self-timed, so the external Serial Clock (C) may be disconnected o r left running after the start of a write cycle.

Write All

The Write All Memory with same Data (WRAL) instruction is valid only after the Protection Register has been cleared by executing a Protection Register Clear (PRCLEAR) instruction. The Write All Memory with same Data (WRAL) instruction simultaneously writes the whole memory with the same data word given in the instruction.

Write Enable (W) mus t be held High before and during the instruction. Input a ddress and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C).

After the last data bit has been sampled, the C hip

Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input

(S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed.

While the M93Sx6 is performing a write cycle, but after a delay (t

SLSH

Programming is internally self-timed, so the external Serial Clock (C) may be disconnected o r left running after the start of a write cycle.

M93S66, M93S56, M93S46

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Figure 6. PREAD, PRWRITE and PREN Sequences

Note: For the mea ni ngs of An, Xn an d Dn, please see Table 2 and Table 3.

AI00891D

1 1 0 Xn X0

DATA

OUT

Protect Register WRITE

ADDR

CODE

1 0An A0D

CODE

BUSY READY

Protect Register ENABLE

1 0XnX0D

CODE

101

CHECK

STATUS

ADDR

PREProtect Register READ

PRE

An A0 F

F = Protect Flag

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