SGS Thomson Microelectronics M50LPW040 Datasheet

3V Supply Low Pin Count Flash Memory

■ SUPPLY VOLTAGE

= 3V to 3.6V for Program, Erase and

–V

Read Operations

–V

= 12V for Fast Program and Fast Erase

(option al)

■ TWO INTERFACES

– Low Pin Count (LPC) Standard I nterface for

embedded operation with PC Chipsets.

– Address/Address Multiplexed (A/A Mux) In-

terface for programm ing equipment compat ibility.

■ LPC HARDWARE INTERFACE MODE

– 5 Signal Communication Interface supporting

Read and Write Operations

– Hardware Write Protect Pins for Block Pro-

tection – Register Based Read and Write Protection – 5 Additional Ge neral Purp ose I nputs f or pla t-

form design flexibility – Synchronized with 33 MHz PCI clock

■ PROGR AMMING TIME

– 10µ s typical – Quadruple Byte Programming Option

■ 8 UNIFORM 64 Kbyte MEMORY BLOCKS

■ PROGRAM/ERA SE CON TROLLER

– Embedded Byte Program and Block/Chip

Erase algorithms – Status Register Bits

■ PROGRAM and ERASE SUSPEND

– Read other Blocks during Program/Erase

Suspend – Program other Blocks during Erase Suspend

■ FOR USE in PC BIOS APPLICATIONS

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Device Code: 26h

M50LPW040

4 Mbit (512Kb x8, Uniform Block)

PRELIMINARY DATA

TSOP40 (N)

10 x 20mm

Figure 1. Logic Diagram (LPC Interface)

ID0-ID2

M50LPW040

GPI0-

GPI4

LFRAME

CLK

INIT

PLCC32 (K)

LAD0LAD3

TBL

AI05435

March 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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M50LPW040

Figure 2. Logic Diagram (A/A Mux Interface)

A0-A10

M50LPW040

DQ0-DQ7

AI05436

DESCRIPTION

The M50LPW040 is a 4 Mbit (512Kb x8) nonvolatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast pro gramming and fast erasing in production lines an optional 12V power supply can be used to reduce the programming and the erasing times.

The memory is divided into blocks that can be erased independently so it is pos sible to pres erve valid data while old data is erased. Blocks can be protected individually to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the m emory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

Two different bus interfaces are supported by t he memory. The primary interface is the Low Pin Count (or LPC) Standard Interface. This has been designed to remove the need for the ISA bus in

Figure 3. TSOP Connections

IC (VIH)

NC NC NC NC

A10

NC RC

A/A Mux

RP NC NC

A9 A8 A7 A6 A5 A4 A3

IC (VIL)

NC NC INIT NC RFU NC

GPI4

CLK

RP NC

NC GPI3 GPI2 LAD0 GPI1 ID0 GPI0

TBL

M50LPW040

20 21

31 30

LFRAME

RFU RFU RFU RFU V

LAD3 LAD2 LAD1

ID1 ID2 RFU

W G RB DQ7 DQ6 DQ5 DQ4 V

DQ3 DQ2 DQ1 DQ0 A0 A1 A2

A/A Mux

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M50LPW040

current PC Chipsets; the M50LPW040 acts as the PC BIOS on the Low P in Count bus for these P C Chipsets.

The secondary interface, the Address/Address Multiplexed (or A/A Mux) Int erface, is design ed t o be compatible with current Flash Programmers for production line programming prior to fitting to a PC Motherboard.

The memory is offered in TSOP40 (10 x 20mm) and PLCC32 packages and it is supplied with all

the bits erased (set to ’1’).

SIGNAL DESCRIPTIONS

There are two different bus interfaces available on this part. The active interface is selected before power-up or during Reset using the Interface Configur a tion Pin, IC.

The signals for each interface are discussed in the Low Pin Count (LPC) Signal Descriptions section and the Address/Address M ultiplexed (A/A Mux) Signal Descriptions section below. The supply signals are discussed in the Supply S ignal Descriptions section below.

Table 1. Signal Names (LPC Interface) Memory

LAD0-LAD3 Input/Output Communications LFRAME ID0-ID2 Identification Inputs GPI0-GPI4 General Purpose Inputs IC Interface Configuration RP INIT CLK Clock TBL WP

RFU V

NC Not Connected Intern ally

Note: 1. Pin 9 in the PLCC32, and Pin 21 in the TSOP40, may also

be driven High or drive n Low.

Input Communication Frame

Interface Reset CPU Reset

Top Block Lock Write Protect Reserved for Future Use. Leave

disconnected Supply Voltage Optional Supply Voltage for Fast

Erase Operations Ground

Figure 4. PLCC Connections

A/A Mux A/A Mux

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

GPI1 GPI0

TBL

RFU

ID2 ID1 ID0

LAD0

GPI2

LAD1

DQ1

RPA8VPPV

VPPV

GPI3

M50LPW040

RFU

LAD3

DQ3

DQ4

LAD2

DQ2

CLK

RFU

DQ5

A10

GPI4

RFU

DQ6

IC (VIL) NC NC V

INIT LFRAME RFU RFU

IC (VIH) NC NC V

G W RB DQ7

A/A MuxA/A Mux

AI05438

Note: P i ns 27 and 28 are not interna l l y connected.

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M50LPW040

Table 2. Memory Identification Input Configuration

Memory Number ID2 ID1 ID0 A21 A20 A19

1 (Boot)

2 3 4 5 6 7 8

or floating VIL or floating VIL or floating

or floating VIL or floating V

or floating V

IH IH

VIL or floating VIL or floating VIL or floating V

VIL or floating

111

110 101 100 011 010 001 000

Low Pin Count (LPC) Signal Descriptions

For the Low Pin Count (LPC) Interface see Figure 1, Logic Diagram, and Table 1, Signal Names.

Input/Output Communications (LAD0-LAD3). All Input and Output Communication with the memory take place on these pi ns. Addresses and Data for Bus Read and Bus W rite operations are en coded on these pins.

Input Communication Frame (LFRAME

). The

) signals the start of a bus operation. When Input Communication Frame is Low, V

, on the rising edge of

the Clock a new bus operat ion is in itiated. If Input Communication Frame is L ow, V

, during a bus

operation then the operation is aborted. When Input Communication Frame is High, V

, the cur-

rent bus operation is proceeding or the bus is idle. Identification Inputs (ID0-ID2). The Identification

Inputs (ID0-ID2) allow to address up to 8 memories on a bus. The value on addresses A19A21 is compared to the hardware strapping on the ID0-ID2 pins to select which memory is being

addressed. For an address bit to be ‘1’ the correspondent ID pin c an be left floating or driven Low, V with a value of R correspondent ID pin must be driven High, V there will be a leakage current of I pin when pulled to V

; an internal pull-down resistor is included

. For an address bit to be ‘0’ the

through each

; see Table 20.

LI2

By convention t he boot memory must h ave ID0ID2 pins left floating or driven Low, V

and a ‘111’

value on A19-A21 and all additional memories take sequential ID0-ID2 configuration, as shown in Table 2.

General Purpose Inputs (GPI0-GPI4). The General Purpose Inputs can be used as digital inputs for the CPU to read. The General Purpose Input Register holds the values on these pins. The pins must

have stable data from before the start of the cycle that reads the General Purpose Input Register until after the cycle is complete. These pins must not be left to float, they should be driven Low, V High, V

Interface Configuration (IC). The Interface Configuration input selects whether the Low Pin Count (LPC) or the Address/Address Multiplexed (A/A Mux) Interface is used. The chosen interface must be selected before power-up or during a Reset and, thereafter, cannot be change d. The state of the Interface Configuration, IC, should not be changed during operation.

To select the Low Pin Count (LPC) Interface the Interface Configuration pin should be left to float or driven Low, V

; to select the Address/Address

Multiplexed (A/A Mux) Interface t he pin should be driven High, V included with a value of R current of I

. An internal pull-down resistor is

through each pin when pulled to VIH;

LI2

; there will be a leakage

see Table 20.

Interface Reset (RP

). The Interface Reset (RP)

input is used to reset the memory. When Interface Reset (RP

) is set Low, VIL, the memor y i s i n R ese t mode: the outputs are put to high impedance and the current consumption is minimized. When RP set High, V

;

After exiting Reset mode, the memory enters

, the memory is in no rmal operat ion.

Read mode.

CPU Reset (INIT

). The CPU Reset, INIT, pin is

used to Reset the memory when the CPU is reset . It behaves identically to Interface Reset, RP the internal Reset lin e is the logical OR (elec tric al AND) of RP

and INIT.

Clock (CLK). The Clock, CLK, input is used to clock the signals in and out of the Input/Output Communication Pins, LAD0-LAD3. The Clock conforms to the PCI specification.

IL,

, and

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M50LPW040

Top Blo ck Lock (TB L

). The Top Block Lock

input is used t o prevent the Top Block (Block 7) from being changed. When Top Block Lock, TBL is set Low, V

, Program and Block Erase

operations in the Top Block have no effect, regardless of the state of the Lock Register. When Top Block Lock, TBL

, is set High, VIH, the protection of the Block is determined by the Lock Register. The state of Top Block Lock, TBL

, does not affect the protection of the Main Blocks (Blocks 0 to 6).

Top Block Lock, TBL

, must be set prior to a Program or Block Erase operation is initiated and must not be changed until the operation completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing TBL

Wri te Protect (WP

during Program or Erase Suspend.

). The Write Protect input is used to prevent the Main Blocks (Blocks 0 to 6) from being chan ged. When W rite Protect, WP set Low, V

, Program and Block Erase operations

, is

in the Main Blocks have no effect, regardless of the state of the Lock Register. When Write Protect,

, is set High, VIH, the protection of the Block is

WP determined by the Lock Register. The state of Write Protect, WP

, does not affect the protection of

the Top Block (Block 7). Write Protect, WP

, must be set prior to a Program or Block Erase operation is initiated and mu st not be changed until the operation completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing WP

during Program or Erase Suspend.

Reserved for Future Use (RFU). These pins do not have assigned functions in this revision of the part. They must be left disconnected. (Pin 9 in the PLCC32, and Pin 21 in the T SOP 40, may al so be driven High or driven Low.)

Address/Address Multiplexed (A/A Mux) Signal Descriptions

For the Address/Address Multiplexed (A/A Mux) Interface see Figure 2, Logic Diagram, and Tabl e 3, Signal Names.

Address Inputs (A0-A10). The Address Inputs are used to set th e R ow A ddre ss bit s ( A0- A1 0) an d the Column Address bits (A11-A18). They are latched during any bus operation by the Row/C olumn Address Select input, RC

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs hold the data that is written to or read

Table 3. Signal Names (A/A Mux Interface)

IC Interface Configuration

A0-A10 Address Inputs DQ0-DQ7 Data Inputs/Outputs G W RC RB RP V

NC Not Connected Intern ally

Output Enable Write Enable Row/Column Address Select Ready/Busy Output Interface Reset Supply Voltage Optional Supply Voltage for Fast

Program and Fast Erase Operations

Ground

from the memory. They output the data s tored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the C ommand Interface of the internal state machine. The Data I nputs/Outputs, DQ0-DQ7, are latched during a Bus Write operation.

Output Enable (G

). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, controls

the Bus Write operation of the memory’s Command Interf a c e .

Row/Column Address Select (RC

). The Row/

Column Address Select input selects whether the Address Inputs should be latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A18). The Row Address bits are latched on the falling edge of RC

whereas the Column

Address bits are latched on the rising edge.

Ready/Busy Output (RB

). The Ready/Busy pin

gives the status of the memory’s Program/Erase Controller. When Ready/Busy is Low, V memory is busy with a Program or Erase operation and it will not accept any additional Program or Erase command except the Program/Erase Suspend command. When Ready/Busy is High, V

, the memory is ready for any Rea d, Program

or Erase operation.

, the

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M50LPW040

Table 4. Absolute Maximum Ratings

Symbol Parameter Value Unit

BIAS

STG

(2)

Note: 1. Except for the ratin g "Operati ng Temperature Range" , stresses above those listed i n t he Table "Absolute M aximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indi cated in t he Operating sect i ons of thi s specifi cation i s not impl i ed. Exposure to Absolute M aximum Rating c onditions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ity docum en ts .

2. Mini m um Voltage may undershoot to -2V and for less than 20 ns during transitions. Maximum Voltage may overshoot to V and for less th an 20ns duri ng t ransitions.

Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C

Ambient Operating Temperature (Temperature Range Option 5) –20 to 85 °C Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage Supply Voltage –0.6 to 4 V Program Voltage –0.6 to 13 V

Supply Signal Descriptions

The Supply Signals are the same for both interfaces.

Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the V Supply Voltage is less than the L ockout Voltage, V

. This prevents Bus Write operations from

LKO

accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. After V

becomes valid the Comma nd Interface

is reset to Read mode.

A 0.1µF capacitor should be connected between the V

Supply Voltage pins and the VSS Ground

pin to decouple the current surges from the power supply. Both V

Supply Voltage pins must be

connected to the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations.

Optional Supply Voltage. The VPP Optional

Supply Voltage pin is used to select the Fast Program (see the Quadruple Byte Program Command description) and Fast Erase options of the memory and to protect the memory. When V < V

Program and Erase operations cannot be

PPLK

performed and an error is reported in the Status Register if an attempt to change the memory contents is made. When V

= VCC Program and

Erase operations take place as normal. When V

= V

Fast Program (if a Quadruple Byte

PPH

Program Command is performed ) and Fast Erase operations are used. Any other voltage input to

(1)

–0.6 to V

will res ult in undefined beha vior and should

+ 0.6

+2V

not be used. V

should not be set to V

for more than 80

PPH

hours during the life of the memory.

Ground. VSS is the reference for al l the vol t-

age measurements.

BUS OPERATIONS

The two interfaces have similar bus operations but the signals and tim ings are compl etely different. The Low Pin Count (LPC) In terface is the usual interface and all of the functionality of the part is available through this in terface. Only a subset of functions are available through the Address/ Address Multiplexed (A/A Mux) Interface.

Follow the section Low Pin Count (LPC) Bus Operations below and the section Address/ Address Multiplexed (A/A Mux) Interface Bus Operations below for a description of the bus operations on each interface.

Low Pin Count (LPC) Bus Operations

The Low Pin Count (LPC) Interface consists of four data signals (LAD0-LAD3), one control line (LFRAME

) and a clock (CLK). In addition protection against accidental or malicious data corruption can be achieved using two further signals (TBL (RP

and INIT) are available to put the memory into

and WP). Finally two reset signals

a known state. The data signals, control signal and clock are

designed to be compatible with PCI electrical specifications. The interface operates with clock speeds up to 33MHz.

The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Standby, Reset and Block Protection.

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M50LPW040

Table 5. Block Addresses

Size

(Kbytes)

64 70000h-7FFFFh 7 Top Block 64 60000h-6FFFFh 6 Main Block 64 50000h-5FFFFh 5 Main Block 64 40000h-4FFFFh 4 Main Block 64 30000h-3FFFFh 3 Main Block 64 20000h-2FFFFh 2 Main Block 64 10000h-1FFFFh 1 Main Block 64 00000h-0FFFFh 0 Main Block

Note: For A19 value, refer to Table 2.

Address Range

Block

Number

Block Type

Bus Read. Bus Read operations read from the

memory cells, specific registers in the Command Interface or Low Pin Count Registers. A valid Bus Read operation starts when Input Communication Frame, LFRAME

, is Low, VIL, as Clock rises and the correct Start cycle is on LAD0-LAD3. On the following clock cycles the Host will send the Cycle Type + Dir, Address and other control bits on LAD0-LAD3. The memory responds by outputting Sync data until the wait-states have elapsed followed by Data0-Data3 and Data4-Data7.

Refer to Table 6, and Figure 5, for a description of the Field definitions for each clock cycle of the transfer. See Table 22, LPC Interface AC Signal Timing Characteristics and Figure 1 0, LPC Interface AC Signal Timing W aveforms, for details on the timings of the signals.

Bus Write. Bus Write operations write to the Command Interface or Low Pin Count Registers. A valid Bus Write operation starts when Input Communication Frame, LFRAME

, is Low, VIL, as Clock rises and the correct Start cycle is on LAD0LAD3. On the following Clock cycles the Host will send the Cycle Type + Dir, Add ress, other c ontrol bits, Data0-Data3 and Data4-Data7 on LAD0LAD3. The memory outputs Sync data until the wait-states have elapsed.

Refer to Table 7, LPC Bus Write Field Definitions, and Figure 6, LPC Bus Write Waveforms, for a description of the Field definitions for each clock cycle of the transfer. See Table 22, LPC Interface AC Signal Timing Characteristics and Figure 10, LPC Interface AC Signal Timing Wa veforms, for details on the timings of the signals.

Bus Abort. The Bus Abort operation can be used to immediately abort the current bus operation. A Bus Abort occurs when LFRAME V

, during the bus o peration; the m emory wi ll tri-

is driven Low,

state the Input/Output Communication pins, LAD0-LAD3.

Note that, during a Bus Write operation, the Command Interface starts executing the command as soon a s the data is f ully received; a Bus Abort during the final TAR cycles is not guaranteed to abort the command; the bus, however, will be released immediately.

Standby. When LFRAME

is High, VIH, the memory is put into Standb y mode where LA D0LAD3 are put into a high-impedance state and the Supply Current is reduced to the Standby level, I

CC1

Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when Interface Reset, RP Rese t, IN IT Low, V

, is Low, VIL. RP or IN IT must be held

, for t

. The memory resets to Read

PLPH

, or CPU

mode upon return from Res et mo de and the Lock Registers return to their default states regardless of their state before Reset, see Table 15. If RP INIT

goes Low, VIL, during a Program or Erase

operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to t

PLRH

to abort a

Program or Erase operation. Block Protection. Block Protection can be

forced using the signals Top Block Lock, TBL Write Protect, WP

, regardless of the state of the

, and

Lock Registers.

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M50LPW040

Table 6. LPC Bus Read Field Definitions

Clock Cycle

Number

Clock Cycle

Count

Field

LAD0-

LAD3

Memory

I/O

Description

1 1 STAR T 0000b I

CYCTYPE

+ DIR

0100b I

3-10 8 ADDR XXXX I

11 1 TAR 1111b I

12 1 TAR

1111b

(float)

13-14 2 WSYNC 0101b O

15 1 RSYNC 0000b O

16-17 2 DATA XXXX O

18 1 TAR 1111b O

On the rising edge of CLK with LFRAME

Low, the contents of LAD0-LAD3 must be 0000b to indicate the start of a LPC cycle.

Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1 indicates the direction of transfer: 0b for read. Bit 0 is 0

A 32-bit address phase is transferred starting with the most significant nibble first. A23-A31 must be set to 1. A22 = 1 for Array, A22 = 0 for registers access. For A19-A21 values, refer to Table 2.

The host drives LAD0-LAD3 to 1111b to indicate a turnaround cycle.

The LPC Flash Memory takes control of LAD0-LAD3 during

this cycle. The LPC Flash Memory drives LAD0-LAD3 to 0101b (short

wait-sync) for two clock cycles, indicating that the data is not yet available. Two wait-states are always included.

The LPC Flash Memory drives LAD0-LAD3 to 0000b, indicating that data will be available during the next clock cycle.

Data transfer is two CLK cycles, starting with the least significant nibble.

The LPC Flash Memory drives LAD0-LAD3 to 1111b to indicate a turnaround cycle.

19 1 TAR

1111b

(float)

Figure 5. LPC Bus Read Waveforms

CLK

LFRAME

LAD0-LAD3

Number of clock cycles

START

CYCTYPE

+ DIR

1182322

N/A

ADDR TAR SYNC DATA TAR

The LPC Flash Memory floats its outputs, the host takes control of LAD0-LAD3.

AI04429

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Table 7. LPC Bu s W ri te Fiel d De finitions

Clock Cycle

Number

Clock Cycle

Count

Field

LAD0-

LAD3

Memory

I/O

M50LPW040

Description

1 1 START 0000b I

CYCTY

PE +

011Xb I

DIR

3-10 8 A DDR XXXX I

11-12 2 DATA XXXX I

13 1 TAR 1111b I

14 1 TAR

1111b

(float)

15 1 SYNC 0000b O

16 1 TAR 1111b O

17 1 TAR

1111b

(float)

N/A

On the rising edge of CLK with LFRAME

Low, the contents of LAD0-LAD3 must be 0000b to indicate the start of a LPC cycle.

Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1

indicates the direction of transfer: 1b for write. Bit 0 is don’t care (X).

A 32-bit address phase is transferred starting with the most significant nibble first. A23-A31 must be set to 1. A22 = 1 for Array, A22 = 0 for registers access. For A19-A21 values, refer to Table 2.

Data transfer is two cycles, starting with the least significant nibble.

The host drives LAD0-LAD3 to 1111b to indicate a turnaround cycle.

The LPC Flash Memory takes control of LAD0-LAD3 during

this cycle. The LPC Flash Memory drives LAD0-LAD3 to 0000b,

indicating it has received data or a command. The LPC Flash Memory drives LAD0-LAD3 to 1111b,

indicating a turnaround cycle. The LPC Flash Memory floats its outputs and the host takes

control of LAD0-LAD3.

Figure 6. LPC Bus Write Waveforms

CLK

LFRAME

LAD0-LAD3

Number of clock cycles

START

1182212

CYCTYPE

+ DIR

ADDR DATA TAR SYNC TAR

AI04430

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M50LPW040

Table 8. A/A Mux Bus Operations

Operation G W RP

Bus Read Bus Write Output Disable Reset

or V

Table 9. Manufacturer and Device Codes

Operation G

Manufacturer Code Device Code

VIL or V

W RP A18-A1 A0 DQ7-DQ0

Don’t Care Data Output

VCC or V

Don’t Care Hi-Z Don’t Care Hi-Z

V V

PPH

DQ7-DQ0

Data Input

20h 26h

Address/Address Multiplexed (A/A Mux) Bus Operations

The Address/Address Multiplexed (A/A Mux) Interface has a more traditional style interface. The signals consist of a multiplexed address signals (A0-A10), data signals, (DQ0-DQ7) and three control signals (RC signal, RP

, can be used to reset the memory.

, G, W). An additional

The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash Programming equipment for faster factory programming. Only a subset of the features available to the Low Pin Count (LPC) Interface are available; these include all the Commands but exclude the Security features and other registers.

The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Output Disable and Reset.

When the Address/Address Multiplexed (A/A Mux) Interface is selected all the blocks are unprotected. It is not possible to protect any blocks through this interface.

Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature and the Status Register. A valid Bus Read operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC Write Enable (W be High, V

) and Interface Reset (RP) must

, and Output Enable, G, Low, VIL, in

. Then

order to perform a Bus Read operation. The Data Inputs/Outputs will output the value, see Figure 12, A/A Mux Interface Read AC Waveforms , and Table 24, A/A Mux Interface Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC the Data Inputs/Outputs; Output Enable, G Interface Reset, RP Enable, W

, must be Low, VIL. The Data Inputs/

. The data should be set up on

, and

, must be High, VIH and Write

Outputs are latched on the rising edge of Write Enable, W

. See Figure 13, A/A Mux Interface Write AC Waveforms, and Table 25, A/A Mux Interface Write AC Characteristics, for details of the timing requirements.

Output Disa bl e . The data outputs are high-impedance when the Output Enable, G

, is at VIH.

Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when RP held Low, V

for t

is Low, VIL. RP must be

. If RP is goes Low, VIL,

PLPH

during a Program or Erase operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to t

to abort a Program or Erase operation.

PLRH

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations.

After power-up or a Reset operation the memory enters Read mode.

The commands are summarized in Table 11, Commands. Refer to Tab le 1 1 in conjun ction with the text descriptions below.

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M50LPW040

Read Memory A rray Command. The Read Mem-

ory Array command returns the memory to its Read mode where it behaves like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read operations will access the memory array.

While the Program/Erase Controller is executing a Program or Erase operation the m emory will not accept the Read Memory Array command until the operation completes.

Read Statu s Register Command. T he Read Status Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read operations read the Status Register until another command is issued. See the section on the Status Register for details on the definitions of the Status Register bits.

Read Electronic S ignature C ommand. The Read Electronic Signature command is used to read the Manufacturer Code and the Device Code. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued subsequent Bus Read operations read the Manufacturer Code or the Device Code until a Read Memory Array command is issued.

After the Read Electronic Signature Command is issued the Manufacturer Code and Devi ce Code can be read using Bus Read op erations us ing the addresses in Table 10.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the address and data in the internal state m achine and starts the Program/Erase Controller. Once the command is issued subsequent Bus R ead operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits.

If the address falls in a pro tected block then the Program operation will abort, the data in the memory array will no t be changed and the S tatus Register will output the error.

During the Program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Program times are given in Table 12.

Note that the Program command cannot change a

bit set at ‘0’ back to ‘1’ and attempting to do so will

Table 10. Read Electronic Signature

Code Address Data

Manufacturer Code 00000h 20h Device Code 00001h 26h

Note: For A19 value, refer to Table 2.

not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to ‘1’.

See Figure 14, Program Flowchart and Pseudo Code, for a suggested flowchart on using the Program command.

Quadruple Byte Program Command. The Quadruple Byte Program Comman d c an be only used in A/A Mux mode to program four adjacent bytes in the memory array at a time. The four bytes must differ only for the addresses A0 and A1. Programming should not be attempted when V is not at V

is below V

if V

. The operation can also be executed

PPH

, but result could be uncertain.

PPH

Five Bus Write operations are required to issue the command. The second, the third and the fourth Bus Write cycle latches respectively the address and data of the first, the second and the third byte in the internal state machine. The fifth Bus Write cycle latches the address and data of the fourth byte in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus R ead operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits.

During the Quadruple Byte Program operation the memory will only accept the Read Status register command and the Program/Erase Suspe nd command. All other commands will be ignored. Typical Quadruple Byte Program times are given in Table

12. Note that the Quadruple Byte Program comm and

cannot change a bit set to ‘0’ back to ‘1’ and attempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to ‘1’.

See Figure 15, Quadruple Byte Program Flowchart and Pseudo Code, for a suggested flowchart on using the Quadruple Byte Program command.

Chip Erase Command. The Chip Erase Command can be only used in A/A Mux mode to erase the entire chip at a time. Erasing should not be attempted when V can also be executed if V

is not at V

PPH

is b elow V

. The operation

, but re-

PPH

sult could be uncertain. Two Bus Write operations are required to issue the com mand and start the Program/Erase Controller. Once the command is issued subsequent Bus R ead operations read the

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