terface for programm ing equipment com patibility
■ FIRMWARE HUB (FWH) HARDWARE
INTERFACE MODE
– 5 Signal Communication Interface supporting
Read and Write Operations
– Hardware Write Protect Pins for Block Pro-
tection
– Register Based Read and Write Protection
– 5 Additional Ge neral Pu rpose I nput s f or pla t-
form design flexibility
– Synchronized with 33MHz PCI clock
■ PROGRAMMING TIME
– 10µ s typical
– Quadruple Byte Programming Option
■ 16 UNIFORM 64 Kbyte MEMORY BLOCKS
■ PROGRAM/ERA SE CON T ROL LER
– Embedded Byte Program and Block/Chip
Erase algorithms
– Status Register Bits
■ PROGRAM and ERASE SUSPEND
– Read other Blocks during Program/Erase
Suspend
– Program other Blocks during Erase Suspend
■ FOR USE in PC BIOS APPLICATIONS
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 2Dh
M50FW080
8 Mbit (1Mb x8, Uniform Block)
V
PP
TSOP40 (N)
10 x 20mm
4
FWH0FWH3
WP
TBL
AI03979
PLCC32 (K)
Figure 1. Logi c D iag ram ( FWH I nte rfa ce)
V
CC
4
ID0-ID3
IC
RP
5
M50FW080
V
SS
FGPI0-
FGPI4
FWH4
CLK
INIT
1/36March 2002
M50FW080
Figure 2. Logic Diagram (A/A Mux Interface)
V
A0-A10
RC
IC
W
RP
V
11
M50FW080
G
V
CC
SS
PP
8
DQ0-DQ7
RB
AI03981
DESCRIPTION
The M50FW080 is a 8 Mbit (1Mb x8) non-volatile
memory that can be read, erased and
reprogrammed. These operations can be
performed using a single low voltage (3.0 to 3.6V)
supply. For fast pro gramming and fast erasing in
production lines an optional 12V power supply can
be used to reduce the programming and the
erasing times.
The memory is divided into blocks that can be
erased independently so it is pos sible to pres erve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are
written to the Command Interface of the m emory.
An on-chip Program/Erase Controller simplifies
the process of programming or erasing the
memory by taking care of all of the special
operations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions
identified. The command set required to control
the memory is consistent with JEDEC standards.
Two different bus interfaces are supported by t he
memory. The primary interface, the Firmware Hub
(or FWH) Interface, uses Intel’s proprietary FWH
protocol. This has been designed to remove the
Figure 3. PLCC Connections
A/A MuxA/A Mux
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
FGPI1
FGPI0
WP
TBL
ID3
ID2
ID1
ID0
FWH0
9
RPA8VPPV
A9
RP
FGPI2
FGPI3
M50FW080
V
FWH1
FWH2
V
DQ1
DQ2
1
17
SS
SS
CC
CC
VPPV
32
RFU
FWH3
DQ3
DQ4
RC
CLK
RFU
DQ5
A10
FGPI4
25
RFU
DQ6
IC (VIL)
NC
NC
V
SS
V
CC
INIT
FWH4
RFU
RFU
IC (VIH)
NC
NC
V
SS
V
CC
G
W
RB
DQ7
A/A MuxA/A Mux
AI04897
Note: Pins 27 and 28 are not internally co nnected.
2/36
M50FW080
need for the ISA bus in current PC Chipsets; the
M50FW080 acts as the PC BIOS on the Low P in
Count bus for these PC Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Int erface, is design ed t o
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is offered in TSOP40 (10 x 20mm)
and PLCC32 packages and it is supplied with all
the bits erased (set to ’1’).
SIGNAL DESCRIPTIONS
There are two different bus interfaces available on
this part. The active interface is selected before
power-up or during Reset using the Interface Configur a tion Pin, IC.
The signals for each interface are discussed in the
Firmware Hub (FWH) Signal Descriptions section
and the Address/Address M ultiplexed (A/A Mux)
Signal Descriptions section below. The supply signals are discussed in the Supply S ignal Descriptions section below.
Firmware Hub (FWH) Signal Descriptions
For the Firmware Hub (FWH) Interface see Figure
1, Logic Diagram, and Table 1, Signal Names.
Table 1. Signal Names (FWH Interface)
FWH0-FWH3Input/Output Communications
FWH4Input Communication Frame
ID0-ID3Identification Inputs
FGPI0-FGPI4General Purpose Inputs
ICInterface Configuration
RP
INIT
CLKClock
TBL
WP
RFU
V
CC
V
PP
V
SS
NCNot Connected Intern ally
Interface Reset
CPU Reset
Top Block Lock
Write Protect
Reserved for Future Use. Leave
disconnected
Supply Voltage
Optional Supply Voltage for Fast
Erase Operations
Ground
Figure 4. TSOP Connection s
NC
IC (VIH)
NC
NC
NC
NC
A10
NC
RC
V
CC
V
PP
A/A Mux
RP
NC
NC
A9
A8
A7
A6
A5
A4A3
NC
IC (VIL)
NC
NCINIT
NCRFU
NC
FGPI4
NC
CLK
V
CC
V
PP
RP
NC
NC
FGPI3
FGPI2FWH0
FGPI1ID0
FGPI0
WP
TBL
1
10
M50FW080
11
2021
40
31
30
V
SS
V
CC
FWH4
RFU
RFU
RFU
RFU
V
CC
V
SS
V
SS
FWH3
FWH2
FWH1
ID1
ID2
ID3
V
SS
V
CC
W
G
RB
DQ7
DQ6
DQ5
DQ4
V
CC
V
SS
V
SS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A/A Mux
AI03980
3/36
M50FW080
Table 2. Signal Names (A/A Mux Interface)
ICInterface Configuration
A0-A10Address Inputs
DQ0-DQ7Data Inputs/Outputs
G
W
RC
RB
RP
V
CC
V
PP
V
SS
NCNot Connected Internally
Output Enable
Write Enable
Row/Column Address Select
Ready/Busy Output
Interface Reset
Supply Voltage
Optional Supply Voltage for Fast
Program and Fast Erase
Operations
Ground
Input/Output Communications (FWH0-FWH3). All
Input and Output Communication with the memory
take place on th ese pins. Addresses and Dat a f or
Bus Read and Bus Wri te operations are encod ed
on these pins.
Input Communication Frame (FWH4). The Input Communication Frame (FWH4) signals the
start of a bus operation. When Input Communication Frame is Low, V
, on the rising edge of the
IL
Clock a new bus operation is initiated. If Input
Communication Frame is Lo w, V
, during a bus
IL
operation then t he operation is ab orted. When Input Communication Frame is High, V
, the cur-
IH
rent bus operation is proceeding or the bus is idle.
Identification Inputs (ID0-ID3). The
Identification Inputs select the address that the
memory responds to. Up to 1 6 memories c an be
addressed on a bus. For an ad dress bit to be ‘0’
the pin can be left floating or driven Low, V
IL
; an
internal pull-down resistor is included with a value
. For an address bit to be ‘1’ the pin must be
of R
IL
driven High, V
through each pin when pulled to VIH; see Table
I
LI2
; there will be a leakage current of
IH
19.
By convention the boot memory must have
address ‘0000’ and all additional memories take
sequential addresses starting from ‘0001’.
General Purpose Inputs (FGPI0-FGPI4). The General Purpose I nputs can be u sed a s digit al inputs
for the CPU to rea d. The General Purpos e Input
Register holds the values on these pins. The pins
must have stable data f rom before t he s tart of t he
cycle that reads the General Purpose Input Register until after the cycle is complete. These pins
must not be left to float, they should be driven Low,
V
or High, VIH.
IL,
Interface Configuration (IC). The Interface Configuration input selects whether the Firmware Hub
(FWH) or the Address/Address Multiplexed (A/A
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
and, thereafter, cannot be change d. The state of
the Interface Configuration, IC, should not be
changed during operation.
To select the Firmware Hub (FWH) Interface the
Interface Configuration pin should be left to float or
driven Low, V
; to select the Address/Address
IL
Multiplexed (A/A Mux) Interface t he pin should be
driven High, V
included with a value of R
current of I
. An internal pull-down resistor is
IH
through each pin when pulled to VIH;
LI2
; there will be a leakage
IL
see Table 19.
Interface Reset (RP
). The Interface Reset (RP)
input is used to reset the memory. When Interface
Reset (RP
) is set Low, VIL, the memor y i s i n R ese t
mode: the outputs are put to high impedance and
the current consumption is minimized. When RP
set High, V
, the memory is in no rmal operat ion.
IH
is
After exiting Reset mode, the memory enters
Read mode.
CPU Reset (INIT
). The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset .
It behaves identically to Interface Reset, RP
, and
the internal Reset lin e is the logical OR (elec tric al
AND) of RP
and INIT.
Clock (CLK). The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, FWH0-FWH3. The Clock
conforms to the PCI specification.
Top Block Lock (TB L
). The Top Block Lock
input is used to prevent the Top Block (Block 15)
from being chan ged. When Top Block Lock, T BL
is set Low, V
, Program and Block Erase
IL
operations in the Top Block have no effect,
regardless of the state of the Lock Register. When
Top Block Lock, TBL
, is set High, VIH, the
protection of the Block is determined by the Lock
Register. The state of Top Block Lock, TBL
, does
not affect the protection of the Main Blocks (Blocks
0 to 14).
Top Block Lock, TBL
, must be set prior to a Program or Block Erase operation is initiated and
must not be changed until the operation completes
or unpredictable results may occur. Care should
be taken to avoid unpredictable behavior by
changing TBL
during Program or Erase Suspend.
,
4/36
M50FW080
Table 3. Absolute Maximum Ratings
SymbolParameterValueUnit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
V
PP
Note: 1. Except f or the rating "Oper ating Temperature R ange", str esses above those l i sted in the T able "Abs ol ute Maxi m um Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indi cated in the Operating sections of this s pecification is not i mplied. Exposu re to Ab solute Ma xi m um Rati ng conditions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ity docum en ts .
2. Minimum Volta ge may unders hoot to –2V and fo r less than 20ns during transitions. Maximum Voltage may overshoot to V
and for less th an 20ns duri ng transitions.
Ambient Operating Temperature (Temperature Range Option 1)0 to 70°C
Ambient Operating Temperature (Temperature Range Option 5)–20 to 85°C
Temperature Under Bias–50 to 125°C
Storage Temperature–65 to 150°C
Input or Output Voltage
Supply Voltage–0.6 to 4V
Program Voltage–0.6 to 13V
Write Protect (WP). The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 14)
from being changed. W hen Write P rotect, WP
set Low, V
, Program and Block Erase operations
IL
in the Main Blocks have no effect, regardless of
the state of the Lock Register. When Write Protect,
, is s et High, VIH, the protection of the B lock
WP
determined by the Lock Register. The state of
Write Protect, WP
, does not affect the protection of
the Top Block (Block 15).
Write Protect, WP
, must be set prior to a Program
or Block Erase operation is initiated and must not
be changed until the o peration completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing
WP
during Program or Erase Suspend.
Reserved for Future Use (RFU). These pins do
not have assigned func tions i n this revision of the
part. They must be left disconnected.
Address/Address Multiplexed (A/A Mux)
Signal Descriptions
For the Address/Address Multiplexed (A/A Mux)
Interface see Figure 2, Logi c Diagram, and Table
2, Signal Names.
Address Inputs (A0-A10). The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A19). They are
latched during any bus operation by the Row/ Column Address Select input, RC
.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
(1)
, is
–0.6 to V
CC
+ 0.6
CC
V
+ 2V
the selected address during a Bus Read operation. During Bus Write operations they represent
the commands sent to the C ommand Interface of
the internal state machine. The Data I nputs/Outputs, DQ0-DQ7, are latched during a Bus Write
operation.
Output Enable (G
). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W
). The Write Enable, W, controls
the Bus Write operation of the memory’s Command Interf a c e .
Row/Column Address Select (RC
). The Row/
Column Address Select input selects whether the
Address Inputs should be latched into the Row
Address bits (A0-A10) or the Column Address bits
(A11-A19). The Row Address bits are latched on
the falling edge of RC
whereas the Column
Address bits are latched on the rising edge.
Ready/Busy Output (RB
). The Ready/Busy pin
gives the status of the memory’s Program/Erase
Controller. When Ready/Busy is Low, V
OL
, the
memory is busy with a Program or Erase operation
and it will not accept any additional Program or
Erase command except the Program/Erase
Suspend command. When Ready/Busy is High,
V
, the memory is ready for any Rea d, Program
OH
or Erase operation.
Supply Signal Descriptions
The Supply Signals are the same for both interfaces.
puts/Outputs hold the data that is written to or read
from the memory. They output the data s tored at
supplies the power for all operations (Read, Program, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the L ockout Voltage,
. This prevents Bus Write operations from
V
LKO
accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the
memory contents being altered will be invalid.
After V
becomes valid the Comma nd Interface
CC
is reset to Read mode.
A 0.1µF capacitor should be connected between
the V
Supply Voltage pins and the VSS Ground
CC
pin to decouple the current surges from the power
supply. Both V
Supply Voltage pins must be
CC
connected to the power supply. The PCB track
widths must be sufficient to carry the currents
required during program and erase operations.
Optional Supply Voltage. The VPP Optional
V
PP
Supply Voltage pin is used to select the Fast
Program (see the Quadruple Byte Program
Command description) and Fast Erase options of
the memory and to protect the memory. When V
< V
Program and Erase operations cannot be
PPLK
PP
performed and an error is reported in the Status
Register if an attempt to change the memory
contents is made. When V
Erase operations take place as normal. When V
= VCC Program and
PP
PP
= V
Fast Program (if A/A Mux interface is
PPH
selected) and Fast Erase operations are used.
Any other voltage input to V
will result in
PP
undefined behavior and should not be used.
should not be set to V
V
PP
for more than 80
PPH
hours during the life of the memory.
V
Ground. VSS is the reference for al l the vol t-
SS
age measurements.
BUS OPERATIONS
The two interfaces have similar bus operations but
the signals and tim ings are com pletely different.
The Firmware Hub (FWH) Interface is the usual
interface and all of the functionality of the part is
available through this in terface. Only a subset of
functions are available through the Address/
Address Multiplexed (A/A Mux) Interface.
Follow the section Firmware Hub (FWH) Bus
Operations below and the section Address/
Address Multiplexed (A/A Mux) Interface Bus
Operations below for a description of the bus
operations on each interface.
Firmware Hub (FWH) Bus Operations
The Firmware Hub (FWH) Interface consists of
four data signals (FWH0-FWH3), one cont rol line
(FWH4) and a clock (CLK). In addition protect ion
against accidental or malicious data corruption
can be achieved using two further signals (TBL
and WP). Finally two reset signals (RP and INIT )
are available to put the memory into a known
state.
The data signals, control signal and clock are
designed to be compatible with PCI electrical
specifications. The interface operates with clock
speeds up to 33MHz.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Standby, Reset and Block Protection.
Bus Read. Bus Read operations read from the
memory cells, specific registers in the Command
Interface or Firmware Hub Reg isters. A valid B us
Read operation starts when Input Communication
Frame, FWH4, is Low, V
, as Clock rises and the
IL
correct Start cycle is on FWH0-FWH3. On the
following clock cycles the Host will send the
Memory ID Select, Address and other control bits
on FWH0-FWH3. The memory responds by
outputting Sync data until the wait-states have
elapsed followed by Data0-Data3 and Data4Data7.
Refer to Table 5, FWH Bus Read Field Definitions,
and Figure 5, FWH Bus Read Waveforms, for a
description of the Field definitions for each clock
cycle of the transfer. See Table 21, FWH Interface
AC Signal Timing Characteristics and Figure 10,
FWH Interface AC Signal Timing Waveforms, for
details on the timings of the signals.
6/36
Tabl e 5. FWH Bus Read Field Definitions
Clock
Cycle
Number
Clock
Cycle
Count
Field
FWH0-
FWH3
Memory
I/O
M50FW080
Description
11START1101bI
On the rising edge of CLK with FWH4 Low, the contents of
FWH0-FWH3 indicate the start of a FWH Read cycle.
Indicates which FWH Flash Memory is selected. The value
21IDSELXXXXI
on FWH0-FWH3 is compared to the IDSEL strapping on the
FWH Flash Memory pins to select which FWH Flash
Memory is being addressed.
3-97ADDRXXXXI
A 28-bit address phase is transferred starting with the most
significant nibble first.
101MSIZE0000bIAlways 0000b (only single byte transfers are supported).
111TAR1111bI
121TAR
1111b
(float)
The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
The FWH Flash Memory takes control of FWH0-FWH3
O
during this cycle.
The FWH Flash Memory drives FWH0-FWH3 to 0101b
13-142WSYNC0101bO
(short wait-sync) for two clock cycles, indicating that the data
is not yet available. Two wait-states are always included.
The FWH Flash Memory drives FWH0-FWH3 to 0000b,
151RSYNC0000bO
indicating that data will be available during the next clock
cycle.
16-172DATAXXXXO
181TAR1111bO
191TAR
1111b
(float)
N/A
Data transfer is two CLK cycles, starting with the least
significant nibble.
The FWH Flash Memory drives FWH0-FWH3 to 1111b to
indicate a turnaround cycle.
The FWH Flash Memory floats its outputs, the host takes
control of FWH0-FWH3.
On the rising edge of CLK with FWH4 Low, the contents of
FWH0-FWH3 indicate the start of a FWH Write Cycle.
Indicates which FWH Flash Memory is selected. The value
on FWH0-FWH3 is compared to the IDSEL strapping on the
FWH Flash Memory pins to select which FWH Flash
Memory is being addressed.
A 28-bit address phase is transferred starting with the most
significant nibble first.
Data transfer is two cycles, starting with the least significant
nibble.
The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
The FWH Flash Memory takes control of FWH0-FWH3
O
during this cycle.
The FWH Flash Memory drives FWH0-FWH3 to 0000b,
indicating it has received data or a command.
The FWH Flash Memory drives FWH0-FWH3 to 1111b,
indicating a turnaround cycle.
The FWH Flash Memory floats its outputs and the host takes
control of FWH0-FWH3.
Figure 6. FWH Bus Write Waveforms
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
STARTIDSELADDRMSIZEDATATARSYNCTAR
11712212
Bus Write. Bus Write operations write to the
Command Interface or Firmware Hub Registers. A
valid Bus Write operation starts when Input
Communication Frame, FWH4, is Low, V
IL
, as
Clock rises and the correct Start cycle is on
FWH0-FWH3. On the following Clock cycles the
Host will send the Memory ID Select, Address,
other control bits, Data0-Data3 and Data4-Data7
on FWH0-FWH3. The memory outputs Sync data
until the wait-states have elapsed.
AI03441
Refer to Table 6, FWH Bus Write Field Definitions,
and Figure 6, FWH Bus Write Waveforms, for a
description of the Field definitions for each clock
cycle of the transfer. See Table 21, FWH Interface
AC Signal Timing Characteristics and Figure 10,
FWH Interface AC Signal Timing Waveforms, for
details on the timings of the signals.
Bus Abort. The Bus Abort operation can be used
to immediately abort the current bus operation. A
Bus Abort occurs when FWH4 is driven Low, V
IL
,
8/36
Table 7. A/A Mux Bus Operations
OperationGWRP
Bus Read
Bus Write
Output Disable
Reset
V
IL
V
IH
V
IH
V
or V
IL
IH
V
IH
V
IL
V
IH
VIL or V
Table 8. Manufacturer and Device Codes
OperationG
Manufacturer Code
Device Code
V
IL
V
IL
WRPA19-A1A0DQ7-DQ0
V
IH
V
IH
M50FW080
V
PP
V
IH
V
IH
V
IH
IH
V
IL
V
IH
V
IH
Don’t CareData Output
VCC or V
Don’t CareHi-Z
Don’t CareHi-Z
V
V
PPH
IL
IL
V
IL
V
IH
DQ7-DQ0
Data Input
20h
2Dh
during the bus operation; the memo ry will tri-state
the Input/Output Communication pins, FWH0FWH3.
Note that, during a Bus Write operation, the
Command Interface starts executing the
command as soon a s the data is f ully received; a
Bus Abort during the final TAR cycles is not
guaranteed to abort the command; the bus,
however, will be released immediately.
Standby. When F WH4 is High, V
, the me mory
IH
is put into Standby mode where FWH0-FWH3 are
put into a high-impedance state and the Supply
Current is reduced to the Standby level, I
CC1
.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when Interface Reset, RP
Rese t, IN IT
Low, V
, is Low, VIL. RP or IN IT must be held
, for t
IL
. The memory resets to Read
PLPH
, or CPU
mode upon return from Res et mo de and the Lock
Registers return to their default states regardless
of their state before Reset, see Table 14. If RP
INIT
goes Low, VIL, during a Program or Erase
or
operation, the operation is aborted and the
memory cells affected no longer contain valid
data; the memory can take up to t
PLRH
to abort a
Program or Erase operation.
Block Protection. Block Protection can be
forced using the signals Top Block Lock, TBL
Write Protect, WP
, regardless of the state of the
, and
Lock Registers.
Address/Address Multiplexed (A/A Mux) Bus
Operations
The Address/Address Multiplexed (A/A Mux)
Interface has a more traditional style interface.
The signals consist of a multiplexed address
signals (A0-A10), data signals, (DQ0-DQ7) and
three control signals (RC
signal, RP
, can be used to reset the memory.
, G, W). An additional
The Address/Address Multiplexed (A/A Mux)
Interface is included for use by Flash
Programming equipment for faster factory
programming. Only a subset of the features
available to the Firmware Hub (FWH) Interface are
available; these include all the Commands but
exclude the Security features and other registers.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface is selected all the blocks are
unprotected. It is not possible to protect any blocks
through this interface.
Bus Read. Bus Read operations are used to
output the contents of the Memory Array, the
Electronic Signature and the Status Register. A
valid Bus Read operation begins by latching the
Row Address and Column Address signals into
the memory using the Address Inputs, A0-A10,
and the Row/Column Address Select RC
Write Enable (W
be High, V
) and Interface Reset (RP) must
, and Output Enable, G, Low, VIL, in
IH
. Then
9/36
M50FW080
order to perform a Bus Read operation. The Data
Inputs/Outputs will output the value, see Figure
12, A/A Mux Interface Read AC Waveforms , and
Table 23, A/A Mux Interface Read AC
Characteristics, for details of when the output
becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by latching the Row Address and Column
Address signals into the memory using the
Address Inputs, A0-A10, and the Row/Column
Address Select RC
the Data Inputs/Outputs; Output Enable, G
Interface Reset, RP
Enable, W
, must be Low, VIL. The Data Inputs/
. The data should be set up on
, and
, must be High, VIH and Write
Outputs are latched on the rising edge of Write
Enable, W
. See Figure 13, A/A Mux Interface
Write AC Waveforms, and Table 24, A/A Mux
Interface Write AC Characteristics, for details of
the timing requirements.
Output Disa bl e . The data outputs are high-impedance when the Output Enable, G
, is at VIH.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when RP
held Low, V
for t
IL
is Low, VIL. RP must be
. If RP is goes Low, VIL,
PLPH
during a Program or Erase operation, the
operation is aborted and the memory cells affected
no longer contain valid data; the memory can take
up to t
to abort a Program or Erase operation.
PLRH
COMMAND INTERFACE
All Bus Write operations to the memory are
interpreted by the Command Interface.
Commands consist of one or more sequential Bus
Write operations.
After power-up or a Reset operation the memory
enters Read mode.
The commands are summarized in Table 10,
Commands. Refer to Tab le 1 0 in conjun ction with
the text descriptions below.
Table 9. Read Electronic Signature
CodeAddressData
Manufacturer Code00000h20h
Device Code00001h2Dh
Read Memory A rray Command. The Read Memory Array command returns the memory to its
Read mode where it behaves like a ROM or
EPROM. One Bus Write cycle is required to issue
the Read Memory Array command and return the
memory to Read mode. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus
Read operations will access the memory array.
While the Program/Erase Controller is executing a
Program or Erase operation the m emory will not
accept the Read Memory Array command until the
operation completes.
Read Statu s Register Co mm an d . The Read Status Register command is used to read the Status
Register. One Bus Write cycle is required to issue
the Read Status Register command. Once the
command is issued subsequent Bus Read operations read the Status Register until another command is issued. See the section on the Status
Register for details on the definitions of the Status
Register bits.
Read Electronic Si gnature Command . The Read
Electronic Signature command is used to read the
Manufacturer Code and the Device Code. One
Bus Write cycle is required to issue the Read
Electronic Signature command. Once the
command is issued subsequent Bus Read
operations read the Manufacturer Code or the
Device Code until another command is issued.
After the Read Electronic Signature Command is
issued the Manufacturer Code and Devi ce Code
can be read using Bus Read op erations us ing the
addresses in Table 9.
10/36
M50FW080
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. Two Bus Write
operations are required to issue the command; the
second Bus Write cycle latches the address and
data in the internal state m achine and starts the
Program/Erase Controller. Once the command is
issued subsequent Bus R ead operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
If the address falls in a pro tected block then the
Program operation will abort, the data in the
memory array will no t be changed and the S tatus
Register will output the error.
During the Program operation the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands will be ignored. Typical Program
times are given in Table 11.
Note that the Program command cannot change a
bit set at ‘0’ back to ‘1’ and attempting to do so will
not cause any modification on its value. One of the
Erase commands must be used to set all of the
bits in the block to ‘1’.
See Figure 14, Program Flowchart and Pseudo
Code, for a suggested flowchart on using the
Program command.
Quadruple Byte Program Command. The Quadruple Byte Program Comman d c an be only used
in A/A Mux mode to program four adjacent bytes
in the memory array at a time. The four bytes must
differ only for the addresses A0 and A10.
Programming should not be attempted when V
is not at V
if V
is below V
PP
. The operation can also be executed
PPH
, but result could be uncertain.
PPH
PP
Five Bus Write operations are required to issue the
command. The second, the third and the fourth
Bus Write cycle latches respectively the address
and data of the first, the second and the third byte
in the internal state machine. The fifth Bus Write
cycle latches the address and data of the fourth
byte in the internal state machine and starts the
Program/Erase Controller. Once the command is
issued subsequent Bus R ead operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
During the Quadruple Byte Program operation the
memory will only accept the Read Status register
command and the Program/Erase Suspe nd command. All other commands will be ignored. Typical
Quadruple Byte Program times are given in Table
11.
Note that the Quadruple Byte Program comm and
cannot change a bit set to ‘0’ back to ‘1’ and
attempting to do so will not cause any modification
on its value. One of the Erase commands must be
used to set all of the bits in the block to ‘1’.
See Figure 15, Quadruple Byte Program Flowchart and Pseudo Code, for a suggested flowchart
on using the Quadruple Byte Program command.
Chip Erase Command. The Chip Erase Command can be only used in A/A Mux mode to erase
the entire chip at a time. Erasing should not be attempted when V
can also be executed if V
is not at V
PP
PPH
is b elow V
PP
. The operation
, but re-
PPH
sult could be uncertain. Two Bus Write operations
are required to issue the com mand and start the
Program/Erase Controller. Once the command is
issued subsequent Bus R ead operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits. During the Chip Erase operation the
memory will only accept the Read Status Register
command. All other commands will be ignored.
Typical Chip Erase times are given in T able 11.
The Chip Erase command sets all of the bits in the
memory to ‘1’. See Figure 17, Chip Erase Flowchart and Pseudo Code, for a suggested flowchart
on using the Chip Erase command.
Block Erase Command. The Block Erase command can be used to erase a block. Two Bus Write
operations are required to issue the command; the
second Bus Write cycle latches the block address
in the internal stat e machine and starts th e Program/Erase Controller. Once the command is issued subsequent Bus Read ope rations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
If the block is protected then the Block Erase
operation will abort, the data in the block will not be
changed and the Status Register will output the
error.
During the Block Erase operation the me mory wi ll
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands will be ignored. Typical Block
Erase times are given in Table 11.
The Block Erase command sets all of the bits in
the block to ‘1’. All previous data in the block is
lost.
See Figure 18, Block Erase Flowchart and Pseudo
Code, for a suggested flowchart on using the
Erase command.
11/36
Loading...
+ 25 hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.