SGS Thomson Microelectronics M50FW040 Datasheet

3V Supply Firmware Hub Flash Memory

■ SUPPLY VOLTAGE

= 3V to 3.6V for Program, Erase and

–V

Read Operations

–V

= 12V for Fast Erase (optional)

■ TWO INTERFACES

– Firmware Hub (FWH) Interface for embedded

operation with PC Chipsets.

– Address/Address Multiplexed (A/A Mux) In-

terface for programm ing equipment compatibility.

■ FIRMWARE HUB (FWH) HARDWARE

INTERFACE MODE – 5 Signal Communication Interface supporting

Read and Write Operations

– Hardware Write Protect Pins for Block Pro-

tection – Register Based Read and Write Protection – 5 Additional Ge neral Pu rpose I nput s f or pla t-

form design flexibility – Synchronized with 33MHz PCI clock

■ PROGRAMMING TIME: 10µs typical

■ 8 UNIFORM 64 Kbyte MEMORY BLOCKS

■ PROGRAM/ERA SE CON T ROL LER

– Embedded Byte Program and Block Erase al-

gorithms – Status Register Bits

■ PROGRAM and ERASE SUSPEND

– Read other Blocks during Program/Erase

Suspend – Program other Blocks during Erase Suspend

■ FOR USE in PC BIOS APPLICATIONS

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Device Code: 2Ch

M50FW040

4 Mbit (512Kb x8, Unif orm Blo ck)

TSOP40 (N)

10 x 20mm

FWH0FWH3

TBL

AI03623

PLCC32 (K)

Figure 1. Logi c D iag ram ( FWH I nte rfa ce)

ID0-ID3

M50FW040

FGPI0-

FGPI4

FWH4

CLK

INIT

1/32March 2002

M50FW040

Figure 2. Logic Diagram (A/A Mux Interface)

A0-A10

M50FW040

DQ0-DQ7

AI03412

DESCRIPTION

The M50FW040 is a 4 M bit (512Kb x 8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast erasing in production lines an optional 12V power supply can be us ed to reduce the erasing time.

The memory is divided into blocks that can be erased independently so it is pos sible to pres erve valid data while old data is erased. Blocks can be protected individually to prevent accidental Program or Erase commands from modifying the memory. Program and Erase com m ands are wri tten to the Command Interface of t he memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase op eration can be de tected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

Two different bus interfaces are supported by t he memory. The primary interface, the Firmware Hub

(or FWH) Interface, uses Intel’s proprietary FWH protocol. This has been designed to remove the need for the ISA bus in current PC Chipsets; the

Figure 3. PLCC Connections

A/A Mux A/A Mux

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

FGPI1 FGPI0

TBL

ID3 ID2 ID1 ID0

FWH0

RPA8VPPV

FGPI2

FGPI3

M50FW040

FWH1

FWH2

DQ1

DQ2

VPPV

RFU

FWH3

DQ3

DQ4

CLK

RFU

DQ5

A10

FGPI4

RFU

DQ6

IC (VIL) NC NC V

INIT FWH4 RFU RFU

IC (VIH) NC NC V

G W RB DQ7

A/A MuxA/A Mux

AI03616

Note: Pins 27 and 28 are not inte rnally connec ted.

2/32

M50FW040

M50FW040 acts as the PC BIOS on the Low P in Count bus for these PC Chipsets.

The secondary interface, the Address/Address Multiplexed (or A/A Mux) Int erface, is design ed t o be compatible with current Flash Programmers for production line programming prior to fitting to a PC Motherboard.

The memory is offered in TSOP40 (10 x 20mm) and PLCC32 packages and it is supplied with all

the bits erased (set to ’1’).

SIGNAL DESCRIPTIONS

There are two different bus interfaces available on this part. The active interface is selected before power-up or during Reset using the Interface Configur a tion Pi n , IC .

The signals for each interface are discussed in the Firmware Hub (FWH) Signal Descriptions section and the Address/Address M ultiplexed (A/A Mux) Signal Descriptions section below. The supply signals are discussed in the Supply S ignal Descriptions section below.

Firmware Hub (FWH) Signal Descriptions

For the Firmware Hub (FWH) Interface see Figure 1, Logic Diagram, and Table 1, Signal Names.

Table 1. Signal Names (FWH Interface)

FWH0-FWH3 Input/Output Communications FWH4 Input Communication Frame ID0-ID3 Identification Inputs FGPI0-FGPI4 General Purpose Inputs IC Interface Configuration RP INIT CLK Clock TBL WP

RFU

NC Not Connected Intern ally

Interface Reset CPU Reset

Top Block Lock Write Protect Reserved for Future Use. Leave

disconnected Supply Voltage Optional Supply Voltage for Fast

Erase Operations Ground

Figure 4. TSOP Connections

IC (VIH)

NC NC NC NC

A10

NC RC

A/A Mux

RP NC NC

A9 A8 A7 A6 A5 A4 A3

IC (VIL)

NC NC INIT NC RFU NC

FGPI4

CLK

RP NC

NC FGPI3 FGPI2 FWH0 FGPI1 ID0 FGPI0

TBL

M50FW040

20 21

31 30

FWH4

RFU RFU RFU RFU V

FWH3 FWH2 FWH1

ID1 ID2 ID3

W G RB DQ7 DQ6 DQ5 DQ4 V

DQ3 DQ2 DQ1 DQ0 A0 A1 A2

A/A Mux

AI03617

3/32

M50FW040

Table 2. Signal Names (A/A Mux Interface)

IC Interface Configuration A0-A10 Address Inputs DQ0-DQ7 Data Inputs/Outputs G W RC RB RP V

NC Not Connected Internally

Output Enable Write Enable Row/Column Address Select Ready/Busy Output Interface Reset Supply Voltage Optional Supply Voltage for Fast

Erase Operations Ground

Input/Output Communications (FWH0-FWH3). All Input and Output Communication with the memory take place on th ese pins. Addresses and Data for Bus Read and Bus Wri te operations are encod ed on these pins.

Input Communication Frame (FWH4). The Input Communication Frame (FWH4) signals the start of a bus operation. When Input Communication Frame is Low, V

, on the rising edge of the

Clock a new bus operation is initiated. If Input Communication Frame is Lo w, V

, during a bus

operation then t he operation is aborted. When Input Communication Frame is High, V

, the cur-

rent bus operation is proceeding or the bus is idle. Identification Inputs (ID0-ID3). The Identifica-

tion Inputs select the address that the memory responds to. U p to 16 m emories c an be addres sed

on a bus. For an address bit to be ‘0’ the pin can be left floating or d riven Low, V down resistor is in cluded with a value of R

; an internal pul l-

. For an address bit to be ‘1’ the pin must be driven High, V

; there will be a leakage current of I

LI2

through each pin when pulled to VIH; see Table 19. By convention the boot memory must have ad-

dress ‘0000’ and all additional memories take sequential addresses starting from ‘0001’.

General Purpose Inputs (FGPI0-FGPI4). The General Purpose I nputs can be u sed a s digit al inputs for the CPU to read. The General Purpose Inputs Register holds the values on these pins. The p ins must have stable dat a from b efore the start of t he cycle that reads the General Purpose Input Register until after the cycle is complete. These pins must not be left to float, they should be driven Low,

or High, VIH.

IL,

Interface Configuration (IC). The Interface Configuration input selects whether the Firmware Hub (FWH) or the Address/Address Multiplexed (A/A Mux) Interface is used. The chosen interface must be selected before power-up or during a Reset and, thereafter, cannot be change d. The state of the Interface Configuration, IC, should not be changed during operation.

To select the Firmware Hub (FWH) Interface the Interface Configuration pin should be left to float or driven Low, V

; to select the Address/Address

Multiplexed (A/A Mux) Interface t he pin should be driven High, V included with a value of R current of I

. An internal pull-down resistor is

through each pin when pulled to VIH;

LI2

; there will be a leakage

see Table 19.

Interface Reset (RP

). The Interface Reset (RP)

input is used to reset the memory. When Interface Reset (RP

) is set Low, VIL, the memor y i s i n R ese t mode: the outputs are put to high impedance and the current consumption is minimized. When RP set High, V

, the memory is in no rmal operat ion.

After exiting Reset mode, the memory enters Read mode.

CPU Reset (INIT

). The CPU Reset, INIT, pin is

used to Reset the memory when the CPU is reset . It behaves identically to Interface Reset, RP

, and the internal Reset lin e is the logical OR (elec tric al AND) of RP

and INIT.

Clock (CLK). The Clock, CLK, input is used to clock the signals in and out of the Input/Output Communication Pins, FWH0-FWH3. The Clock conforms to the PCI specification.

Top Block Lock (TBL

). The Top Block Lock in-

put is used to prevent the Top Block (Block 7) from being changed. When Top Block Lock, TBL Low, V

, Program and Erase operations in the

, is set

Top Block have n o effect, regardless of the state of the Lock Register. When T op B lock Lock, TBL is set Hig h, V

, the protection of the Block is de-

termined by the Lock Register. The state of Top Block Lock, TBL

, does not affect the protection of

the Main Blocks (Blocks 0 to 6). Top Block Lock, TBL

, must be set prior to a Program or Erase operation is initiated and must not be changed until the o peration completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing

during Program or Erase Suspend.

TBL

Write Protect (WP

). The Write Protect input is

used to prevent the Main Blocks (Blocks 0 to 6) from being changed. W hen Write P rotect, WP set Low, V

, Program and Erase operations in the

, is

Main Blocks have no ef fect, regardl ess of the state of the Lock Register. When Write Protect, WP set High, V

, the protection of the Block deter-

, is

mined by the Lock Register. The state of Write

4/32

M50FW040

Table 3. Absolute Maximum Ratings

Symbol Parameter Value Unit

BIAS

STG

(2)

Note: 1. Except f or the ratin g "Operating Temperatur e Range", stresses abo ve those lis ted in the Tab l e " Absolute M aximum Rati ngs" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operatin g sections of this s pecification is not i m plied. Ex posure to A bsolute Maximum Rating cond itions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ity docum en ts .

2. Minimum Volta ge may undershoot to –2V and for less than 20ns during transitions. Maximum Volta ge m ay overshoot to V

and for less th an 20ns during t ransitions.

Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C Ambient Operating Temperature (Temperature Range Option 5) –20 to 85 °C Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage Supply Voltage –0.6 to 4 V Program Voltage –0.6 to 13 V

Protect, WP, does no t affect the protection of t he Top Block (Block 7).

Write Protect, WP

, must be set prior to a Program or Erase operation is initiated and must not be changed until the operation completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing WP during Program or Erase Suspend.

Reserved for Future Use (RFU). These pins do not have assigned func tions i n this revision of the part. They must be left disconnected.

Address/Address Multiplexed (A/A Mux) Signal Descriptions

For the Address/Address Multiplexed (A/A Mux) Interface see Figure 2, Logi c Diagram, and Table 2, Signal Names.

Address Inputs (A0-A10). The Address Inputs are used to set the Row Address bits (A0-A10) and the Column Address bits (A11-A18). They are latched during any bus operation by the Row/ Column Address Select input, RC

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs hold the data that is written to or read from the memory. They output the data s tored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent t o the Command Interface of the internal state machine. The Data I nputs/Outputs, DQ0-DQ7, are latched during a Bus Write operation.

Output Enable (G

). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, controls

the Bus Write operation of the memory’s Command Interf a c e .

Row/Column Address Select (RC

Column Address Select input selects whether the

(1)

). The Row/

–0.6 to V

+ 0.6

+2V

Address Inputs should be latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A18). The Row Address bits are latched on the falling edge of RC

whereas the Column Ad-

dress bits are latched on the rising edge.

Ready/Busy Output (RB

). The Ready/Busy pin

gives the status of the memory’s Program/Erase Controller. When Ready/Busy is Low, V

, the memory is busy with a Program or Erase operation and it will not accept any additional Program or Erase command exc ept the Program/Erase S uspend command. When Ready/Busy i s High, V

the memory is ready for any Read, Program or Erase operation.

Supply Signal Descriptions

The Supply Signals are the same for both interfaces.

Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the V

Supply Voltage is less than the L ockout Voltage, V

. This prevents Bus Write operations from ac-

LKO

cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. After V

becomes valid the Command Int erface is reset to Read mode.

A 0.1µF capacitor should be connected between the V

Supply Voltage pins and the VSS Ground

pin to decouple the current surges from the power supply. Both V

Supply Voltage pins must be

connected to the power supply. The PCB track widths must be suf ficient to carry the currents required during program and erase operations.

Optional Supply Voltage. The VPP Optional

Supply Voltage pin is used to select the Fast Erase

5/32

M50FW040

Table 4. Block Addresses

Size

(Kbytes)

64 70000h-7FFFFh 7 Top Block 64 60000h-6FFFFh 6 Main Block 64 50000h-5FFFFh 5 Main Block 64 40000h-4FFFFh 4 Main Block 64 30000h-3FFFFh 3 Main Block 64 20000h-2FFFFh 2 Main Block 64 10000h-1FFFFh 1 Main Block 64 00000h-0FFFFh 0 Main Block

Address Range

Block

Number

Block Type

option of the memory and to protect the memory. When V

< V

Program and Erase operations

PPLK

cannot be performed and an error is reported in the Status Register if an attempt to change the memory contents is made. When V

= VCC Pro-

gram and Erase operations take place as normal. When V

= V

used. Any oth er voltage i nput to V

Fast Erase operations are

PPH

will result in

undefined behavior and should not be used. V

should not be set to V

for more than 80

PPH

hours during the life of the memory.

Ground. VSS is the reference for al l the vol t-

age measurements.

BUS OPERATIONS

The two interfaces have similar bus operations but the signals and tim ings are com pletely different. The Firmware Hub (FWH) Interface is the usual interface and all of the functionality of the part is available through this interfac e. Only a subset of functions are available through the Address/Address Multiplexed (A/A Mux) Interface.

Follow the section Firmware Hub (FWH) Bus Operations below and the section Address/Address Multiplexed (A/A Mux) Interface Bus Operations below for a description of the bus operations on each interface.

Firmware Hub (FWH) Bus Operations

The Firmware Hub (FWH) Interface consists of four data signals (FWH0-FWH3), one cont rol line (FWH4) and a clock (CLK). In addition protection against accidental or malicious data corruption can be achieved using two further signals (TBL and WP). Finally two reset signals (RP and INIT ) are available to put the memory into a known state.

The data signals, control signal and clock are designed to be compatible with PCI electrical specifi-

cations. The interface operates with clock speeds up to 33MHz.

The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Standby, Reset and Block Protection.

Bus Read. Bus Read operations read from the memory cells, specific registers in the Command Interface or Firmware Hub Reg isters. A valid B us Read operation starts when Input Communication Frame, FWH4, is Low, V

, as Clock rises and the

correct Start cycle is on FWH0-FWH3. On the following clock cycles the Host will send the Memory ID Select, Address and other control bits on FWH0-FWH3. The memory responds by outputting Sync data until the wait-states have elapsed followed by Data0-Data3 and Data4-Data7.

Refer to Table 5, FWH Bus Read Field Definitions, and Figure 5, FWH Bus Read Waveforms, for a description of the Field definitions for each clock cycle of the transfer. See Table 21, FWH Interface AC Signal Timing Characteristics and Figure 10, FWH Interface AC Signal Timing Waveforms, for details on the timings of the signals.

Bus Write. Bus Write operations write to the Command Interface or Firmware Hub Registers. A valid Bus Write operation starts when Input Communication Frame, FWH4, is Low, V

, as Clock

rises and the correct Start cycle is on FWH0FWH3. On the following Clock cycles the Host will send the Memory ID Select, Address, other control bits, Data0-Data3 and Data4-Data7 on FWH0FWH3. The memory outputs Sync data until the wait-states have elapsed.

Refer to Table 6, FWH Bus Write Field Definitions, and Figure 6, FWH Bus Wri te Waveforms, for a description of the Field definitions for each clock cycle of the transfer. See Table 21, FWH Interface AC Signal Timing Characteristics and Figure 10, FWH Interface AC Signal Timing Waveforms, for details on the timings of the signals.

Bus Abort. The Bus Abort operation can be used to immediately abort the current bus operation. A Bus Abort occurs when FWH4 is driven Low, V

during the bus operation; the memo ry will tri-state the Input/Output Communication pins, FWH0FWH3.

Note that, during a Bus Write operation, the Command Interface starts executing the c ommand as soon as the data is fully received; a Bus Abort during the final TAR cycles is not guaranteed to abort the com man d; the bus , how e ver, w ill be re leas ed immediately.

Standby. When F WH4 is High, V

, the me mory

is put into Standby mode where FWH0-FWH3 are

6/32

Tabl e 5. FWH Bus Read Field Definitions

Clock Cycle

Number

Clock Cycle

Count

Field

FWH0-

FWH3

Memory

I/O

M50FW040

Description

1 1 START 1101b I

On the rising edge of CLK with FWH4 Low, the contents of FWH0-FWH3 indicate the start of a FWH Read cycle.

Indicates which FWH Flash Memory is selected. The value

2 1 IDSEL XXXX I

on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed.

3-9 7 ADDR XXXX I

A 28-bit address phase is transferred starting with the most significant nibble first.

10 1 MSIZE 0000b I Always 0000b (only single byte transfers are supported).

11 1 TAR 1111b I

12 1 TAR

1111b

(float)

The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle.

The FWH Flash Memory takes control of FWH0-FWH3

during this cycle. The FWH Flash Memory drives FWH0-FWH3 to 0101b

13-14 2 WS YNC 0101b O

(short wait-sync) for two clock cycles, indicating that the data is not yet available. Two wait-states are always included.

The FWH Flash Memory drives FWH0-FWH3 to 0000b,

15 1 RSYNC 0000b O

indicating that data will be available during the next clock cycle.

16-17 2 DATA XXXX O

18 1 TAR 1111b O

19 1 TAR

1111b

(float)

N/A

Data transfer is two CLK cycles, starting with the least significant nibble.

The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate a turnaround cycle.

The FWH Flash Memory floats its outputs, the host takes control of FWH0-FWH3.

Figure 5. FWH Bus Read Waveforms

CLK

FWH4

FWH0-FWH3

Number of clock cycles

START IDSEL ADDR MSIZE TAR SYNC DATA TAR

11712322

AI03437

7/32

M50FW040

Table 6. FWH Bus Write Field Definitions

Clock Cycle

Number

Clock Cycle

Count

Field

FWH0-

FWH3

Memory

I/O

Description

1 1 START 1110b I

2 1 IDSEL XXXX I

3-9 7 ADDR XXXX I

10 1 MSIZE 0000b I Always 0000b (single byte transfer).

11-12 2 DATA XXXX I

13 1 TAR 1111b I

14 1 TAR

15 1 S YNC 0000b O

16 1 TAR 1111b O

17 1 TAR

1111b

(float)

1111b

(float)

N/A

On the rising edge of CLK with FWH4 Low, the contents of FWH0-FWH3 indicate the start of a FWH Write Cycle.

Indicates which FWH Flash Memory is selected. The value on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed.

A 28-bit address phase is transferred starting with the most significant nibble first.

Data transfer is two cycles, starting with the least significant nibble.

The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle.

The FWH Flash Memory takes control of FWH0-FWH3

during this cycle. The FWH Flash Memory drives FWH0-FWH3 to 0000b,

indicating it has received data or a command. The FWH Flash Memory drives FWH0-FWH3 to 1111b,

indicating a turnaround cycle. The FWH Flash Memory floats its outputs and the host takes

control of FWH0-FWH3.

Figure 6. FWH Bus Write Waveforms

CLK

FWH4

FWH0-FWH3

Number of clock cycles

START IDSEL ADDR MSIZE DATA TAR SYNC TAR

11712212

put into a high-impedance state and the Supply Current is reduced to the Standby level, I

CC1

Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when Interface Reset, RP Rese t, IN IT Low, V

, is Low, VIL. RP or IN IT must be held

, for t

. The memory resets to Read

PLPH

, or CPU

mode upon return from Res et mo de and the Lock Registers return to their default states regardless of their state before Reset, see Table 14. If RP

AI03441

goes Low, VIL, during a Program or Erase op-

INIT eration, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to t

to abort a Program

PLRH

or Erase operation. Block Protection. Block Protection can be

forced using the signals Top Block Lock, TBL Write Protect, WP

, regardless of the state of the

, and Lock Registers.

8/32

Table 7. A/A Mux Bus Operations

Operation G W RP

Bus Read Bus Write Output Disable Reset

or V

VIL or V

Table 8. Manufacturer and Device Codes

Operation G

Manufacturer Code Device Code

W RP A18-A1 A0 DQ7-DQ0

M50FW040

Don’t Care Data Output

VCC or V

Don’t Care Hi-Z Don’t Care Hi-Z

V V

PPH

DQ7-DQ0

Data Input

20h

2Ch

Address/Address Multiplexed (A/A Mux) Bus Operations

The Address/Address Multiplexed (A/A Mux) Interface has a more traditional style interface. The signals consist of a multiplexed a ddress s ignals (A0A10), data signals, (DQ0-DQ7) an d three control signals (RC

, G, W). An additional signal, RP, can

be used to reset the memory. The Address/Address Multiplexed (A/A Mux) Inter-

face is included for use by Flash Programming equipment for faster factory programming. Only a subset of the features available to the Firmware Hub (FWH) Interface are available; these in clude all the Commands but e xclude the Securi ty features and other registers.

The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Output Disable and Reset.

When the Address/Address Multiplexed (A/A Mux) Interface is selected all the blocks are unprotected. It is not possible to protect any blocks through this interface.

Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature and the Status Register. A valid Bus Read operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC Enable (W

) and Interface Reset (RP) must be

. Then Write

High, V

, and Output Enable, G, Low, VIL, in order

to perform a Bus Read operation. The Data Inputs/ Outputs will output the value, see Figure 12, A/A Mux Interface Read AC Waveforms, and Table 23, A/A Mux Interface Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC Data Inputs/Outputs; Output Enable, G face Reset, RP able, W

, must be Low, VIL. The Data Inputs/

. The data should be set up on the

, and Inter-

, must be High, VIH and Write En-

Outputs are latched on the rising edge of Write Enable, W

. See Figure 13, A/A Mux Interface Write AC Waveforms, and Table 24, A/A Mux Interface Write AC Characteristics, for details of the timing requirements.

Output Disa bl e . The data outputs are high-impedance when the Output Enable, G

, is at VIH.

Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when RP held Low, V

for t

PLPH

is Low, VIL. RP must be

. If RP is goes Low, VIL, during a Program or Erase operation, the operation is aborted and the memory cel ls affected no l onger contain valid data; the memory can take up to t

to abort a Program or Erase operation.

PL-

9/32

M50FW040

COMMAND INTERFACE

All Bus Write operations t o the me mory are in terpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations.

After power-up or a Reset operation the memory enters Read mode.

The commands are summarized in Table 10, Commands. Refer to Tab le 1 0 in c onjun ction with the text descriptions below.

Read Memory A rray Command. The Read Memory Array command returns the memory to its Read mode where it behaves like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read operations will access the memory array.

While the Program/Erase Controller is executing a Program or Erase operation the m emory will not accept the Read Memory Array command until the operation completes.

Read Statu s Register Co mm an d . The Read Status Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read operations read the Status Register until another command is issued. See the section on the Status Register for details on the definitions of the Status Register bits.

Read Electronic Si gnature Command . The Read Electronic Signature command is used to read the Manufacturer Code and the Device Code. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the comm and is issued subsequent Bus R ead operations read the Manufacturer Code or the Device Code until another command is issued.

After the Read Electronic Signature Command is issued the Manufacturer Code and Devi ce Code can be read using Bus Read op erations us ing the addresses in Table 9.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the address and data in the internal stat e machine and starts th e Program/Erase Controller. Once the command is issued subsequent Bus Read ope rations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits.

If the address falls in a pro tected block then the Program operation will abort, the data in the mem-

10/32

Table 9. Read Electronic Signature

Code Address Data

Manufacturer Code 00000h 20h Device Code 00001h 2Ch

ory array will not be changed and the Status Register will output the error.

During the Program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Program times are given in Table 11.

Note that the Program command cannot change a

bit set at ‘0’ back to ‘1’ and attempting to do so will not cause any modification on its value. The Erase command must be used to set all of the bits in the block to ‘1’.

See Figure 14, Program Flowchart and Pseudo Code, for a suggested flowchart on using the Program command.

Erase Command. The Erase command can be used to erase a block. Two Bu s Write operations are required to issue the command; the second Bus Write cycle latches the block address in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits.

If the block is protected then the Erase o peration will abort, the data in the block will not be changed and the Status Register will output the error.

During the Erase operation the memory will only accept the Read Status Register command and the Program/Erase Su spend command. All ot her commands will be ignored. Typical Erase times are given in Table 11.

The Erase command sets all of the bits in the block to ‘1’. All previous data in the block is lost.

See Figure 16, Erase Flowchart and Pseudo Code, for a suggested flowchart on using the Erase command.

Clear Status Register Command. The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One Bus Write is required to issue the Clear Status Register command. Once the command is issued the memory returns to its previous mode, subs equent Bus Read operations continue to output the same data.

The bits in the Status Register are stic ky and do not automatically return to ‘0’ when a new Program or Erase command is issued. If an error occurs then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a ne w Program or Erase command.

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