SGS Thomson Microelectronics M50FW002 Datasheet

3V Supply Firmware Hub Flash Memory

FEATURES SUMMARY

■ SUPPLY VOLTAGE

= 3 V to 3.6 V for Program, Erase and

–V

Read Operations

–V

= 12 V for Fast Program and Fast Erase

(optional)

■ TWO INTE R FA CES

– Firmware Hub (FWH) Interface for embedded

operation with PC Chipsets

– Address/Address Multiplexed (A/A Mux)

Interface for programming equipment compatibility

■ FIRMWARE HUB (FWH) HARDWARE

INTERFACE MODE – 5 Signal Communication Interface supporting

Read and Write Operations

– Hardware Write Protect Pins for Block

Protection – Register Based Read and Write Protection – 5 Additional General Purpose Inputs for

platform design flexibility – Synchronized with 33MHz PCI clock – Multi-byte Read Operation (1-byte, 16-byte,

32-byte)

■ PROGRAMMING TIME

– 10 µs typical – Quadruple Byte Programming Option

■ 7 MEMORY BLOCKS

– 1 Boot Block (Top Location) – 4 Main Blocks and 2 Parameter Blocks

■ PROGRAM/ERA SE CON T ROL LER

– Embedded Byte Program, Block Erase and

Chip Erase algorithms – Status Register Bits

■ PROGRAM and ERASE SUSPEND

■ FOR USE in PC BIOS APPLICATIONS

M50FW002

2 Mbit (256Kb x8, Boot Block)

PRELIMINARY DATA

Figure 1. Packages

PLCC32 (K)

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Device Code: 29h

May 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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M50FW002

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Firmware Hub (FWH) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Address/Address M ultiplexe d (A/A Mux) Sign al Descrip tions . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Supply Signal Description s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Firmware Hub (FWH) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

FWH Bus Read Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

FWH Bus Write Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

Address/Address M ultiplexe d (A/A Mux) B us Operati ons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

A/A Mux Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Manufacturer and Device Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 17

Lock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Firmware Hub (FWH) General Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Firmware Hub Register Configuration Map

(1)

Lock Register Bit Definitions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

General Purpose Input Register Definition

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

AC Measurement Conditions (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

AC Measurement Conditions (A/A Mux Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Device Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Clock Characteristics (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

AC Signal Timing Characteristics (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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M50FW002

Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Read AC Characteristics (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Write AC Characteristics (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6

PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data . . . . . . . . . . . . . . . . . 36

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8

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M50FW002

SUMMARY DESCRIPTION

The M50FW 002 is a 2 Mbit (25 6Kb x8) n on-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing in production lines an optional 12V power supply can be used to reduce the programming and the erasing times.

The memory is divided into blocks that can be erased independently so it is pos sible to pres erve valid data while old data is erased. Blocks can be protected individually to prevent accidental Program or Erase commands from modifying the memory. Program and Erase com m ands are wri tten to the Command Interface of t he memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase op eration can be de tected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

The device features an asymmetrical blocked architecture. The device has an array of 7 blocks:

■ 1 Boot Block of 16 KByte

■ 2 Parameter Blocks of 8 KByte each

■ 1 Main Block of 32 KByte

■ 3 Main Blocks of 64 KByte each

Two different bus interfaces are supported by t he memory. The primary interface, the Firmware Hub

(or FWH) Interface, uses Intel’s proprietary FWH protocol. This has been designed to remove the need for the ISA bus in current PC Chipsets; the M50FW002 acts as the PC BIOS on the Low Pin Count bus for these PC Chipsets.

The secondary interface, the Address/Address Multiplexed (or A/A Mux) Int erface, is design ed t o be compatible with current Flash Programmers for production line programming prior to fitting to a PC Motherboard.

The memory is delivered with all the bits erased (set to 1).

Figure 2. PLCC Connections

A/A Mux A/A Mux

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

FGPI1 FGPI0

TBL

ID3 ID2 ID1 ID0

FWH0

RPA8VPPV

FGPI2

FGPI3

M50FW002

FWH1

FWH2

DQ1

DQ2

VPPV

RFU

FWH3

DQ3

DQ4

CLK

RFU

DQ5

A10

FGPI4

RFU

DQ6

IC (VIL) NC NC V

INIT FWH4 RFU RFU

IC (VIH) NC NC V

G W RB DQ7

A/A MuxA/A Mux

AI05749

Note: Pi ns 27 and 28 are not interna l l y co nnected.

4/39

M50FW002

Figure 3. Logi c Diagram (FWH I nt erfa ce)

ID0-ID3

FGPI0-

FGPI4

FWH4

CLK

INIT

M50FW002

FWH0FWH3

TBL

AI05747

Figure 4. Logic Diagram (A/A Mux Interface)

A0-A10

M50FW002

DQ0-DQ7

AI05748

Table 1. Signal Names (FWH Interface)

FWH0-FWH3 Input/Output Communications FWH4 Input Communication Frame ID0-ID3 Identification Inputs FGPI0-FGPI4 General Purpose Inputs IC Interface Configuration RP INIT CLK Clock TBL WP

RFU

Interface Reset CPU Reset

Top Block Lock Write Protect Reserved for Future Use. Leave

disconnected Supply Voltage Optional Supply Voltage for Fast

Erase Operations

Table 2. Signal Names (A/A Mux Interface)

IC Interface Configuration A0-A10 Address Inputs DQ0-DQ7 Data Inputs/Outputs G W RC RB RP V

NC Not Connected Internally

Output Enable Write Enable Row/Column Address Select Ready/Busy Output Interface Reset Supply Voltage Optional Supply Voltage for Fast

Program and Fast Erase Operations Ground

NC Not Connected Internally

Ground

5/39

M50FW002

SIGNAL DESCRIPTIONS

There are two different bus interfaces available on this part. The active interface is selected before power-up or during Reset using the Interface Configur a tion Pin, IC.

The signals for each interface are discussed in the Firmware Hub (FWH) Signal Descriptions section and the Address/Address M ultiplexed (A/A Mux) Signal Descriptions section below. The supply signals are discussed in the Supply S ignal Descriptions section below.

Firmware Hub (FWH) Signal Descriptions

For the Firmware Hub (FWH) Interface see Figure 4, Logic Diagram, and Table 1, Signal Names.

Input/Output Communications (FWH0-FWH3). All Input and Output Communication with the memory take place on these pi ns. Addresses and Data for Bus Read and Bus W rite operations are en coded on these pins.

Input Communication Frame (FWH4). The Input Communication Frame (FWH4) signals the start of a bus op eration. When Input Communication Frame is Low, V Clock a new bus operation is initiated. If Input Communication Frame is L ow, V operation then the operation is aborted. When Input Communication Frame is High, V rent bus operation is proceeding or the bus is idle.

Identification Inputs (ID0-ID3). The Identification Inputs select the address that the memory responds to. Up to 16 memories can be

addressed on a bus. For an address bit to be ‘0’ the pin can be left floating or driven Low, V internal pull-down resistor is included with a value

. For an address bit to be ‘1’ the pin must be

of R

driven High, V I

through each pin when pulled to VIH; see Table

LI2

; there will be a leakage current of

19. By convention the boot memory must have

address ‘0000’ and all additional memories take sequential addresses starting from ‘0001’.

General Purpose Inputs (FGPI0-FGPI4) . The General Purpose Inputs can be used as digital inputs for the CPU to read. Th e General Purpose Input Register holds the values on t hese pins. The pins must have stable data f rom before t he s tart of t he cycle that reads the General Purpose Input Register until after the cycle is complete. These pins must not be left to float, they should be driven Low, V

or High, VIH.

IL,

Interface Configuration (IC). The Interface Configuration input selects whether the Firmware Hub (FWH) or the Address/Address Multiplexed (A/A Mux) Interface is used. The chosen interface must be selected before power-up or during a Reset and, thereafter, cannot be changed . The state of

, on the rising edge of the

, during a bus

, the cur-

; an

the Interface Configuration, IC, should not be changed during operation.

To select the Firmware Hub (FWH) Interface the Interface Configuration pin should be left to float or driven Low, V

; to select the Address/Address

Multiplexed (A/A Mux) Interface t he pin should be driven High, V included with a value of R current of I

. An internal pull-down resistor is

through each pin when pulled to VIH;

LI2

; there will be a leakage

see Table 19.

Interface Reset (RP

). The Interface Reset (RP)

input is used to reset the memory. When Interface Reset (RP

) is set Low, VIL, the memor y i s i n R ese t mode: the outputs are put to high impedance and the current consumption is minimized. When RP set High, V

, the memory is in no rmal operat ion.

After exiting Reset mode, the memory enters Read mode.

CPU Reset (INIT

). The CPU Reset, INIT, pin is

used to Reset the memory when the CPU is reset . It behaves identically to Interface Reset, RP

, and the internal Reset lin e is the logical OR (elec tric al AND) of RP

and INIT.

Clock (CLK). The Clock, CLK, input is used to clock the signals in and out of the Input/Output Communication Pins, FWH0-FWH3. The Clock conforms to the PCI specification.

Top Block Lock (TB L

). The Top Block Lock

input is used to pre vent the Top Block (Block 6) from being chan ged. When Top Block Loc k, TBL is set Low, V

, Program and Erase operations in

the Top Block have no effect, regardless of the state of the Lock Register. When To p Bloc k Loc k,

, is set High , VIH, the protection of the Block is

TBL determined by the Lock Register. The state of Top Block Lock, TBL

, does not affect the protection of

the other blocks (Blocks 0 to 5). Top Block Lock, TBL

, must be set prior to a Program or Erase operation is initiated and must not be changed until the o peration completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing TBL

during Program or Erase Suspend.

Write Protect (WP

). The Write Protect input is

used to prevent the blocks 0 to 5 from being changed. When Write Protect, WP

, is s et Lo w, VIL, Program and Erase operations in these blocks have no effect, regardless of the state of the Lock Register. When Write Protect, WP V

, the protection of the Block is determined by

, is set High,

the Lock Register. T he st ate of Write Prot ect, WP does not affect the protection of the Top Block (Block 6).

Write Protect, WP

, must be set prior to a Program or Erase operation is initiated and must not be changed until the operation completes or unpre-

6/39

M50FW002

dictable results may occur. Care should be taken to avoid unpredictable behavior by changing WP during Program or Erase Suspend.

Reserved for Future Use (RFU). These pins do not have assigned func tions i n this revision of the part. They must be left disconnected.

Address/Address Multiplexed (A/A Mux) Signal Descriptions

For the Address/Address Multiplexed (A/A Mux) Interface see Figure 4, and Table 2.

Address Inputs (A0-A10). The Address Inputs are used to set the Row Address bits (A0-A10) and the Column Address bits (A11-A17). They are latched during any bus operation by the Row/ Column Address Select input, RC

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs hold the data that is written to or read from the memory. They output the data s tored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent t o the Command Interface of the internal state machine. The Data I nputs/Outputs, DQ0-DQ7, are latched during a Bus Write operation.

Output Enable (G

). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, controls

the Bus Write operation of the memory’s Command Interf a c e .

Row/Column Address Select (RC

). The Row/

Column Address Select input selects whether the Address Inputs should be latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A17). The Row Address bits are latched on the falling edge of RC

whereas the Column

Address bits are latched on the rising edge.

Ready/Busy Output (RB

). The Ready/Busy pin

gives the status of the memory’s Program/Erase Controller. When Ready/Busy is Low, V

, the memory is busy with a Program or Erase operation and it will not accept any additional Program or Erase command except the Program/Erase Suspend command. When Ready/Busy is High,

, the memory is ready for any Rea d, Program

or Erase operation.

Supply Signal Descriptions

The Supply Signals are the same for both interfaces.

Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the V

Supply Voltage is less than the L ockout Voltage, V

. This prevents Bus Write operations from

LKO

accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. After V

becomes valid the Comma nd Interface

is reset to Read mode. A 0.1µF capacitor should be connected between

the V

Supply Voltage pins and the VSS Ground

pin to decouple the current surges from the power supply. Both V

Supply Voltage pins must be

connected to the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations.

Optional Supply Voltage. The VPP Optional

Supply Voltage pin is used to select the Fast Program (see the Quadruple Byte Program Command description) and Fast Erase options of the memory and to protect the memory. When V < V

Program and Erase operations cannot be

PPLK

performed and an error is reported in the Sta tus Register if an attempt to change the memory contents is made. When V Erase operations take place as normal. When V = V

Fast Program (if A/A Mux interface is

PPH

= VCC Program and

selected) and Fast Erase operations are used. Any other voltage input to V

will result in

undefined behavior and should not be used.

should not be set to V

for more than 80

PPH

hours during the life of the memory.

Ground. VSS is the reference for al l the vol t-

age measurements.

Table 3. Block Addresses

Size

(Kbytes)

16 3C000h-3FFFFh 6

32 30000h-37FFFh 3 Main Block 64 20000h-2FFFFh 2 Main Block 64 10000h-1FFFFh 1 Main Block 64 00000h-0FFFFh 0 Main Block

Address Range

8 3A000h-3BFFFh 5

8 38000h-39FFFh 4

Block

Number

Block Type

Boot Block

(Top)

Parameter

Block

Parameter

Block

7/39

M50FW002

BUS OPERATIONS

The two interfaces have similar bus operations but the signals and tim ings are comple tely different. The Firmware Hub (FWH) Interface is the usual interface and all of the functionality of the part is available through this interfac e. Only a subset of functions are available through the Address/ Address Multiplexed (A/A Mux) Interface.

Follow the section Firmware Hub (FWH) Bus Operations below and the section Address/ Address Multiplexed (A/A Mux) Interface Bus Operations below for a description of the bus operations on each interface.

Firmware Hub (FWH) Bus Operations

The Firmware Hub (FWH) Interface consists of four data signals (FWH0-FWH3), one cont rol line (FWH4) and a clock (CLK). In addition protection against accidental or malicious data corruption can be achieved using two further signals (TBL and WP). Finally two reset signals (RP and INIT ) are available to put the memory into a known state.

The data signals, control signal and clock are designed to be compatible with PCI electrical specifications. The interface operates with clock speeds up to 33MHz.

The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Standby, Reset and Block Protection.

Bus Read. Bus Read operations read from the memory cells, specific registers in the Command Interface or Firmware Hub Registers. A v alid Bus Read operation starts when Input Communication Frame, FWH4, is Low, V correct Start cycle is on FWH0-FWH3. On the following clock cycles the Host will send the Memory ID Select, Address and other control bits on FWH0-FWH3. The memory responds by outputting Sync data until the wait-states have elapsed followed by Data0-Data3 and Data4Data7.

Refer to Table 4, FWH Bus Read Field Definitions, and Figure 5, FWH Bus Read Waveforms (1-byte), for a description of the Field definitions for each clock cycle of the transfer. S ee T able 16, AC Measurement Conditions (F WH Interface), an d Fi gure 10, AC Signal Timing Waveforms (FWH Interface), for details on the timings of the signals.

Bus Write. Bus Write operations write to the Command Interface or Firmware Hub Registers. A

, as Clock rises and the

valid Bus Write operation starts when Input Communication Frame, FWH4, is Low, V

, as Clock rises and the correct Start cycle is on FWH0-FWH3. On the following Clock cycles the Host will send the Memory ID Select, Address, other control bits, Data0-Data3 and Data4-Data7 on FWH0-FWH3. The memory outputs Sync data until the wait-states have elapsed.

Refer to Table 5, FWH Bus Write Field Definitions, and Figure 6, FWH Bus Write Waveforms, for a description of the Field definitions for each clock cycle of the transfer. See Table 16, AC Measurement Conditions (FWH Interface), and Figure 10, AC Signal Timing Waveforms (FWH Interface), for details on the timings of the signals.

Bus Abort. The Bus Abort operation can be used to immediately abort the current bus operation. A Bus Abort occurs when FWH4 is driven Low, V

during the bus operation; the memo ry will tri-state the Input/Output Communication pins, FWH0FWH3.

Note that, during a Bus Write operation, the Command Interface starts executing the command as soon a s the data is f ully received; a Bus Abort during the final TAR cycles is not guaranteed to abort the command; the bus, however, will be released immediately.

Standby. When F WH4 is High, V

, the me mory

is put into Standby mode where FWH0-FWH3 are put into a high-impedance state and the Supply Current is reduced to the Standby level, I

CC1

Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when Interface Reset, RP Rese t, IN IT Low, V

, is Low, VIL. RP or IN IT must be held

, for t

. The memory resets to Read

PLPH

, or CPU

mode upon return from Res et mo de and the Lock Registers return to their default states regardless of their state before Reset, see Table 12. If RP

goes Low, VIL, during a Program or Erase

INIT

operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to t

PLRH

to abort a

Program or Erase operation. Block Protection. Block Protection can be

forced using the signals Top Block Lock, TBL Write Protect, WP

, regardless of the state of the

, and

Lock Registers.

8/39

Table 4. FWH Bus Read Field Definitions

Clock Cycle

Number

3-9 7 ADDR XXXX I

10 1 MSIZE 0X0Xb I

11 1 TA R 1111b I

12 1 TA R 1111b (float) O

13-14 2 WSYNC 0101b O

15 1 RSYNC 0000b O

16-17 2 DATA XXXX O

17+

5(2

Clock Cycle

Count

Field

FWH0-

FWH3

1 1 START 1101b I

2 1 IDSEL XXXX I

2 WSYNC

-1)

0 (1-byte)

75 (16-byte)

155 (32-byte)

MULTI-

BYTE

1 RSYNC

2 DATA

1 TAR 1111b O

1TAR

1111b

(float)

Memory

I/O

N/A

M50FW002

Description

On the rising edge of CLK with FWH4 Low, the contents of FWH0-FWH3 indicate the start of a FWH Read cycle.

Indicates which FWH Flash Memory is selected. The value on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed.

A 28-bit address phase is transferred starting with the most significant nibble first.

Indicates how many bytes will be transferred during multi-byte read operations. The FWH Flash Memory supports 1-byte (0000b), 16-byte (0100b) and 32-byte (0101b) transfers.

The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle.

The FWH Flash Memory takes control of FWH0-FWH3 during this cycle.

The FWH Flash Memory drives FWH0-FWH3 to 0101b (short wait-sync) for two clock cycles, indicating that the data is not yet available. Two wait-states are always included.

The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating that data will be available during the next clock cycle.

Data transfer is two CLK cycles, starting with the least significant nibble.

For each subsequent byte of data repeat cycles 13-17 (2WSYNC + 1RSYNC + 2DATA) 2

Flash Memory supports n = 0000b (1-byte), n = 0100b (16-byte) and n = 0101b (32-byte) reads.

The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate a turnaround cycle.

The FWH Flash Memory floats its outputs, the host takes control of FWH0-FWH3.

-1 times. The FWH

Figure 5. FWH Bus Read Waveforms (1-byte)

CLK

FWH4

FWH0-FWH3

Number of clock cycles

START IDSEL ADDR MSIZE TAR SYNC DATA TAR

11712322

AI03437

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Table 5. FWH Bus Write Field Definitions

Clock Cycle

Number

Clock Cycle

Count

Field

FWH0-

FWH3

Memory

I/O

Description

1 1 START 1110b I

On the rising edge of CLK with FWH4 Low, the contents of FWH0-FWH3 indicate the start of a FWH Write Cycle.

Indicates which FWH Flash Memory is selected. The value

2 1 IDSEL XXXX I

on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed.

3-9 7 ADDR XXXX I

A 28-bit address phase is transferred starting with the most significant nibble first.

10 1 MSIZE 0000b I Always 0000b (single byte transfer).

11-12 2 DATA XXXX I

13 1 TAR 1111b I

14 1 TAR

1111b

(float)

15 1 SYNC 0000b O

16 1 TAR 1111b O

17 1 TAR

1111b

(float)

N/A

Data transfer is two cycles, starting with the least significant nibble.

The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle.

The FWH Flash Memory takes control of FWH0-FWH3

during this cycle. The FWH Flash Memory drives FWH0-FWH3 to 0000b,

indicating it has received data or a command. The FWH Flash Memory drives FWH0-FWH3 to 1111b,

indicating a turnaround cycle. The FWH Flash Memory floats its outputs and the host takes

control of FWH0-FWH3.

Figure 6. FWH Bus Write Waveforms

CLK

FWH4

FWH0-FWH3

Number of clock cycles

START IDSEL ADDR MSIZE DATA TAR SYNC TAR

11712212

AI03441

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M50FW002

Address/Address Multiplexed (A/A Mux) Bus Operations

The Address/Address Multiplexed (A/A Mux) Interface has a more traditional style interface. The signals consist of a multiplexed address signals (A0-A10), data signals, (DQ0-DQ7) and three control signals (RC signal, RP

, can be used to reset the memory.

, G, W). An additional

The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash Programming equipment for faster factory programming. Only a subset of the features available to the Firmware Hub (FWH) Interface are available; these include all the Commands but exclude the Security features and other registers.

The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Output Disable and Reset.

When the Address/Address Multiplexed (A/A Mux) Interface is selected all the blocks are unprotected. It is not possible to protect any blocks through this interface.

Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature and the Status Register. A valid Bus Read operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC Write Enable (W be High, V

) and Interface Reset (RP) must

, and Output Enable, G, Low, VIL, in

. Then

order to perform a Bus Read operation. The Data Inputs/Outputs will output the value, see Figure 12, Read AC Waveforms (A/A Mux Interface), and Table 24, A/A Mux Interface Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC the Data Inputs/Outputs; Output Enable, G Interface Reset, RP Enable, W

, must be Low, VIL. The Data Inputs/

. The data should be set up on

, and

, must be High, VIH and Write

Outputs are latched on the rising edge of Write Enable, W

. See Figure 13, and Table 25, A/A Mux Interface Write AC Characteristics, for details of the timing requirements.

Output Disa bl e . The data outputs are high-impedance when the Output Enable, G

, is at VIH.

Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when RP held Low, V

for t

is Low, VIL. RP must be

. If RP is goes Low, VIL,

PLPH

during a Program or Erase operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to t

to abort a Program or Erase operation.

PLRH

Table 6. A/A Mux Bus Operations

Operation G W RP

Bus Read Bus Write Output Disable Reset

or V

VIL or V

Table 7. Manufacturer and Device Codes

Operation G

Manufacturer Code Device Code

W RP A17-A1 A0 DQ7-DQ0

Don’t Care Data Output

VCC or V

Don’t Care Hi-Z Don’t Care Hi-Z

V V

PPH

DQ7-DQ0

Data Input

20h 29h

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M50FW002

Table 8. Commands

Command

Cycles

Read Memory Array 1 X FFh Read Status Register 1 X 70h

1st 2nd 3rd 4th 5th

Addr Data Addr Data Addr Data Addr Data Addr Data

Bus Write Operations

Read Electronic Signature

1X 90h 1X 98h 2X 40hPAPD

Program

2X 10hPAPD

Quadruple Byte Program 5 X 30h

A Chip Erase 2 X 80h X 10h Block Erase 2 X 20h BA D0h Clear Status Register 1 X 50h Program/Erase Suspend 1 X B0h Program/Erase Resume 1 X D0h

1X 00h 1X 01h

Invalid/Reserved

1X 60h 1X2Fh 1XC0h

Note: X Don’t Care, PA Program Address, PD Program Data, A

Read Memory Array: After a Read M em ory Array command, read the memory as normal unti l another comm and is issued. Read Status Register: After a Read Status Register command, read the Status Register as normal until another command is issued. Read Electronic Signature: After a Read E l ectronic S i gnature c ommand, read Manufacturer C ode, Device Code unt i l another co m-

mand is issued. Block Erase , Byte Pr o gram : After these commands, read the Status Register until the command completes and another command is issued. Quadruple Byte Program: This command is only valid in A/A Mux mode. Addresses A differing only for address bit A0 and A1. After this command read the Status Register until the command completes and another command is issued. Chip Erase: This command is only valid in A/A Mux mode. After this command, read the Status Register until the command completes and another command is issued.

Clear Status Register: After th e Clear Status Register comman d bi t s 1, 3, 4 and 5 in the Status Reg i st er are reset to ‘ 0’ . Program/Erase Susp end: After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read Status

Register, Program (during Era se suspend ) and Program/ Erase resum e commands. Program /Erase Re sume: Af ter the P rogr am /Era se Re sume co mmand t he su sp ended P rogra m/E ras e o perat ion re sum es, read th e Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Invalid/Reserved: Do not use Invalid or Reserved commands.

Consecutive Addresses, BA Any ad dress in the Block.

1,2,3,4

, A2, A3 and A4 must be consecutive addresses

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