SGS Thomson Microelectronics M48T128Y-70PM1, M48T128Y, M48T128V Datasheet

3.3V-5V 1 Mbit (128Kb x8) TIMEKEEPER® SRAM

■ INTEGRATED ULTRA LOW POWER SRAM,

REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT, BATTERY, AND CRYSTAL

■ BCD CODED YEAR, MONTH, DAY, DATE,

HOURS, MINUTES, and SECONDS

■ AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■ WRITE PROTECT VOLTAGES

(V

= Power-fail Deselect Voltage):

PFD

– M48T128Y: 4.1V ≤ V
– M48T128V: 2.7V ≤ V

■ CONVENTIONAL SRAM OPERATION;

UNLIMITED WRITE CYCLES

■ SOFTWARE CONTROLLED CLOCK

CALIBRATION for HIGH ACCURACY
APPLICATIONS

■ 10 YEARS of DATA RETENTION and CLOCK

OPERATION in the ABSENCE of POWER

■ PIN and FUNCTION COMPATIBLE with

JEDEC STANDARD 128K X 8 SRAMS

■ SELF-CONTAINED BATTERY and CRYSTA L

in DIP PACKAGE

Table 1. Signal Names

A0-A16 Address Inputs

DQ0-DQ7 Data Inputs / Outputs

PFD
PFD

≤ 4.5V
≤ 3.0V

M48T128Y
M48T128V

32

1

PMDIP32 (PM)

Module

Figure 1. Logic Diagram

V

CC

17

A0-A16 DQ0-DQ7

W

E

M48T128Y
M48T128V

8

E

G
W

V

CC

V

SS

NC Not Connected Internally

Chip Enable Input

Output Enable Input
Write Enable Input

Supply Voltage

Ground

G

V

SS

AI02244

1/14March 2000

M48T128Y, M48T128V

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

STG

V

IO

V

CC

I

O

P

D

Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoo ts bel ow –0.3V ar e not allowed on any pi n while in the B attery Back-up mode.

Ambient Operating Temperature 0 to 70 °C
Storage Temperature (VCC Off, Oscillator Off)
Input or Output Voltages

Supply Voltage

Output Current 20 mA
Power Dissipation 1 W

rating only and functi onal opera tion of the dev i ce at these or any other conditions above thos e i ndi cated in the operational section
of this spec ification is not im plied. Exposure t o the abso lute max imum rat ing cond itions for extende d period s of tim e may affe ct
reliability.

Figure 2. DIP C on ne ctions

(1)

–40 to 70 °C

–0.3 to V
M48T128Y –0.3 to 7.0 V
M48T128V –0.3 to 4.6 V

CC

+0.3

V

It also provides the non-volatility of Flash without
any requirement for special write timing or limita­tions on the number of writes that can be per-

NC V

1

A16

2
3

A14

4

A12

5

A7

6

A6

7

A5

8

A4
A3
A2
A1
A0

DQ0

DQ2

SS

M48T128Y
M48T128V

9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

AI02245

CC

A15
NC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

formed. The 32 pin 600 mil DIP Hybrid houses a
controller chip, SRAM, quartz crystal, and a long
life lithium button cell in a single package.

Figure 3 illustrates the static memory array and the
quartz controlled clock oscillator. The clock loca­tions contain the year, month, date, day, hour,
minute, and second in 24 ho ur BCD format. Cor­rections for 28, 29 (leap year), 30, and 31 day
months are made automatically. Byte 1FFF8 h is
the clock control register. This byte controls user
access to the clock information and also stores the
clock calibration setting. The seven clock bytes
(1FFFFh - 1FFF8h) are not the actual clock
counters, they are m emo ry locations cons isting of

BiPORT™ read/write memory cells within the stat­ic RAM array. The M48T128Y/V includes a clock
control circuit which updates the clock bytes with
current information once per second. The informa­tion can be accessed by the user in the same man­ner as any other location in the static memory
array. The M48T128Y/V also has its own Power­Fail Detect circuit. This control circuitry constantly
monitors the supply voltage for an out of tolerance

DESCRIPTION

The M48T128Y/V TIMEKEEPER RAM is a 128Kb
x 8 non-volatile static RAM and real time clock.
The special DIP package provides a fully integrat­ed battery back-up memory and real time clock so-

condition. When V
write pro te c ts the TIMEKEEPER register data an d
external SRAM, providing data security in the
midst of unpredictable system operation. As V
falls, the control circuitry automatically switches to
the battery, maintaining data and clock operation
until valid power is restored.

is out of t olerance, the ci rcuit

CC

CC

lution. The M48T128Y/V directly replaces industry
standard 128Kb x 8 SRAM.

2/14

M48T128Y, M48T128V

≤ V

V

or

PFD

SO

CC

(1)

(min)

(2)

(2)

E G W DQ0-DQ7 Power

V

IH

V

IL

V

IL

V

IL

X X X High Z CMOS Standby
X X X High Z Battery Back-up Mode

Table 3. Operating Modes

Mode

Deselect
Write
Read
Read

Deselect
Deselect

Note: 1. X = VIH or VIL; VSO = Battery Back-up Swit ch ov er Volta ge.

2. See T able 7 for details.

4.5V to 5.5V

3.0V to 3.6V

V

to V

SO

READ MODE

The M48T128Y/V is in the Read Mode whenever
W

(Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 A d­dress Inputs defines which one of the 131,072
bytes of data is to be accessed.

Valid data will be available at the Data I/O pins
within t
address input signal is stable, providing the E
G

access times are also satisfied. If the E and G

(Address Access Time) after the la st

AVQV

and

access tim es are not me t, valid da ta w ill be avail­able after the latter of the Chip Enable Access
Times (t
(t

). The state of the eight three-state Data I/O

GLQV

signals is controlled by E
activated before t
to an indeterminate state until t
dress Inputs are changed while E
active, output data will remain valid for t

) or Output Enable Access Time

ELQV

and G. If the outputs are

, the data lines will be driven

AVQV

AVQV

. If the Ad-

and G remain

AXQX

(Out­put Data Hold Time) but will go indeterminate until
the next Addres s Acce ss.

X X High Z Standby
X

V

IL

V

IH

V

IL

V

IH

V

IH

D

IN

D

OUT

High Z Active

Active
Active

Table 4. AC Measurement Conditions

Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V

Note that Output Hi-Z is defined as the point where data is no longer
driven.

Figure 3. AC Testing Load Circuit

DEVICE
UNDER

TEST

650Ω

CL = 100pF
or 50pF

(2)

1.75V

(1)

WRITE MODE

The M48T128Y/V is in the Wri te Mode whenever

(Write Enable) and E (Chip Enable) are low

W
state after the address inputs are stable. The start
of a write is referenced from the latter occurring
falling edge of W
earlier rising edge of W
be held valid throughout the cycle. E
turn high for a minimum of t
or t

from Write Enable prior to the initiation of

WHAX

or E. A write is terminated by the

or E. The addresses must

or W must r e-

from Chip Enable

EHAX

another read or write cycle. Data-in must be valid

prior to the end of write and remain valid for

t

DVWH

t

afterward. G should be kept high during

WHDX

write cycles to avoid bus c ontention; although, if
the output bus has been activated by a low on E
and G a low on W will disable the outputs t
ter W

falls .

WLQZ

af-

CL includes JIG capacitance

Note: 1. 50pF for M48T128V (3.3V).

2. Exc l udi ng open dr ai n output pins.

AI03630

DATA RETENTION MODE

With valid V

applied, the M48T128Y/V operates

CC

as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au­tomatically deselect, write protecting itself when
V

falls between V

CC

(max), V

PFD

(min) win-

PFD

dow. All outputs become high impedance an d all
inputs are treated as "don't care".

3/14

M48T128Y, M48T128V

Figure 4. Block Diagram

OSCILLATOR AND

CLOCK CHAIN

32,768 Hz
CRYSTAL

POWER

LITHIUM

CELL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

V

CC

Note: A power failure during a write cycle may cor­rupt data at the current addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltage s below V
in a write protected state, provided the V
time is not less than t
spond to transient noise s pi kes on V

(min), the memory will be

PFD

. The M48T128Y/V may re-

F

that cr os s

CC

CC

fall

into the deselect window during the time the de­vice is sampling V
power supply lines is recomm ended. When V

. Therefore, decoupling of the

CC

CC

drops below VSO, the control circuit switches pow­er to the internal battery, preserving data and pow­ering the clock. The internal energy source will
maintain data in the M48T128Y/V for an accumu­lated period of at least 10 years at room tem pera­ture. As system power rises above V

SO

, the
battery is disconnected, and the power supply is
switched to external V
t

after VCC reaches V

REC

. Deselect continues for

CC

(max).

PFD

8 x 8

TIMEKEEPER

REGISTERS

A0-A16

DQ0-DQ7

E

W

G

AI01804

V

PFD

131,064 x 8

SRAM ARRAY

V

SS

CLOCK OPERATIONS
Reading the Clock

Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME­KEEPER cel ls in th e RAM array a re o n ly data re g ­isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself. Updating is halted when a ’1’ is written
to the READ bit, D6 in the Control Register
(1FFF8h). As long as a ’1’ remains in that position,
updating is halted. After a halt is issued, the regis­ters reflect the count; that is, the day, date, and
time that were current at the moment the halt com­mand was issued. All of the TIMEKEEPER regis­ters are updated simultaneously. A halt will not
interrupt an update in progress. Updating occurs 1
second after the READ bit is reset to a ’0’.

4/14

M48T128Y, M48T128V

Table 5. Capacitance

(T

= 25 °C, f = MHz)

A

(1)

Symbol Parameter Test Condition Min Max Unit

C

IN

C

IO

Note: 1. Effective capacitance meas ured with po wer suppl y at 5V.

2. Outputs deselected.

Input Capacitance

(2)

Input / Output Capacitance

V

V

OUT

IN

= 0V

= 0V

20 pF
20 pF

Table 6A. DC Characteristics

= 0 to 70 °C; VCC = 4.5V to 5.5V)

(T

A

Symbol Parameter Test Condition Min Max Unit

(1)

I

LI

I

LO

I
I

V

V

V

Note: 1. Outputs deselected.

Input Leakage Current

(1)

Output Leakage Current

I

Supply Current Outputs open 95 mA

CC

Supply Current (Standby) TTL

CC1

Supply Current (Standby) CMOS

CC2

Input Low Voltage –0.3 0.8 V

V

IL

Input High Voltage 2.2

IH

Output Low Voltage

OL

Output High Voltage

OH

0V ≤ V

IN

0V ≤ V

OUT

E

= V

E

= VCC –0.2V

I

= 2.1mA

OL

I

= –1mA

OH

≤ V

≤ V

IH

CC

CC

±2 µA
±2 µA

8mA
4mA

V

+ 0.3

CC

0.4 V

2.4 V

V

Table 6B. DC Characteristics

= 0 to 70 °C; VCC = 3.0V to 3.6V)

(T

A

Symbol Parameter Test Condition Min Max Unit

(1)

Input Leakage Current

I

LI

(1)

Output Leakage Current

I

LO

I
I
I

V

V

V

Note: 1. Outputs deselected.

Supply Current Outputs open 50 mA

CC

Supply Current (Standby) TTL

CC1

Supply Current (Standby) CMOS

CC2

Input Low Voltage –0.3 0.4 V

V

IL

Input High Voltage 2.2

IH

Output Low Voltage

OL

Output High Voltage

OH

0V ≤ V

IN

0V ≤ V

OUT

E

= V

E

= VCC –0.2V

I

= 2.1mA

OL

I

= –1mA

OH

≤ V

≤ V

IH

CC

CC

±2 µA
±2 µA

4mA
3mA

V

+ 0.3

CC

0.4 V

2.2 V

V

5/14