SGS Thomson Microelectronics M41T81 Datasheet
SERIAL ACCESS RTC WITH ALARMS
FEATURES SUMMARY
■ 2.0 TO 5.5V CLOCK OPERATING VOLT A GE
■ COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE , MONTH, YEAR, and
CENTURY
■ AUTOMATIC SWITCH-OVER and DESELECT
CIRCUITRY
■ SERIAL INTERFAC E SU PPO R TS I
(400KHz PROTOCOL)
■ PROGRAMMABLE ALAR M and INTERRUPT
FUNCTION (valid even during Battery Back-up
Mode)
■ WATCHDOG T IM E R
■ LOW OPERATING CURRENT OF 400µA
■ BATTERY BACK-UP NOT RECOMMENDED
FOR 3.0V APPLICAT IO N S (C APAC ITOR
BACK-UP ONLY)
■ BATTERY OR SUPER-CAP BACK-UP
■ OPERATING TEMPERATURE OF –40 TO
85°C
■ ULTRA-LOW BATTERY SU PPL Y C URRENT
OF 1µA
■ PACKAGE OPTI ONS INCLUDE A 28-LEAD o r
18-LEAD EMBE DDE D CRYSTAL SOIC
2
C BUS
M41T81
Figure 1. 8-pi n S OI C Package
8
1
SO8 (M)
Figure 2. 28-pin (300mil) SOIC Package*
EMBEDDED Crystal
SOX28 (MX)
Figure 3. 18-pin (300mil) SOIC Package*
EMBEDDED Crystal
18
1
SOX18 (MY)
Rev. 2.0
1/28September 2003
M41T81
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 5. 8-pin SOIC (M) Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 7. 28-pin, 300mil SOIC (MX) Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. 18-pin, 300mil SOIC (MY) Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 8. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Crystal Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10. Serial Bus Data Transfer Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 11. Acknowledgement Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12. Bus Timing Requirements Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 13. Slave Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14. READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15. Alternative READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16. WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TIMEKEEPER® Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5
Table 10. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8
Figure 18. Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/28
M41T81
Figure 19. Back-up Mode Alarm Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Alarm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Square Wave Outp ut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output Driver Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Preferred Initial Power-on Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 13. Preferred Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 20. Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 21. Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3/28
M41T81
SUMMARY DESCRIPTION
The M41T81 Serial Access TIMEKEEPER
SRAM is a low power Serial RTC with a b uilt-in
32.768 KHz oscillator (external crystal controlled).
Eight bytes of the SRA M (see Table 10, page 16)
are used for the c lock/calendar function and are
configured in binary coded decimal (BCD) form at.
An additional 12 bytes of SRAM provide status/
control of Alarm, Watchdog and Square Wave
functions. Addresses and data are transferred serially via a two line, bi-directional I
2
C in ter fac e. The
built-in address register is incremented automatically after each WRITE or READ data byte.
The M41T81 has a built-in power sense circuit
which detects power failures and automatically
switches to the battery supply when a power f ailure occurs. The energy needed to sustain the
SRAM and clock operations can be supplied by a
Figure 4. Logic Diagram
V
V
BAT
CC
(1)
XI
(1)
XO
SCL
SDA
M41T81
IRQ/FT/OUT/SQW
®
small lithium button supply when a po wer failure
occurs. Functions avai lable to the user include a
non-volatile, time-of-day clock/calendar, Alarm interrupts, Watchdog Timer and programmable
Square Wave output. The eight clock address locations contain the century, year, month, date,
day, hour, minute, second and tenths/hundredths
of a second in 24 hour BCD format. Corrections for
28, 29 (leap year - valid until year 2100), 30 and 31
day months are made automatically.
The M41T81 is supplied in either an 8-pin SOIC or
an 18-pin (MY) or 28-pin (MX), 300mil SOIC package which includes an embedded 32kHz crystal.
The 8-pin and 28-pin, embedd ed c rystal SOI C requires only a user-supplied battery to provide nonvolatile operation.
Table 1. Signal Names
(1)
XI
(1)
XO
IRQ
/OUT/
FT/SQW
SDA Serial Data Input/Output
SCL Serial Clock Input
V
BAT
Oscillator Input
Oscillator Output
Interrupt / Output Driver / Frequency
Test / Square Wave (Open Drain)
Battery Supply Voltage
V
SS
Note: 1. For SO8 package only.
4/28
AI04613
V
CC
V
SS
Note: 1. For SO8 package only.
Supply Voltage
Ground
M41T81
Figure 5. 8-pin SOIC (M) Connections
1
XI
2
XO
V
BAT
V
SS
M41T81
3
45
8
V
CC
7
IRQ/FT/OUT/SQW
6
SCL
SDA
AI04769
Figure 6. 18-pin, 300mil SOIC (MY) Connections
1
NC
2
NC
3
NC
4
NC
5
NC
6
NC
7
NC
V
BAT
V
SS
8
9
M41T81
18
NC
17
NC
16
NC
15
V
14
NC
13
IRQ/FT/OUT/SQW
12
NC
11
SCL
10
SDA
CC
AI07830
Figure 8. Block Diagram
Figure 7. 28-pin, 300mil SOIC (MX) Connections
1
NC
2
NC
3
NC
4
NC
5
NC
6
NC
7
NC
NC
NC
NC
NC
8
9
10
11
M41T81
12
V
V
Note: 1. No Connect (NC) pin for 28-pin SOIC, but should be con-
13
BAT
14
SS
sidered t o have indicat ed function i n anticipation of replacement with 18-pin S O I C.
28
V
27
NC
26
IRQ/FT/OUT/SQW
25
NC
V
24
23
NC
22
SCL
21
NC
20
V
19
NC
18
IRQ/FT/OUT/SQW
17
SDANC
16
SCL
15
SDA
CC
CC
SS
(1)
(1)
(1)
(1)
AI07805
CRYSTAL
SDA
SCL
V
CC
V
BAT
Note 1. Open drain output
Note 2. VSO = V
– 0.5V (typ)
BAT
V
SO
OSCILLATOR
INTERFACE
(2)
COMPARE
32KHz
I2C
PROTECT
WRITE
REAL TIME CLOCK
CALENDAR
RTC W/ALARM
& CALIBRATION
WATCHDOG
SQUARE WAVE
INTERNAL
AFE
WDF
SQWE
POWER
IRQ/FT/OUT/SQW
AI04616
(1)
5/28
M41T81
MAXIMUM RATI N G
Stressing the device ab ove the rating listed in t he
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the dev ice at
these or any other conditions above those indicated in the Operating sections of this specification is
Table 2. Absolute Maximum Ratings
Sym Parameter Value Unit
T
STG
V
T
SLD
V
P
Note: 1. Reflow at peak temp erature of 2 15°C to 225°C for < 60 s econds (to tal therma l budget not to exceed 180° C for betw een 90 to 12 0
Storage Temperature (VCC Off, Oscillator Off)
Supply Voltage
CC
(1)
Lead Solder Temperature for 10 Seconds 260 °C
Input or Output Voltages –0.3 to Vcc+0.3 V
IO
I
Output Current 20 mA
O
Power Dissipation 1 W
D
secon ds).
CAUTION: Negative under shoots below –0.3 volts ar e not allowed on any pin while i n the Batter y B ack-Up Mode
not implied. Exposure to Absol ute Maxim um Ra ting conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics SURE Program and other relevant quality documents.
SOIC –55 to 125
–0.3 to 7
°C
V
6/28
DC AND AC PARAMETERS
This section summarizes the operat ing and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the M easure-
Table 3. Operating and AC Measurement Conditions
Parameter M41T81
M41T81
ment Conditions listed in the rel evant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Supply Voltage (V
Ambient Operating Temperature (T
Load Capacitance (C
CC
)
)
A
)
L
2.0 to 5.5V
–40 to 85°C
100pF
Input Rise and Fall Times ≤ 50ns
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note: Out put Hi-Z is def i ned as the poi nt where dat a i s no longer dri ven.
0.2VCC to 0.8 V
0.3V
to 0.7 V
CC
Figure 9. AC Measurement I/O Waveform
0.8V
0.2V
CC
CC
0.7V
0.3V
AI02568
CC
CC
CC
CC
Table 4. Capacitance
Symbol
C
IN
(3)
C
OUT
t
LP
Note: 1. Effective capacitance measured with power supply at 5V; sam p l ed only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselect ed.
Input Capacitance 7 pF
Output Capacitance 10 pF
Low-pass filter input time constant (SDA and SCL) 50 ns
Parameter
(1,2)
Min Max Unit
7/28
M41T81
Table 5. DC Characteristics
IN
≤ V
≤ V
CC
(1)
CC
CC
– 0.3V
= 3V
BAT
Min Typ Max Unit
0.7V
CC
(3)
2.5
0.6 1 µA
Sym Parameter
I
Input Leakage Current
LI
I
Output Leakage Current
LO
I
I
Supply Current Switch Freq = 400kHz 400 µA
CC1
Supply Current (standby)
CC2
V
Input Low Voltage –0.3
IL
V
Input High Voltage
IH
Output Low Voltage
V
OL
Output Low Voltage (Open Drain)
(2)
V
BAT
I
Note: 1. Valid for Ambient Operating T em perature: TA = –40 to 85°C ; VCC = 2.0 to 5. 5V (except wh ere noted ) .
Battery Supply Voltage
Battery Supply Current
BAT
2. STMic roelectronics recommends the RAYOVAC BR 1225 or BR16 32 (or equiva l ent) as the battery supply.
3. After s wi tchover (V
4. For re chargeabl e back-up, V
5. For IRQ
/FT/OUT/SQW pin (Open Drain)
SO
), V
(min) can be 2.0V for crystal with RS = 40KΩ.
BAT
(max) may be considered VCC.
BAT
(5)
Test Condition
0V ≤ V
0V ≤ V
OUT
SCL,SDA = V
I
= 3.0mA 0.4
OL
IOL = 10mA
T
= 25°C, VCC = 0V
A
Oscillator ON, V
3
±1 µA
±1 µA
100 µA
0.3V
CC
VCC + 0.3
0.4 V
(4)
3.5
V
V
V
V
Table 6. Crystal Electrical Characteristics
Sym
f
O
R
S
C
L
Note: 1. External ly supp lied if usin g th e SO8 pa ckag e. S TMic roe lectr onic s re com mend s th e KD S D T-38 : 1T A/1T C252 E127 , Tuni ng F ork
2. Load capacitors are in te grated within the M41T81. Circuit board layout considerations for the 32.768 kHz cryst al of m i ni m um trace
Resonant Frequency 32.768 kHz
Series Resistance
Load Capacitance 12.5 pF
Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at kouhou@kds j .c o. j p or http:// www.kdsj.c o.jp for further inform ation on this cr ystal type.
lengths an d i solation from RF genera ting signals should be taken into acco unt.
Parameter
(1,2,3)
Min Typ Max Units
60
kΩ
8/28
OPERATION
The M41T81 clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave address (D0h). The 20 bytes contained in the device
can then be accessed sequentially in the following
order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
4. Century/Hours Register
5. Day Register
6. Date Register
7. Month Register
8. Year Register
9. Control Register
10. Watchdog Register
11 - 16. Alarm Registers
17 - 19. Reserved
20. Square Wave Register
The M41T81 clock continually monitors V
out-of-tolerance condition. Should V
V
, the device terminates an ac ces s in progress
SO
CC
for an
CC
fall be low
and resets the device add ress counter. Inputs to
the device will not be recognized at this time to
prevent erroneous data from being written to the
device fro m a an ou t-o f-tolerance syste m. The device also automatically switches over to the battery
and powers down into an ultra low current mode of
operation to conserve battery life. As system power returns and V
rises above VSO, the battery is
CC
disconnected, and the power supply is switched to
external V
CC
.
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different ICs. It consists of two lines: a bi-directional data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the bus
is not busy.
– During data trans fer, the dat a line mus t remain
stable whenever the clock line is High.
M41T81
– Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A c hange in the st ate of the
data line, from high to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The devices that are controlled by the master are cal led
“slaves.”
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low during the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must signal an end of data to the slave transm itter by not
generating an acknowledge on t he last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
9/28
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