SGS Thomson Microelectronics M40Z300W, M40Z300VMH1, M40Z300MH1, M40Z300 Datasheet
1/16March 2000
M40Z300
M40Z300W
NVRAM CONTROLLER for up to EIGHT LPSRAM
■ CONVERT LOW POWER SRAMs int o
NVRAMs
■ PRECISION POWER MONITORING and
POWER SWITCHING CIRCUITRY
■ AUTOMATIC WRITE-PROTECTION when V
CC
is OUT-OF-T OLE R A N CE
■ TWO INPUT DECODER ALLOWS CONTROL
for up to 8 SRAMs (with 2 devices active in
parallel)
■ CHOICE of SUPPLY VOLTAGES and
POWER-FAIL DESELECT VOLTAGES:
– M40Z300:
V
CC
= 4.5V to 5.5V
THS = V
SS
4.5V ≤ V
PFD
≤ 4.75V
THS = V
OUT
4.2V ≤ V
PFD
≤ 4.5V
– M40Z300W:
V
CC
= 3.0V to 3.6V
THS = V
SS
2.8V ≤ V
PFD
≤ 3.0V
V
CC
= 2.7V to 3.3V
THS = V
OUT
2.5 ≤ V
PFD
≤ 2.7V
■ RESET OUTPUT (RST) for POWER ON
RESET
■ LESS THAN 12ns CHIP ENABLE ACCESS
PROPAGATION DELAY (fo r 5 .0 V devi ce )
■ PACKAGING INCL UD ES a 28-L EAD SOI C
and SNAPHAT
®
TOP, or a 16-LEAD SOIC
(to be Ordered Separately)
■ SOIC PACKAGE PROVIDES D IREC T
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY
■ BATTERY LOW PIN (BL)
DESCRIPTION
The M40Z300/W NVRAM Con troller is a self-contained device which converts a standard low-power SRAM into a non-volatile memory. A precision
voltage reference and comparator monitors the
V
CC
input for an out-of-tolerance condition.
Figure 1. Logic Diagram
AI02242
THS
V
CC
M40Z300
M40Z300W
BL
V
SS
E
V
OUT
B
A
E1
CON
E2
CON
E3
CON
E4
CON
RST
B+
(1)
B–
(1)
NOTE: 1. For 16-pin SOIC package only.
28
1
SOH28 (MH)
SNAPHAT (SH)
Battery
16
1
SO16 (MQ)
M40Z300, M40Z300W
2/16
When an invalid VCC condition occurs, t he conditioned chip enable outputs (E1
CON
to E4
CON
) are
forced inactive to write-protect the st ored data in
the SRAM. During a power failure, the SRAM is
switched from the V
CC
pin to the lithium cell within
the SNAPHAT to provide the energy required for
data retention. On a subsequent power-up, the
SRAM remains write protect ed until a valid power
condition returns.
The 28 pin, 330 mil SOIC provides sockets with
gold plated contacts for direct connection to a separate SNAPHAT housing containing the battery.
The SNAPHAT housing has gold plated pins
which mate with the sockets, ensuring reliable
connection. The housing is keyed to prevent improper insertion. This unique design allows the
SNAPHAT battery p acka ge t o b e m ount ed o n t op
of the SOIC package after the c ompletion of the
surface mount process which greatly reduces the
board manufacturing process complexity of either
directly soldering or inserting a battery into a soldered holder. Providing non-volatility becomes a
"SNAP".
The 16 pin SOIC provides battery pins for an external user supplied battery.
Figure 2A. SOIC28 Connections
AI02243
8
2
3
4
5
6
7
9
10
11
12
13
14
22
21
20
19
18
17
16
15
28
27
26
25
24
23
1
NC
NC
BL
NC
A
NC
B
RST
NC
NC
NC
E1
CON
NC
E3
CON
E
E2
CON
NC
NC
NCNC
THS
NCV
SS
E4
CON
NC
NC
V
OUT
V
CC
M40Z300
M40Z300W
Table 1. Signal Names
THS Threshold Select Input
E
Chip Enable Input
E1
CON
-E4
CON
Conditioned Chip Enable Output
A, B Decoder Inputs
RST
Reset Output (Open Drain)
BL
Battery Low Output (Open Drain)
V
OUT
Supply Voltage Output
V
CC
Supply Voltage
V
SS
Ground
B+ Positive Battery Pin
B– Negative Battery Pin
NC Not Connected Internally
Figure 2B. SOIC16 Connections
AI03624
8
2
3
4
5
6
710
16
15
14
13
12
11
1
A
RST
B
E1
CON
E
E2
CON
B– (B+)V
SS
NC
V
OUT
V
CC
M40Z300
M40Z300W
BL
THS
E3
CON
E4
CON
9
B+ (B–)
( ) = M40Z300W
3/16
M40Z300, M40Z300W
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional opera tion of the devi ce at these or any other conditions above thos e i ndi cated in th e operational section
of this spec ification is not im plied. Exposure t o the abso lute max imum rat ing cond itions for extende d period s of tim e may affe ct
reliability.
CAUTION: Negative undershoots below –0. 3V are not allowe d on any pin while i n the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Symbol Parameter Value Unit
T
A
Ambient Operating Temperature 0 to 70 °C
T
STG
Storage Temperature (VCC Off) SNAPHAT
SOIC
–40 to 85
–55 to 125
°C
V
IO
Input or Output Voltages
–0.3 to V
CC
+0.3
V
V
CC
Supply Voltage M40Z300
M40Z300W
–0.3 to 7
–0.3 to 4.6
V
I
O
Output Current 20 mA
P
D
Power Dissipation 1 W
OPERATION
The M40Z300/W, as shown in Figure 4, can c ontrol up to four (eight, if placed in parallel) standard
low-power SRAMs. These SRAMs must be configured to have the chip enable input disable all other
input signals. Most slow, low-power SRAMs are
configured like this, however many fast SRAMs
are not. During normal operating conditions, the
conditioned chip enable (E1
CON
to E4
CON
) output
pins follow the chip enable (E
) input pin with timing
shown in Table 7. An internal switch connects V
CC
to V
OUT
.
This switch has a vol tage drop of less than 0.3V
(I
OUT1
).
When V
CC
degrades during a power failure,
E1
CON
to E4
CON
are forced inactive inde pendent
of E
. In this situation, the SRAM is unconditionally
write protected as V
CC
falls below an out-of-toler-
ance threshold (V
PFD
). For the M40Z300 the pow-
er fail detection value associated with V
PFD
is
selected by the Threshold Select (THS) pin and is
shown in Table 6A. For the M 40Z300W, the THS
pin selects both the supply vo ltage and V
PFD
as
shown in Table 6B.
Note: In either case, THS pi n must b e connected
to either V
SS
or V
OUT
.
If chip enable access is in progress during a power
fail detection, that memory cycle continues to completion before the memory is write protected. I f the
memory cycle is not terminated within time t
WPT
,
E1
CON
to E4
CON
are unconditionally driven high,
write protecting the SRAM. A power failure during
a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest
of the SRAM’s contents. At voltages below V
PFD
(min), the user can be assured the memory will be
write protected within the Write Protect Time
(t
WPT
) provided the VCC fall time exceeds tF (See
Table 7).
As V
CC
continues to degrade, the internal switch
disconnects V
CC
and connects the internal battery
to V
OUT
. This occurs at the switchover voltage
(V
SO
). Below the VSO, the battery provides a volt-
age V
OHB
to the SRAM and can supply current
I
OUT2
(see Table 6A/6B).
When V
CC
rises above VSO, V
OUT
is switched
back to the supply voltage. Outputs E1
CON
to
E4
CON
are held inactive for t
CER
(120ms maxi-
mum) after the power supply has reached V
PFD
,
independent of the E
input, to all ow fo r proces sor
stabilization (see Figure 6).
M40Z300, M40Z300W
4/16
DATA RETENTION LIFETIME CALCULATION
Most low power SRAMs on the market today can
be used with the M40Z300/W NVRAM Cont roller.
There are, however some criteria which should be
used in making the final choice of which S RA M to
use. The SRAM must be designed in a way where
the chip enable input disables all other inputs to
the SRAM. This allows i nputs to the M40Z 300/W
and SRAMs to be Don’t Care once V
CC
falls below
V
PFD
(min). The SRAM should also guarantee
data retention down to V
CC
= 2.0V. T he chip enable access time must be sufficient to meet the
system needs with the chip enable propagation
delays included. If the SRAM includes a second
Chip Enable pin (E2), this pin should be tied to
V
OUT
.
If data retention lifetime is a critical parameter f or
the system, it is importa nt to re view the dat a retention current specifications for the particular
SRAMs being evaluated. M ost SRAMs specify a
data retention current at 3.0V. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally
at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retent ion current val ue of the
SRAMs can then be added to t he I
CCDR
value of
the M40Z300/W to de termine the t otal current requirements for data retention. The available battery capacity for the SNAPHAT of your choice can
then be divided b y this current to determine the
amount of data retention available (see Table 8).
CAUTION: Take care to avoid inadvertent discharge through V
OUT
and E1
CON
-E4
CON
after bat-
tery has been attached.
For a further more detailed review of lifetime cal-
culations, please see Application Note AN1012.
Tabl e 3. Truth Table
Inputs Outputs
E
BA
E1
CON
E2
CON
E3
CON
E4
CON
HXXHHHH
LLLLHHH
LLHHLHH
LHLHHLH
LHHHHHL
Figure 3. AC Testing Load Circuit
AI02393
CL = 50pF
CL includes JIG capacitance
333Ω
DEVICE
UNDER
TEST
1.73V
Table 4. AC Measurement Conditions
Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V
5/16
M40Z300, M40Z300W
POWER-ON RESET OUTPUT
All microprocessors have a reset input which forces them to a known state when starting. The
M40Z300/W has a reset output (RST
) pin which is
guaranteed to be low within t
WPT
of V
PFD
(See Table 7). This signal is an open drain conf iguration.
An appropriate pull-up resistor should be chosen
to control the rise time. This signal will be valid for
all voltage conditions, even when V
CC
equals VSS.
Once V
CC
exceeds the power failure detect volt-
age V
PFD
, an internal timer keeps RST low for
t
REC
to allow the power supply to stabilize.
TWO TO FOUR DECODE
The M40Z300/W includes a 2 input (A, B) decoder
which allows the control of up to 4 independent
SRAMs. The Truth Table for these inputs is shown
in Table 3.
Figure 4. Hardware Hookup
AI02395
V
CC
E
E1
CON
V
SS
V
OUT
V
CC
CMOS
SRAM
3.0V, 3.3V or 5V
THS
A
0.1µF
0.1µF
M40Z300
M40Z300W
Threshold
E
B
E2
CON
E3
CON
E4
CON
RST
BL
E
V
CC
CMOS
SRAM
0.1µF
E
V
CC
CMOS
SRAM
0.1µF
E
V
CC
CMOS
SRAM
0.1µF
To Microprocessor
To Battery Monitor Circuit
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