M36W216TI, M36W216BI
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SIGNAL DESCRIPTION
See Figure 2 Logic Diagram and Table 1, Sign al
Names, for a brief overview of the signals connected to this de vice.
Address Inputs (A0-A16). Addresses A0-A16
are common inputs for the Flash an d the SRAM
components. The Address Inputs select the cells
in the memory array to access during Bu s Read
operations. During Bus Write operations they control the commands sent to the Command Interface
of the internal state machine. The Flash memory is
accessed through the Chip Enable (
E
F
) and Write
Enable (W
F
) signals, while the SRAM i s acce sse d
through two Chip Enable ( ES
) and Write Enable
(W
S
) signals.
Address Inputs (A17-A19). Addresses A17-A19
are inputs for the Flash component only. The
Flash memory is acc essed through the Chip E nable (
E
F
) and Write Enable (WF) signals
Data Inputs/Outputs (DQ0-DQ15). The Data I/
O output the d ata stored at the selected addres s
during a Bus Read operation or in put a c om m and
or the data to be programmed durin g a Write Bus
operation.
Flash Chip Enable (
E
F
). The Chip Enable input
activates the Flash memory control logic, input
buffers, decoders and sense amplifiers. When
Chip Enable is at V
IL
and Reset is at VIH the device
is in active mode. When Chip Enable is at V
IH
the
memory is deselected, the outputs are high impedance and the power consumption is reduced to the
standby level.
Flash Output Enable (G
F
). The Output Enable
controls the data outputs during the Bus Read operation of the Flash memory.
Flash Write Enable (
W
F
). The Write Enable con-
trols the Bus Write operation of the Flash m emory’s Command Interface. The data and address
inputs are latched on the rising e dge of Chip Enable,
E
F
, or Write Enable, WF, whichever occurs
first .
Flash Write Protect (WP
F
). Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is at V
IL
, the
Lock-Down is enabled and the protection status of
the block cannot be changed. When Write Protect
is at V
IH
, the Lock-Down is disabled and the block
can be locked or unlocked. (refer to T able 6, Read
Protection Register and Protection Register Lock).
Flash Reset (RP
F
). The Reset input provides a
hardware reset of the Flash memory. When Reset
is at V
IL
, the memory is in reset mode: the outputs
are high impedance and the current c onsumption
is minimized. After Reset all blocks are in the
Locked state. When Reset is at V
IH
, the device is
in normal operation. Exiting reset mode the device
enters read array mode, but a negative t ransition
of Chip Enable or a change of the address is required to ensure valid data outputs.
SRAM Chip Enable (E1
S
, E2S). The Chip En-
able inputs activate the SRAM memory control
logic, input buffers and decoders. E1
S
at VIH or
E2
S
at VIL deselects the memory and reduces the
power consumption to the standby level. E1
S
or
E2
S
can also be used to control writing to the
SRAM memory array, while W
S
rema in s at V
IL.
It
is not allowed to set
E
F
at VIL and, E1S at VIL or
E2
S
at VIL at the same time.
SRAM Write Enable (W
S
). The Write Enable in-
put controls writing to the SRA M memory array.
W
S
is active low .
SRAM Output E nable (G
S
). The Output Enable
gates the outputs through the data buffers during
a read operation of the SRAM m emory. G
S
is ac-
tive low.
SRAM Upper Byte Enable (UB
S
). The Upper
Byte Enable enables the upper bytes for SRAM
(DQ8-DQ15). UB
S
is acti v e low.
SRAM Lower Byte Enable (LB
S
). The Lower
Byte Enable enables the lower bytes for SRAM
(DQ0-DQ7). LB
S
is active low.
V
DDF
and V
DDS
Supply Voltages. V
DDF
provides the power supply to the internal core of the
Flash Memory device. It is the main power s upply
for all operations (Read, Program and Erase).
V
DDQF
and V
DDS
Supply Voltage (2.7V to 3.3V).
V
DDQF
provides the power supply for the Flash
memory I/O pins and V
DDS
provides the power
supply for t he SRAM control pins. This a llows all
Outputs to be powered independently of the Flash
core power supply, V
DDF
. V
DDQF
can be tied to
V
DDS.
V
PPF
Program Supp ly Vol tage. V
PPF
is both a
control input and a power suppl y pin for t he F lash
memory. The two functions are selected by the
voltage range applied to the pin. The Supply Voltage V
DDF
and the Program Supply Vol tage V
PPF
can be applied in any order.
If V
PPF
is kept in a low voltage range (0V t o 3.6V)
V
PPF
is seen as a control input. In this case a volt-
age lower than V
PPLK
gives an absolute protection
against program or erase, while V
PPF
> V
PP1
enables these functions (see Table 6, DC Characteristics for the relevant values). V
PPF
is only
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect and program or erase operations continue.
If V
PPF
is in the range 11.4V to 12.6V it acts as a
power supply pin. In this condition V
PPF
must be
stable until the Program/Erase algorithm i s completed (see Table 19 and 20).