SGS Thomson Microelectronics M36W216T, M36W216B Datasheet
1/62
PRELIMINARY DATA
November 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M36W216TI
M36W216BI
16 Mbit (1Mb x16, Boot Block) Flash Memory
and 2 Mbit (128Kb x16) SRAM, Multiple Memory Product
FEATURES SUMMARY
■ MULTIPLE MEMORY PRODUCT
– 16 Mbit (1Mb x 16) Boot Block Flash Memory
– 2 Mbit (128Kb x 16) SRAM
■ SUPPLY VOLTAGE
–V
DDF
= V
DDS
= 2.7V to 3.3V
–V
DDQF
= V
DDS
= 2.7V to 3.3V
–V
PPF
= 12V for Fast Program (optional)
■ ACCESS TIME: 70ns, 85ns
■ LOW POWER CONSUMPTION
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M36W216TI: 88CEh
– Bottom Device Code, M36W216BI: 88CFh
FLASH MEMORY
■ MEMORY BLOCKS
– Parameter Blocks (Top or Bottom location)
– Main Blocks
■ PROGRAMMING TIME
– 10µs typical
– Double Word Programming Option
■ BLOCK LOCKING
– All blocks locked at Power up
– Any combination of blocks can be locked
–WP
F
for Block Lock-Down
■ AUTOMATIC STAND-BY MODE
■ PROGRAM and ERASE SUSPEND
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ COMMON FLASH INTERFACE
– 64 bit Security Code
■ SECURITY
– 64 bit user programmable OTP cells
– 64 bit unique device identifier
– One parameter block permanently lockable
SRAM
■ 2 Mbit (128K x 16 bit)
■ ACCESS TIME: 70ns
■ LOW V
DDS
DATA RETENTION: 1.5V
■ POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
Figure 1. Packages
FBGA
Stacked LFBGA66 (ZA)
12 x 8mm
M36W216TI, M36W216BI
2/62
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. LFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Address Inputs (A0-A16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Address Inputs (A17-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Inputs/Outputs (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Write Enable (WF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRAM Chip Enable (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRAM Output Enable (GS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
DDF
and VDDS Supply Voltages.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
DDQF
and V
DDS
Supply Voltage (2.7V to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
PPF
Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
SSF
and V
SSS
Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2
Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Device Capaci ta n ce. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. DC Character i stics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Stacked LFBGA66-12x8mm , 8x8 ball array, 0.8mm pitch, Bottom Vi ew Package Ou tline15
Table 7. Stacked LFBGA66 - 12x8mm, 8x8 ball array, 0.8 mm pitch, Package Mechanical Data . 15
Figure 8. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package) . . 16
Figure 9. Stac k ed LFBGA6 6 Daisy C hain - PC B Connect ions proposal (Top view through package).17
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M36W216TI, M36W216BI
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. Daisy Chain Orde r ing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
FLASH DEVICE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FLASH SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Flash Block Ad d re sse s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Flash Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . 20
FLASH BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1
Write.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output Disable.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Automatic Standby.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FLASH COMMAND INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Read Electronic Signature Comma nd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clear Status Regist e r Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Program/Erase Suspend Comm and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Program/Eras e Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Protection Regi ste r Pr o g ra m Comman d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4
Block Lock-Down Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10. Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Read Block Lock Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 13. Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 14. Program, Erase Times and Program/E rase Endu ranc e Cycles . . . . . . . . . . . . . . . . 26
FLASH BLOCK LOCKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Lock-Down State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Locking Operatio n s Durin g Erase Su sp e nd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 15. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 16. Protection Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
M36W216TI, M36W216BI
4/62
FLASH STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Erase Status (Bit 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
V
PP
Status (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Program Suspend Status (Bit 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Reserved (Bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0
Table 17. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 12. Flash Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18. Flash Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 13. Flash Write AC Wavefo r ms, Write Enable Control l e d . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19. Flash Write AC Chara cte ristics, Write En a ble Controlled. . . . . . . . . . . . . . . . . . . . . 33
Figure 14. Flash Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 20. Flash Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . 35
Figu r e 1 5 . Flash Power -Up an d R e set AC W a veforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 21. Flash Power-Up and Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7
SRAM SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 16. SRAM Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
SRAM OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8
Figure 17. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V
IL
. . . 39
Figure 18. SRAM Read AC Waveforms, GS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 19. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 22. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 20. SRAM Write AC Waveforms, WS Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figu r e 2 1 . SRAM Write A C Wav e forms, E1S Con trolle d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 22. SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . 43
Figure 23. SRAM Write Cycle Waveform, UBS and LBS Controlled, GS Low . . . . . . . . . . . . . 43
Table 23. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 24. SRAM Low V
DDS
Data Retention AC Waveforms, E1S or UBS / LBS Controlled . . 45
Table 24. SRAM Low V
DDS
Data Retention Characte r i stic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 25. Top Boot Block Addresses, M36W216TI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 26. Botto m Boo t Bl oc k Addre sse s, M36W216BI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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M36W216TI, M36W216BI
APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 27. Query Stru cture Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 28. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 29. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 30. Device Geome try Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 31. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 32. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 25. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 26. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 27. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 54
Figure 28. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 29. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 30. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE . . . . . . . 59
Table 33. Write State Machine Current/Next, sheet 1 of 2.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 34. Write State Machine Current/Next, sheet 2 of 2.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 35. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
M36W216TI, M36W216BI
6/62
SUMMARY DESCRIPTION
The M36W216TI is a low voltage Multiple Memory
Product which combines two memory devices; a
16 Mbit boot block Flash memory and a 2 Mbit
SRAM. Recommended operating conditions do
not allow both the F lash memory and the S RAM
memory to be active at the same time.
The memory is offered in a Stacked LFBGA66
(12x8mm, 8 x 8 active ball, 0.8 mm pitch) package
and is supplied with all the bits erased (set to ‘1’).
Figure 2. Logic Diagram
Table 1. Signal Names
AI07903
20
A0-A19
E
F
DQ0-DQ15
V
DDF
M36W216TI
M36W216BI
G
F
V
SSF
16
W
F
RP
F
WP
F
V
DDQF
E1
S
G
S
W
S
UB
S
LB
S
V
SSS
V
PPF
V
DDS
E2
S
A0-A16 Flash and SRAM Address Inputs
A17-A19 Address Inputs for Flash Chip only
DQ0-DQ15 Data Input/Output
V
DDF
Flash Power Supply
V
DDQF
Flash Power Supply for I/O Buffers
V
PPF
Flash Optional Supply V oltage for Fast
Program & Erase
V
SSF
Flash Ground
V
DDS
SRAM Power Supply
V
SSS
SRAM Ground
NC Not Connected Internally
Flash control functions
E
F
Chip Enable input
G
F
Output Enable input
W
F
Write Enable input
RP
F
Reset input
WP
F
Write Protect input
SRAM control functions
E1
S
, E2
S
Chip Enable inputs
G
S
Output Enable input
W
S
Write Enable input
UB
S
Upper Byte Enable input
LB
S
Lower Byte Enable input
7/62
M36W216TI, M36W216BI
Figure 3. LFBGA Connections (Top view through package)
AI90254
A
654321#2#1
E
B
F
A12
A13A11NCNC
NC
E2SDQ12V
SSS
A2A3A6A7A18
EFA0A4NCNC
DQ4
WS
DQ15A9A16
DQ6DQ13NCWF
A8 A10
A5
NC V
SSF
A17
RPF
A15 A14
NCNC
V
DDF
E1SA1
NCNCGF
V
DDS
DQ7
DQ5
DQ14
NC
V
SSF
V
DDQF
#4#387
C
DQ10
DQ11A19WPF
V
PPF
DQ3DQ2
D
DQ8DQ9GSLBS
UBS
DQ1DQ0
G
H
M36W216TI, M36W216BI
8/62
SIGNAL DESCRIPTION
See Figure 2 Logic Diagram and Table 1, Sign al
Names, for a brief overview of the signals connected to this de vice.
Address Inputs (A0-A16). Addresses A0-A16
are common inputs for the Flash an d the SRAM
components. The Address Inputs select the cells
in the memory array to access during Bu s Read
operations. During Bus Write operations they control the commands sent to the Command Interface
of the internal state machine. The Flash memory is
accessed through the Chip Enable (
E
F
) and Write
Enable (W
F
) signals, while the SRAM i s acce sse d
through two Chip Enable ( ES
) and Write Enable
(W
S
) signals.
Address Inputs (A17-A19). Addresses A17-A19
are inputs for the Flash component only. The
Flash memory is acc essed through the Chip E nable (
E
F
) and Write Enable (WF) signals
Data Inputs/Outputs (DQ0-DQ15). The Data I/
O output the d ata stored at the selected addres s
during a Bus Read operation or in put a c om m and
or the data to be programmed durin g a Write Bus
operation.
Flash Chip Enable (
E
F
). The Chip Enable input
activates the Flash memory control logic, input
buffers, decoders and sense amplifiers. When
Chip Enable is at V
IL
and Reset is at VIH the device
is in active mode. When Chip Enable is at V
IH
the
memory is deselected, the outputs are high impedance and the power consumption is reduced to the
standby level.
Flash Output Enable (G
F
). The Output Enable
controls the data outputs during the Bus Read operation of the Flash memory.
Flash Write Enable (
W
F
). The Write Enable con-
trols the Bus Write operation of the Flash m emory’s Command Interface. The data and address
inputs are latched on the rising e dge of Chip Enable,
E
F
, or Write Enable, WF, whichever occurs
first .
Flash Write Protect (WP
F
). Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is at V
IL
, the
Lock-Down is enabled and the protection status of
the block cannot be changed. When Write Protect
is at V
IH
, the Lock-Down is disabled and the block
can be locked or unlocked. (refer to T able 6, Read
Protection Register and Protection Register Lock).
Flash Reset (RP
F
). The Reset input provides a
hardware reset of the Flash memory. When Reset
is at V
IL
, the memory is in reset mode: the outputs
are high impedance and the current c onsumption
is minimized. After Reset all blocks are in the
Locked state. When Reset is at V
IH
, the device is
in normal operation. Exiting reset mode the device
enters read array mode, but a negative t ransition
of Chip Enable or a change of the address is required to ensure valid data outputs.
SRAM Chip Enable (E1
S
, E2S). The Chip En-
able inputs activate the SRAM memory control
logic, input buffers and decoders. E1
S
at VIH or
E2
S
at VIL deselects the memory and reduces the
power consumption to the standby level. E1
S
or
E2
S
can also be used to control writing to the
SRAM memory array, while W
S
rema in s at V
IL.
It
is not allowed to set
E
F
at VIL and, E1S at VIL or
E2
S
at VIL at the same time.
SRAM Write Enable (W
S
). The Write Enable in-
put controls writing to the SRA M memory array.
W
S
is active low .
SRAM Output E nable (G
S
). The Output Enable
gates the outputs through the data buffers during
a read operation of the SRAM m emory. G
S
is ac-
tive low.
SRAM Upper Byte Enable (UB
S
). The Upper
Byte Enable enables the upper bytes for SRAM
(DQ8-DQ15). UB
S
is acti v e low.
SRAM Lower Byte Enable (LB
S
). The Lower
Byte Enable enables the lower bytes for SRAM
(DQ0-DQ7). LB
S
is active low.
V
DDF
and V
DDS
Supply Voltages. V
DDF
provides the power supply to the internal core of the
Flash Memory device. It is the main power s upply
for all operations (Read, Program and Erase).
V
DDQF
and V
DDS
Supply Voltage (2.7V to 3.3V).
V
DDQF
provides the power supply for the Flash
memory I/O pins and V
DDS
provides the power
supply for t he SRAM control pins. This a llows all
Outputs to be powered independently of the Flash
core power supply, V
DDF
. V
DDQF
can be tied to
V
DDS.
V
PPF
Program Supp ly Vol tage. V
PPF
is both a
control input and a power suppl y pin for t he F lash
memory. The two functions are selected by the
voltage range applied to the pin. The Supply Voltage V
DDF
and the Program Supply Vol tage V
PPF
can be applied in any order.
If V
PPF
is kept in a low voltage range (0V t o 3.6V)
V
PPF
is seen as a control input. In this case a volt-
age lower than V
PPLK
gives an absolute protection
against program or erase, while V
PPF
> V
PP1
enables these functions (see Table 6, DC Characteristics for the relevant values). V
PPF
is only
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect and program or erase operations continue.
If V
PPF
is in the range 11.4V to 12.6V it acts as a
power supply pin. In this condition V
PPF
must be
stable until the Program/Erase algorithm i s completed (see Table 19 and 20).
9/62
M36W216TI, M36W216BI
V
SSF
and V
SSS
Ground. V
SSF
and V
SSS
are the
ground reference for all voltage measurements in
the Flash and SRAM chips, respectively.
Note: Each device in a system should have V
D-
DF
, V
DDQF
and V
PPF
decoupled with a 0.1µF ca-
pacitor close to the pin. See Figure 9, AC
Measurement Load Circuit. The PCB trace
widths should be sufficient to carry the required V
PPF
program and erase currents.
FUNCTIONAL DESCRIPTION
The Flash and SRAM components have separate
power supplies and grounds and are distinguished
by three chip enable inputs:
E
F
for the Flash mem-
ory and E1
S
and E2S for the SRAM.
Recommended operating conditions do not allow
both the Flash and the SRAM to be in active mode
at the same time. The most common example is
simultaneous read operations on the Flash and
the SRAM which would resul t in a data bus contention. Therefore it is recommended to put the
SRAM in the h igh impedance state whe n reading
the Flash and vice versa (see Table 2 Main Operation Modes for details).
Figure 4. Func ti onal Block Di a gram
AI07904
Flash Memory
16 Mbit (x16)
V
SSF
E
F
G
F
W
F
RP
F
WP
F
E1
S
G
S
W
S
UB
S
LB
S
DQ0-DQ15
V
DDF
V
PPF
A17-A19
A0-A16
SRAM
2 Mbit (x16)
V
SSS
V
DDS
V
DDQF
E2
S
M36W216TI, M36W216BI
10/62
Table 2. Main Operation Modes
Note: X = Don’t care = VIL or VIH, V
PPFH
= 12V ± 5%.
Operation
Mode
E
FGFWF
RPFWP
F
V
PPF
E1SE2SGSWSUBSLB
S
DQ7-DQ0 DQ15-DQ8
Flash Memory
Read
V
ILVILVIHVIH
X Don’t care SRAM must be disabled Data Output
Write
V
ILVIHVILVIH
X
V
DDF
or
V
PPFH
SRAM must be disabled Data Input
Block
Locking
V
IL
XX
V
IH
V
IL
Don’t care SRAM must be disabled X
Standby
V
IH
XX
V
IH
X Don’t care Any SRAM mode is allowed Hi-Z
Reset X X X
V
IL
X Don’t care Any SRAM mode is allowed Hi-Z
Output
Disable
V
ILVIHVIHVIH
X Don’t care Any SRAM mode is allowed Hi-Z
SRAM
Read
Flash must be disabled
V
ILVIHVILVIHVIL
V
IL
Data out Word Read
Flash must be disabled
V
ILVIHVILVIHVIHVIL
Data out Hi-Z
Flash must be disabled
V
ILVIHVILVIHVIL
V
IH
Hi-Z Data out
Write
Flash must be disabled
V
ILVIH
XVILV
IL
V
IL
Data in Word Write
Flash must be disabled
V
ILVIH
XVILV
IHVIL
Data in Hi-Z
Flash must be disabled
V
ILVIH
XVILV
IL
V
IH
Hi-Z Data in
Standby/
Power
Down
Any Flash mode is allowable
V
IHVIL
X X X X Hi-Z
XXXX
V
IHVIH
Hi-Z
Data
Retention
Any Flash mode is allowable
V
IHVIL
X X X X Hi-Z
XXXX
V
IHVIH
Hi-Z
Output
Disable
Any Flash mode is allowable
V
ILVIHVIHVIHVIL
V
IL
Hi-Z
Any Flash mode is allowable
V
ILVIHVIHVIHVIHVIL
Hi-Z
Any Flash mode is allowable
V
ILVIHVIHVIHVIL
V
IH
Hi-Z
11/62
M36W216TI, M36W216BI
MAXIMUM RATIN G
Stressing the device above the rating l isted in the
Absolute Maximum Ratings table m ay cause permanent damage to the device. These are stress
ratings only and operation of the device at t hese or
any other conditions ab ove those i ndicated in t he
Operating sections of this specificat ion is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 3. Absolute Maximum Ratings
Note: 1. Depends on range.
Symbol Parameter
Value
Unit
Min Max
T
A
Ambient Operating Temperature
(1)
–40 85 °C
T
BIAS
Temperature Under Bias –40 125 °C
T
STG
Storage Temperature –55 150 °C
V
IO
Input or Output Voltage –0.5
V
DDQF
+0.5
V
V
DDF
, V
DDQF
Flash Supply Voltage –0.5 3.8 V
V
PPF
Program Voltage –0.6 13 V
V
DDS
SRAM Supply Voltage –0.5 3.8 V
M36W216TI, M36W216BI
12/62
DC AND AC PARAMETERS
This section summarizes the operat ing and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are derived from tests performed under the Measure-
ment Conditions summarized in Table 4,
Operating and AC Measurem ent Conditions. Designers should check that the operating conditions
in their circuit match the measurement conditions
when relying on the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Figure 5. AC Measurement I/O Waveform
Note: V
DDQ
means V
DDQF
= V
DDS
Figure 6. AC Me asureme nt Load Circuit
Table 5. Device Capacitance
Note: Sampled o nl y, not 100% test ed.
Parameter
SRAM Flash Memory
Units70 70/85
Min Max Min Max
V
DDF
Supply Voltage
– – 2.7 3.3 V
V
DDQF
Supply Voltage
– – 2.7 3.3 V
V
DDS
Supply Voltage
2.7 3.3 – – V
Ambient Operating Temperature – 40 85 – 40 85 °C
Load Capacitance (C
L
)
30 50 pF
Input Rise and Fall Times 1V/ns 5ns
Input Pulse Voltages
0 to V
DDQF
0 to V
DDQF
V
Input and Output Timing Ref. Voltages
V
DDQF
/2 V
DDQF
/2
V
AI90258
V
DDQ
0V
V
DDQ
/2
AI90259
V
DDQF
C
L
CL includes JIG capacitance
25kΩ
DEVICE
UNDER
TEST
0.1µF
V
DDF
0.1µF
V
DDQF
25kΩ
Symbol Parameter Test Condition Typ Max Unit
C
IN
Input Capacitance
V
IN
= 0V, f=1 MHz
12 pF
C
OUT
Output Capacitance
V
OUT
= 0V, f=1 MHz
15 pF
13/62
M36W216TI, M36W216BI
Table 6. DC Characteristics
Symbol Parameter Device Test Condition Min Typ Max Unit
I
LI
Input Leakage Current Flash & SRAM
0V≤ V
IN
≤
V
DDQF
±1 µA
I
LO
Output Leakage Current
Flash
0V ≤V
OUT
≤
V
DDQF
±10 µA
SRAM
0V ≤V
OUT
≤
V
DDQF,
SRAM Outputs Hi-Z
±1 µA
I
DDSVDD
Standby Current
Flash
E
F
= V
DDQF
± 0.2V
RP
F
= V
DDQ
± 0.2V
15 50 µA
SRAM
E1
S
≥
V
DDS
– 0.2V
V
IN
≥
V
DDS
−
0.2V or V
IN
≤
0.2V
515µA
I
DDD
Supply Current (Reset) Flash
RP
F
= V
SSF
± 0.2V
15 50 µA
I
DD
Supply Current SRAM
V
DDS
= 3.3V
,
I
OUT
= 0 mA, f = 1MHz
1.5 3 mA
V
DDS
= 3.3V
,
I
OUT
= 0 mA, f = f
MAX
= 1/t
AVAV
715mA
I
DDR
Supply Current (Read) Flash
E
F
= VIL, G
F
=
V
IH,
f = 5 MHz
10 20 mA
I
DDW
Supply Current
(Program)
Flash
Program in progress
V
PPF
= 12V ± 5%
10 20 mA
Program in progress
V
PPF
= V
DDF
10 20 mA
I
DDE
Supply Current (Erase) Flash
Erase in progress
V
PPF
= 12V ± 5%
520mA
Erase in progress
V
PPF
= V
DDF
520mA
I
DDES
Supply Current
(Program/Erase
Suspend)
Flash
E
F
= V
DDQF
± 0.2V,
Erase suspended
50 µA
I
PP1
Program Current
(Read or Standby)
Flash
V
PPF
> V
DDF
400 µA
I
PP2
Program Current
(Read or Standby)
Flash
V
PPF
≤
V
DDF
5µA
I
PPR
Program Current (Reset) Flash
RP
F
= V
SSF
± 0.2V
5µA
I
PPW
Program Current
(Program)
Flash
V
PPF
= 12V ± 0.5V
Program in progress
10 mA
V
PPF
= V
DDF
Program in progress
5mA
I
PPE
Program Current (Erase) Flash
V
PPF
= 12V ± 0.5V
Erase in progress
10 mA
V
PPF
= V
DDF
Erase in progress
5µA
V
IL
Input Low Voltage Flash & SRAM
V
DDQF
= V
DDS
≥
2.7V
–0.3 0.6 V
V
IH
Input High Voltage Flash & SRAM
V
DDQF
= V
DDS
≥
2.7V 0.7V
DDQF
V
DDQF
+0.3
V
M36W216TI, M36W216BI
14/62
V
OL
Output Low Voltage Flash & SRAM
V
DDQF
= V
DDS
= VDDmin
I
OL
= 100µA
0.1 V
V
OH
Output High Voltage Flash & SRAM
V
DDQF
= V
DDS
= VDDmin
I
OH
= –100µA
V
DDQ
–0.1
V
V
PP1
Program Voltage
(Program or Erase
operations)
Flash 1.65 3.6 V
V
PPFH
Program Voltage
(Program or Erase
operations)
Flash 11.4 12.6 V
V
PPLK
Program Voltage
(Program and Erase
lock-out)
Flash 1 V
V
LKO
V
DDF
Supply Voltage
(Program and Erase
lock-out)
Flash 2 V
Symbol Parameter Device Test Condition Min Typ Max Unit
15/62
M36W216TI, M36W216BI
PACKAGE MECHANICAL
Figure 7. Stacked LFBGA66-12x8mm, 8x8 ball arra y, 0.8mm pitch, Bottom View Package Outline
Note: Drawing is not to scale.
Table 7. Stacked LFBGA66 - 12x8mm, 8x8 ball array, 0.8 mm pitch, Pack age Mechanical Data
Symbol
millimeters inches
Typ Min Max Typ Min Max
A 1.400 0.0551
A1 0.300 0.0118
A2 1.100 0.0433
b 0.400 0.300 0.500 0.0157 0.0118 0.0197
D 12.000 – – 0.47 24 – –
D1 5.600 – – 0.22 05 – –
D2 8.800 – – 0.34 65 – –
ddd 0.100 0.0039
E 8.000 – – 0.31 50 – –
E1 5.600 – – 0.2205 – –
e 0.800 – – 0.03 15 – –
FD 1.600 – – 0.0630 – –
FE 1.200 – – 0.04 72 – –
SD 0 .400 – – 0.0157 – –
SE 0.400 – – 0.0157 – –
A2
A1
A
BGA-Z12
ddd
D
E
e
b
SE
FDFE
E1
e
D1
SD
D2
BALL "A1"
M36W216TI, M36W216BI
16/62
Figure 8. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package)
AI90273
D
C
#4#3
8761
E
F
A
B
H
G
5
4
32#1 #2
17/62
M36W216TI, M36W216BI
Figure 9. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)
#1
AI90274
D
C
E
F
A
B
H
G
START
POINT
END
POINT
#4#3
87615
4
32#2
M36W216TI, M36W216BI
18/62
PART NUMBERING
Table 8. Ordering Information Scheme
Devices are shipped from the factory with the memory content bits erased to ’1’.
Table 9. Daisy Chain Ordering Scheme
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
Example: M36W216 T I 85 ZA 6 T
Device Type
M36 = MMP (Flash + SRAM)
Operating Voltage
W = V
DDF
= 2.7V to 3.3V, V
DDS
= V
DDQF
= 2.7V to 3.3V
SRAM Chip Size & Organization
2 = 2 Mbit (128K x 16 bit)
Device Function
16 = 16 Mbit (x16), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
SRAM Component
I = 2Mb, 0.16µm, 70ns, 3V
Speed
70 = 70ns
85 = 85ns
Package
ZA = LFBGA66: 12x8mm, 0.8mm pitch
Temperature Range
1 = 0 to 70°C
6 = –40 to 85°C
Option
T = Tape & Reel packing
Example: M36W216TI -ZA T
Device Type
M36W216TI
Daisy Chain
-ZA = LFBGA66: 0.8mm pitch
Option
T = Tape & Reel Packing
19/62
M36W216TI, M36W216BI
FLASH DEVICE
The M36W216TI contains one 16 Mbit Flash
memory. This section describes how to use the
Flash device and all signals refer to the Flash device .
FLASH SUMMARY DESCRIPTION
The Flash Memory is a 16 Mb it (1 Mb it x 16) nonvolatile device that can be erased electrically at
the block level and prog rammed in-system on a
Word-by-Word basis. These operations can be
performed using a single low voltage (2.7 to 3.6V)
supply. V
DDQF
is used to drive the I/O pin down to
1.65V. An optional 12V V
PPF
power supply is pro-
vided to speed up customer programming.
The device features an asymmetrical blocked ar-
chitecture with an array of 39 blocks: 8 Parameter
Blocks of 4 KWords and 31 Main Blocks of 32
KWords. The M36W216TI has the Parameter
Blocks at the top of the memory address space
while the M36W216BI locates the Parameter
Blocks starting from the bottom. The memory
maps are shown in Figure 10, Block Addresses.
The Flash Memory features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling instant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any accidental programming or erasure. There is an additional
hardware protection against program and erase.
When V
PPF
≤ V
PPLK
all blocks are protected
against program or erase. All blocks are locked at
Power Up.
Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be suspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
The device includes a 128 b it Protection Register
and a Security Block to increase the protection of
a system design. The Protection Register is divided into two 64 bit segments, the first one contains
a unique device number written by ST, while the
second one is one-time-programmable by the user. The user programmable segm ent can be permanently protected. The Security Block,
parameter block 0, can be permanentl y protected
by the user. Figure 11, shows the Flash Security
Block Memory Map.
Program and Erase command s are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the timings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
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