SGS Thomson Microelectronics M34D64-W Datasheet

M34D64

64 Kbit Serial I²C Bus EEPROM

With Hardware Write Control on Top Quarter of Memory

FEATURES SUMMARY

■ Two Wire I

C Serial Interface

Supports 400 kHz Protocol

■ Single Supply Voltage:

– 2.5V to 5.5V for M34D64-W – 1.8V to 5.5V for M34D64-R

■ Hardware Write Control of the top quarter of

memory

■ BYTE and PAGE WRITE (up to 32 Bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Tim e d P rogramming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behavior

■ More than 1M Erase/Write Cycles

■ More than 40 Year Data Retention

Figure 1. Packages

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

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M34D64

SUMMARY DESCRIPTION

These I

C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 8192 x 8.

Figure 2. Logic Diagram

E0-E2 SDA

SCL

M34D64

AI02850B

Table 1. Signal Names

E0, E1, E2 Chip Enable SDA Serial Data SCL Serial Clock WC V

Power On Reset: V

Write Control Supply Voltage Ground

Lock-Out Write Protect

In order to prevent data corruption and inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. The internal reset is held active until V

has reached the POR

threshold value, and all operations are disabled – the device will not respond to any command. In the same way, when V

drops from the operating

voltage, below the POR threshold value, all operations are disabled and the device will not respond to any com ma nd. A s table a nd v alid V

must be applied before applying any logic signal.

These devices are compatible with the I

memory protocol. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I

bus definition. The device behaves as a slave in the I

C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select Code and RW

bit (as described in Table 2),

terminated by an acknowledge bit. When writing data to the memory, the device

inserts an acknowledge bit during the 9

bit time,

following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

Figure 3. SO and TSSOP Connections

M34D64

E0 V

2 3

Note: 1. See page 17 (onwards) for package dimensions, and how

to identify pin-1.

8 7 6 5

AI02851C

WCE1 SCL SDAV

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SIGNAL DESCRIPTION Serial Clock (SCL)

This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to V

. (Figure 5

indicates how the value of the pull-up resist or can be calculated). In most applications, thoug h, this method of synchronization is no t employed, and so the pull-up resistor is not necessary, provided that the bus maste r has a push-pull (rather than open drain) output.

Serial Data (SDA)

This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that

may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to V

. (Figure 5 indicates how the value of the pull-up resistor can be calculated).

Chip Enable (E0, E1, E2)

These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to V

or VSS, to establish the

Device Select Code.

Write Control (WC

The hardware Write Control pin (WC

)

) is useful for protecting the top quarter of the memory (as shown in Figure 4) from inadvertent erase or write. The Write Control signal is used to enable

M34D64

(WC

=VIL) or disable (WC=VIH) write instructions to the top quarter of the memory area. When unconnected, the WC write operations are allowed.

Figure 4. Me m ory Map showing Write Cont rol Area

input is internally read as VIL, and

1FFFh

Write Controlled

Area

1800h

1000h

0800h

0000h

AI03114C

Figure 5. Maximum R

Maximum RP value (kΩ)

10 1000

Value versus Bus Capacitance (C

fc = 100kHz

fc = 400kHz

100

(pF)

BUS

) for an I2C Bus

BUS

MASTER

SDA

SCL

BUS

AI01665

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M34D64

Figure 6. I2C Bus Protocol

SCL

SDA

SCL

SDA

SCL

SDA

START

Condition

START

Condition

1 23 789

MSB

1 23 789

MSB ACK

SDA

Input

SDA

Change

STOP

Condition

ACK

STOP

Condition

AI00792B

Table 2. Device Select Code

Device Type Identifier

Chip Enable Address

b7 b6 b5 b4 b3 b2 b1 b0

Device Select Code 1 0 1 0 E2 E1 E0 RW

Note: 1. The most si gnifican t bit, b7, is se nt first.

2. E0 , E 1 and E2 are compared agai nst the respective external pins on the memory device.

Table 3. Most Significant Byte Table 4. Least Significant Byte

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

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M34D64

DEVICE OPERATION

The device supports the I

C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitte r, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M34D64 device is always a slave in all communication.

Start Condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The devi ce continuously monitors (except duri ng a Write cycle ) Se ri a l Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is give n.

Stop Condition

Stop is identified by a rising edg e of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EEPRO M Writ e cycle.

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9

clock pulse period, the receiver pulls

Serial Data (SDA) Low to acknowledge the receipt of the eight data bits.

Data Input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal

only

must change

when Serial Clock (SCL) is

driven Low.

Memory Addressing

To start communication betwee n the bus master and the slave device, the bus mas ter mus t initiate a Start condition. Following this, t he bus master sends the Device Select Code, shown in Tabl e 2 (on Serial Data (SDA), most significant bit first).

The Device Select Code consists of a 4-bit Device

Type Identifier, and a 3-bit Chip Enable “Address” (E2, E1, E0). To address the memory array, t he 4bit Device Type Identifier is 1010b.

Up to eight memory devices can be connected on a single I

C bus. Each one is given a uniq ue 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is received on Serial Data (SDA), the device only responds if the Chip Enable Address is the s ame as the v alue on the Chip Enable (E0, E1, E2) inputs.

The 8

bit is the Read/Write bit (RW). This bi t is

set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code , the

corresponding device gives an acknowledgment on Serial Data (SDA) during the 9

bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Standby mode.

Table 5. Operating Modes

Mode RW bit

Current Address Read 1 X 1 START, Device Select, RW

Random Address Read

Sequential Read 1 X Byte Write 0 V Page Write 0 V

Note: 1. X = V

or V

0X 1 X reSTART, Device Select, RW

Bytes Initial Sequence

1 Similar to Current or Random Address Read

≥

1 START, Device Select, RW = 0

32 START, Device Select, RW

≤

START, Device Select, RW

= 1 = 0, Address

= 1

= 0

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M34D64

Figure 7. Wri te Mo de S e qu e nces with WC =0 (data wri te enab led)

ACK

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

R/W

START

ACK ACK ACK ACK

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

R/W

START

WC (cont'd)

ACKACK

PAGE WRITE (cont'd)

DATA IN N

ACK ACK ACK

STOP

DATA IN 2

Write Operations

Following a Start condition the bus master sends a Device Select Code with the RW

bit rese t to 0 . The device acknowledges this, as shown in Figure 7, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte(s).

Writing to the memory may be inhibited if Write Control (WC with Write Control (WC

) is driven High. Any Write instruction

) driven High (during a period of time from the Start condition until the end of the two address bytes) will not modify the contents of the top quarter of the memory.

Each data byte in the m emory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 3) is sent first, followed by the Least Significant Byte (Table 4). Bits b15 to b0 form t he add ress of the byte in memory.

When the bus mast er generates a Stop con dition

immediately after the Ack bi t (in t he “10

bit” time

slot), either at the end of a Byte Write or a Page

STOP

AI01106C

Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.

During the internal Write cycle, Serial Da ta (SDA) is disabled internally, and the devi ce does not respond to any requests.

Byte Write

After the Device Select code and the address bytes, the bus master sends one dat a byte. If the addressed location is Write-protected (top quarter of the memory), by Write Control (WC

) being driven High, the location is not modified. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 7.

Page Write

The Page Write mode allows u p to 32 by tes to be written in a single Write cycle, provided that they are all located in the same ’row’ in the memory: that is, the most significant m emory address bits (b12-b5) are the same. If more bytes are sent than will fit up to t he en d of t he row, a condition known as ‘roll-over’ occurs. This should be avoided, as

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M34D64

data starts to become overwritten in an implementation dependent way.

The bus master sends fr om 1 to 32 bytes of data. If Write Control (WC

) is High, the contents of the

addressed top quarter of the m emo ry locatio n are

Figure 8. W ri t e C yc le Pol l in g Fl owchart usin g A C K

WRITE Cycle

in Progress

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

First byte of instruction with RW = 0 already decoded by the device

ReSTART

YES

Operation is

Addressing the

Memory

not modified. After each byte is transferred, the internal byte address counter (the 5 least significant address bits only) is incremented. Th e transfer is terminated by the bus master generating a Stop condition.

YESNO

Send Address

and Receive ACK

STOP

DATA for the

WRITE Operation

Continue the

WRITE Operation

Minimizing System Delays by Polling On ACK

During the internal Write cycle, the device disconnects itself from t he bus , and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (t

) is shown in

Tables 13 and 14, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master.

The sequence, as shown in Figure 8, is:

– Initial condition: a Write cycle is in progress.

START

Condition

YESNO

DEVICE SELECT

with RW = 1

Continue the

Random READ Operation

AI01847C

– Step 1: the bus master issues a Start condition

followed by a Device Select Code (the first byte of the new instruction).

– Step 2: if the device is busy with the internal

Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).

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