SGS Thomson Microelectronics M34C00-WMN6T, M34C00-WDW6T Datasheet

M34C00

3 x 128 bit Serial I²C Bus EEPROM

For ee-Tags

PRELIMINARY DATA

■ Two-Wire I

C Serial Interface

Supports 400 kHz Protocol

■ 2.5 V to 5.5 V Single Supply Voltage

■ 384-bit EEPROM divided in three areas:

– 128 bits of non-erasable memory – 128 bits of standard EEPROM – 128 bits that can be permanently Write-

protected (to behave as ROM)

■ Self-Tim e d P rogram Cyc le

■ Enhanced ESD/Latch-Up Protection

■ More than 1 Million Erase/Write Cycles

■ More than 40 Year Data Retention

DESCRIPTION

The M34C00 is a 384-bit serial EEPROM. The bottom third of the memory area (from location 00h to 0Fh) can be Write-protected using a specially designed software Write-protection mechanism. By sending the device a specific sequence, the first 128 bits of the memory become permanently Write-protected. Care must be taken when using this sequence as its effect cannot be reversed.

The top third of the mem ory area (from location 20h to 2Fh) is already configured to give the functional equivalence of a non-erasable memory. That is, it is initialized to all 1s (FFh), and the user is able to reset any number of those 1s to 0; but there is no mechanism for the user to set a 0 back to a 1.

The M34C00 is a 384-bit electrically erasable programmable memory (EEPROM), organized as 48 x 8 bits.

SO8 (MN)

150 mil width

Figure 1. Logic Diagram

SCL

M34C00

TSSOP8 (DW)

169 mil width

SDA

Table 1. Signal Names

SDA Serial Data SCL Serial Clock V

August 2001

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Supply Voltage Ground

AI03394

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M34C00

Figure 2A. SO and TSSOP Connections

When data is read by the bus master, the bus master acknowledges the receipt of t he data b yte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a

M34C00

NC V

1 2

3 4

8 7 6 5

AI03395B

NCNC SCL SDAV

NoAck for Read.

Power On Reset: V

Lock-Out Write Protect

In order to prevent data corruption and inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. The internal reset is held active until V

has reached the POR

threshold value, and all operations are disabled – the device will not respond to any command. In the same way, when V

drops from the operating

voltage, below the POR threshold value, all operations are disabled and the device will not

Note: 1. NC = Not Connected

respond to any com ma nd. A s table a nd v alid V

must be applied before applying any logic signal.

These devices are compatible with the I memory standard. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The device carries a built-in 4-bit Device Type Identifier code (1010) in accordance with the I

C bus definition to access the memory area and a second Device Type Identifier code (0110) to access the Protection Register.

The device behaves as a slave in the I

C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select code and RW

bit (as described in Table 3),

terminated by an acknowledge bit. When writing data to the memory, the device

inserts an acknowledge bit during the 9

bit time,

following the bus master’s 8-bit transmission.

SIGNAL DESCRIPTION Serial Clock (SCL)

This signal is used to strobe all data in and out of the device. In appli cations where this line is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to V 3 indicates how t he value of the pull-up resistor can be calculated). In most applications, t hough, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.

Serial Data (SDA)

This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that

. (Figure

may be wire-OR’ed with other open drain or open

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

STG

LEAD

ESD

Note: 1. Except for the rating “Operating Temperature Ra nge”, stresses above those li sted in t he Table “Absolute M aximum Ratings” may

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indi cated in t he Operating sect i ons of thi s specifi cation i s not impl i ed. Exposure to Absolute M aximum Rating c onditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. IPC/JEDEC J- S T D- 020A

3. JEDEC Std JESD22-A 114A (C1=1 00 pF, R1=1500 Ω, R2=500 Ω)

Ambient Operating Temperature –40 to 85 °C Storage Temperature –65 to 150 °C

Lead Temperature during Soldering

Input or Output range –0.6 to 6.5 V Supply Voltage –0.3 to 6.5 V

Electrostatic Discharge Voltage (Human Body model)

SOT23: t.b.d. SO: 20 seconds (max) TSSOP: 20 seconds (max)

t.b.d.

235 235

4000 V

°C

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M34C00

Figure 3. Maximum RL Value versus Bus Capacitance (C

Maximum RP value (kΩ)

10 1000

BUS

fc = 400kHz

100

(pF)

collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to V (Figure 3 indicates how the value of the pull-up resistor can be calculated).

fc = 100kHz

Stop Condition

Stop is identified by a rising edg e of Serial Data (SDA) while Serial Clock (SCL) is stable, and driven High. A Stop condition terminates communication between the device and the bus

DEVICE OPERATION

The device supports the I

C protocol. This is summarized in Figure 4. Any device that sends data on to the bus is defined to be a transmitte r, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M34C00 device is always a slave in all communication.

Start Condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The devi ce continuously monitors (except during a programming cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not re sp ond unless one is

master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EEPRO M Writ e cycle.

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9 Serial Data (SDA) Low to acknowledge the receipt of the eight data bits.

Data Input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the data on Serial Data (SDA)

given.

) for an I2C Bus

BUS

MASTER

clock pulse period, the receiver pulls

SDA

SCL

BUS

AI01665

Table 3. Device Select Code

Device Type Identifier

b7 b6 b5 b4 b3 b2 b1 b0 Memory Area Select Code (three arrays) 1 0 10111RW Protection Register Select Code 0 1 10111RW

Note: 1. The most signi ficant bit (b7) is sent fir st .

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M34C00

Figure 4. I2C Bus Protocol

SCL

SDA

SCL

SDA

SCL

SDA

START

Condition

START

Condition

1 23 789

MSB

1 23 789

MSB ACK

SDA Input

SDA

Change

STOP

Condition

ACK

STOP

Condition

AI00792B

must change

only

when Serial Clock (SCL) is

driven Low.

Memory Addressing

To start communication betwee n the bus master and the slave device, the bus mas ter mus t initiate a Start condition. Following this, t he bus master sends the 8-bit byte, shown in Table 3, on Serial Data (SDA) (most significant bit first). This consists of the 7-bit Device Select code, and the Read/Write

bit (RW).

To address the memory array, the 4-bit Device Type Identifier is 1010b. To address the Protection Register, it is 0110b, as shown in Table 3.

The 8

bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9

bit time. If the

device does not match the Device Select code, it

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deselects itself from the bus, and goes into Standby mode.

Memory Partition in g

The memory is divided in three arrays:

■ Array-0: Write-protectable Array (00h to 0Fh)

■ Array-1: EEPROM Array (10h to 1Fh)

■ Array-2: Non-Erasable Memory Array (20h to

2Fh)

The 4 least significant bits of the address byte determine the byte that is to be addressed within the given array. The next 2 more significant address bits determine the array that is to be addressed (Array-0, Array-1, Array-2 or Invalid).

The 2 most significant address bits are Don’t Care. If the address is of the form xx11xxxx, the device

recognises that an attempt is being made to

Figure 5. Me m ory P a rti tioning

M34C00

Array 2

Array 1

Array 0

Default EEPROM memory area state before write access to the Protection Register

EPROM

Array

Standard

Array

Standard

Array

2Fh

20h 1Fh

10h 0Fh

00h

address the Invalid array, and immediately deselects itself.

The Write-protectable array consists of 16 bytes of EEPROM, which can be used as normal EEPROM until this array is set in its Write-protected mode. Once Write-protected, this array becomes functionally equivalent to a Read-Only Memory (ROM), and cannot be modified further. The procedure to set this array in its Write-protected mode is described later.

Array-2 also consists of 16 bytes of EEPROM, but configured to give the functional equivalence of non-erasable memory. That is, it is initialized to contain all 1s (FFh), with the user able to reset any 1 to a 0, but unable to set any 0 to a 1. One application envisaged for this array is as a nonresettable 128-token array.

WRITE AND READ OPERATIONS Write Operations

Following a Start condition the bus master sends a Device Select code with the R W

bit reset to 0. The device acknowledges this, as shown in Figure 6, and waits for an address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte.

Byte Write

After the Device Select code and the address byte, the bus master sends one data byte. If the addressed location is in the Write-protected area,

Array 2

Array 1

Array 0

EPROM

Array

Standard

Array

Write

Protected

Array

State of the EEPROM memory area after write access to the Protection Register

2Fh

20h 1Fh

10h 0Fh

00h

AI03396

the device replies with NoAck, and the l ocation is not modified. If, instead, the addressed location is not in a Write-protected area , t he device replies with Ack. The bus m aster terminates the tran sfer by generating a Stop condition, as shown in Figure

6. During the internal Write cycle, Serial Da ta (SDA)

is disabled internally, and the device does not respond to any requests.

Minimizing System Delays by Polling On ACK

During the internal Write cycle, the device disconnects itself from the bus, and copies the data from its internal latches to the memory cells. The ma x imum Write time (t

) is shown in Table 6,

but the typical time is shorter. To make use of this, an Ack polling sequenc e can be used by t he bus master.

The sequence, as shown in Figure 7, is:

– Initial condition: a Write cycle is in progress. – Step 1: the bus master issues a Start con dition

followed by a D evice S ele ct code (the first byte of the new instruction).

– Step 2: if the device is busy with the internal

Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the next instruction (the first byte of this instruction having been sent during Step 1).

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