SGS Thomson Microelectronics M34A02-V, M34A02 Datasheet

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PRODUCT PREVIEW

April 2001

This is preliminary information on a new product now in development. Details are subject to change without notice.

M34A02

2 Kbit Serial SMBus EEPROM for ACR Card Configuration

■ Two Wire SMBus Serial Interf a ce

■ 2.7V to 3.6V Single Supply Voltage

■ Hardware Write Control

■ BYTE and PAGE WRITE (up to 16 Bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Tim ed P ro g ra m ming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behavior

■ More than 1 Million Erase/Write Cycles

■ More than 40 Year Data Retention

DESCRIPTION

These electrically erasable programmable memory (EEPROM) devices are organized as 256x8 bits, and operate down to 2.7 V.

These devices are available in Plastic Small Outline and Thin Shrink Small Outline packages.

These devices are written by the ACR card-issuer, and then accessed in Read mode in the application, using the ACR Serial Bus protocol. This is a two wire serial interface that uses a bidirectional data bus and serial clock. The device carries a built-in 4-bit Device Type Identifier code (1011).

The device behaves as a slave i n the ACR Serial Bus protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. Th e Start con dition

Figure 1. Logic Diagram

AI03794

SDA

M34A02

SCL

E0-E2

Table 1. Signal Names

E0, E1, E2 Chip Enable SDA Serial Data SCL Serial Clock WC

Write Control

Supply Voltage

Ground

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

M34A02

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is followed by a Device Select code and RW bit (as described in Table 3), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9

bit time,

following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

Power On Reset: V

Lock-Out Write Protect

In order to prevent data corruption and inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. The internal reset is held active until V

has reached the POR

threshold value, and all operations are disabled – the device will not respond to any command. In the same way, when V

drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any com ma nd. A s table a nd v alid V

must be applied before applying any logic signal.

SIGNAL DESCRIPTION Serial Clock (SCL)

This input signal is use d to strobe all data in and out of the device. In applications where this line is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to V

. (Figure

3 indicates how t he value of the pull-up resistor

Figure 2. SO and TSSOP Connections

AI03795

2 3 4

8 7 6 5

SDAV

SCL

WCE1

E0 V

M34A02

Table 2. Absolute Maximum Ratings

Note: 1. Exc ept for the rating “Operating Temperature Ra nge”, stres ses above those listed in the Table “Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality document s.

2. IPC/ JEDEC J-STD- 020A

3. JED EC St d JESD22-A 114A (C1=1 00 pF, R1=1500 Ω, R2=500 Ω)

Symbol Parameter Value Unit

Ambient Operating Temperature –40 to 125 °C

STG

Storage Temperature –65 to 150 °C

LEAD

Lead Temperature during Soldering

SO8: 20 seconds (max)

TSSOP8: 20 seconds (max)

235 235

°C

Input or Output range –0.6 to 6.5 V

Supply Voltage –0.3 to 6.5 V

ESD

Electrostatic Discharge Voltage (Human Body model)

4000 V

Figure 3. Typical ACR Application PCB Connection (showing E2,E1,E0 address 000)

Note: 1. This arrangement on the chip enable lines allows the

application to start at ACR addres s 000h.

AI04092

E0 E1 E2 V

SCL

SDA

ACR Bus

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M34A02

can be calculated). In most applications, t hough, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.

Serial Data (SDA)

This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that

may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to V

. (Figure 3 indicates how the value of the pull-up resistor can be calculated).

Chip Enable (E0, E1, E2)

These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs should be tied t o V

or VSS, to estab lish

the Device Select Code.

Write Control (WC

)

This input signal is useful for protecting the entire contents of the memory from inadvertent erase and write operations. Write operations are disabled to the entire mem ory array when Write Control (WC

) is held High. When unconnected, the

signal is internally read as V

, and Write

operations are allowed. When Write Control (WC

) is held High, Device Select and Address bytes are acknowledged, Data bytes are

not

acknowledged.

DEVICE OPERATION

The device supports the ACR Serial Bus protocol. This is summarized in Figure 4. Any device that sends data on to the bus is defined to be a

transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data tran sfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always a slave in all communication.

Start Condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The de vice continuously monitors (except duri ng a Write cycle ) Se ri a l Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is give n.

Stop Condition

Stop is identified by a rising edg e of the SDA l ine while the clock SCL is stable in the High state. A Stop condition terminates communication between the device and the bus master. A Stop condition at the end of a Read command, provided that it is followed by NoAck, forces the device into its Stand-by mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle.

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9

clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits.

Data Input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL).

Figure 4. Maximum R

Value versus Bus Capacitance (C

BUS

) for an ACR Serial Bus

AI01665

BUS

SDA

MASTER

SCL

BUS

100

BUS

(pF)

Maximum RP value (kΩ)

10 1000

fc = 400kHz

fc = 100kHz

M34A02

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For correct device operation, Serial Data (SDA) must be stable before the rising edge of Serial Clock (SCL), and the data must change

only

after

Serial Clock (SCL) is Low.

Memory Addressing

To start communication betwee n the bus master and the slave device, the bus mas ter mus t initiate a Start condition. Following this, t he bus master sends the 8-bit byte, shown in Table 3, on Serial Data (SDA) (most significant bit first). This

consists of the 7-bit Device Select code, and the Read/Write

bit (RW).

The Device Select Code consists of a 4-bit Device

Type Identifier, and a 3-bit Chip Enable “Address” (E2, E1, E0). To address the memory array, t he 4bit Device Type Identifier is 1011b.

Up to eight memory devices can be connected on a single bus. Each one is given a unique 3-bit code on Chip Enable (E0, E1, E2). When the Device Select Code is received on Serial Data (SDA), the device only responds if the Chip Select Code is the

Figure 5. ACR Serial Bus Protocol

SCL

SDA

SCL

SDA

START

Condition

SDA Input

SDA

Change

AI00792B

STOP

Condition

1 23 789

MSB

ACK

START

Condition

SCL

1 23 789

MSB ACK

STOP

Condition

Table 3. Device Select Code

Note: 1. The most significant bit, b7, is sent firs t.

Device Type Identifier Chip Enable RW

b7 b6 b5 b4 b3 b2 b1 b0

Device Select Code 1 0 1 1 E2 E1 E0 RW

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M34A02

same as the pattern applied on Chip Enable (E0, E1, E2 ) .

The 8

bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment

on Serial Data (SDA) during the 9

bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Standby mode.

Table 4. Operating Modes

Note: 1. X = V

or V

Mode RW bit

Bytes Initial Sequence

Current Address Read 1 X 1 START, Device Select, RW

= 1

Random Address Read

START, Device Select, RW

= 0, Address

1 X reSTART, Device Select, RW

= 1

Sequential Read 1 X

≥

1 Similar to Current or Random Address Read

Byte Write 0

1 START, Device Select, RW = 0

Page Write 0

≤

16 START, Device Select, RW

= 0

Figure 6. Wri te Mo de S e qu e nces with WC =1 (data wri te inhibi ted)

STOP

START

Byte Write DEV SEL BYTE ADDR DATA IN

START

Page Write DEV SEL BYTE ADDR DATA IN 1 DATA IN 2

DATA IN 3

AI02803C

Page Write (cont'd)

WC (cont'd)

STOP

DATA IN N

ACK ACK NO ACK

R/W

ACK ACK NO ACK NO ACK

R/W

NO ACK NO ACK

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