The M29W800 is a non-volatilememory that may
beerasedelectricallyat theblock or chipleveland
programmedin-systemonaByte-by-Byteor Wordby-Wordbasisusingonly a single2.7V to 3.6V V
supply. For Program and Erase operations the
necessary high voltages are generated internally.
The device can also be programmed in standard
programmers.
Thearraymatrixorganisationallowseach block to
be erased and reprogrammed without affecting
otherblocks.Blockscan be protectedagainst programing and erase on programming equipment,
CC
12 x 20 mm
Figure1. LogicDiagram
V
CC
19
A0-A18
W
E
G
RP
M29W800T
M29W800B
V
SS
M29W800T
M29W800B
NOT FOR NEW DESIGN
44
1
SO44 (M)TSOP48 (N)
15
DQ0-DQ14
DQ15A–1
BYTE
RB
AI02178
June 19991/33
Thisis informationon a product stillin productionbutnotrecommended for newdesigns.
Notes: 1. Except for therating ”OperatingTemperature Range”, stresses above those listed in the Table ”AbsoluteMaximum Ratings”
may cause permanent damage to thedevice. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operatingsections of this specification is not implied.Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.Refer also tothe STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltagemay undershootto –2V during transition and for less than 20ns.
3. Depends on range.
Ambient Operating Temperature
Temperature Under Bias–50 to 125
Storage Temperature–65 to 150
Input or Output Voltages–0.6to 5V
Supply Voltage–0.6to 5V
(2)
A9, E, G, RP Voltage–0.6to 13.5V
DESCRIPTION(Cont’d)
and temporarily unprotected to make changes in
the application. Each block can be programmed
and erased over 100,000 cycles.
Instructionsfor Read/Reset, Auto Select for reading the Electronic Signature or Block Protection
status,Programming,BlockandChipErase,Erase
Suspend and Resume are written to the devicein
cyclesofcommandstoaCommandInterfaceusing
standardmicroprocessorwrite timings.
Thedevice is offered in TSOP48(12 x20mm)and
SO44packages.Both normal and reversepinouts
are available for the TSOP48package.
Organisation
TheM29W800is organisedas1 M x8 or512Kx16
bitsselectableby the BYTEsignal.WhenBYTE is
Low the Byte-wide x8 organisationis selectedand
the address lines are DQ15A–1and A0-A18. The
Data Input/Output signal DQ15A–1 acts as address line A–1 which selects the lower or upper
Byteof the memoryword for output on DQ0-DQ7,
DQ8-DQ14 remain at High impedance. When
BYTEis Highthe memoryuses the addressinputs
A0-A18 and the Data Input/Outputs DQ0-DQ15.
Memory control is provided by Chip Enable E,
OutputEnable G and WriteEnable W inputs.
blocks previously protected allowing them to be
programedanderased.Erase andProgramoperations are controlled by an internal Program/Erase
Controller(P/E.C.). StatusRegisterdata output on
DQ7providesa DataPollingsignal,and DQ6 and
DQ2provideToggle signalstoindicatethe state of
(1)
(3)
–40 to 85
C
°
C
°
C
°
the P/E.C operations. A Ready/Busy RB output
indicatesthecompletionof theinternalalgorithms.
MemoryBlocks
Thedevicesfeatureasymmetrically blockedarchitectureprovidingsystem memory integration.Both
M29W800Tand M29W800Bdeviceshavean array
of 19 blocks, one Boot Block of 16 KBytes or 8
KWords, two Parameter Blocks of 8 KBytes or 4
KWords, one Main Block of 32 KBytes or 16
KWordsand fifteenMainBlocksof 64KBytesor 32
KWords.TheM29W800ThastheBoot Block atthe
top of the memory add ress space and the
M29W800Blocates the Boot Block starting at the
bottom. The memory maps are showed in Figure
3.
Each block can be erased separately, any combi-
nation of blocks can be specified for multi-block
eraseor the entirechip may beerased.TheErase
operations are managed automatically by the
P/E.C. The block erase operation can be suspended in order to read from or program to any
blocknot being ersased, and then resumed.
Block protection provides additionaldata security.
Each block can be separatelyprotected or unprotectedagainst Program or Erase on programming
equipment.All previously protected blocks can be
temporarilyunprotectedin the application.
Bus Operations
The following operations can be performed using
theappropriatebus cycles:Read(Array,Electronic
Signature, Block Protection Status), Write command, Output Disable,Standby,Reset, Block Protection, Unprotection, Protection Verify,
Unprotection Verifyand Block Temporary Unprotection.See Tables4 and5.
3/33
M29W800T, M29W800B
Figure3A. TopBootBlock Memory Map and Block Address Table
Instructions,made up of commands written in cycles,canbe givento theProgram/EraseController
through a Command Interface (C.I.). For added
dataprotection,programor eraseexecutionstarts
after4 or6cycles.The first,second,fourthandfifth
This Coded sequence is the same for all Program/Erase Controller instructions. The ’Command’itself and its confirmation,when applicable,
are given on the third, fourth or sixth cycles. Any
incorrectcommandor any impropercommandsequence will resetthe device to Read Array mode.
cycles are used to input Coded cycles to the C.I.
6/33
M29W800T, M29W800B
Table3B. M29W800BBlock Address Table
Address Range (x8)Address Range (x16)A18A17A16A15A14A13A12
Seven instructions are defined to perform Read
Array,AutoSelect(toreadthe ElectronicSignature
or BlockProtectionStatus),Program,BlockErase,
Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handlesall timing and verification of the Program and Erase
operations.TheStatus Register Data Polling,Toggle, Error bits and the RB output may be read at
anytime, during programmingor erase, to monitor
the progress of theoperation.
Instructionsarecomposedof upto six cycles. The
first two cycles input a Coded sequence to the
CommandInterfacewhich iscommon toall instructions(see Table 8).
The third cycle inputs the instruction set-up com-
data, Electronic Signature or Block Protection
Status for Read operations.In order to give additional data protection,the instructionsforProgram
and Block or Chip Erase require further command
inputs. For a Programinstruction,the fourth command cycle inputs the address and data to be
programmed. For an Erase instruction (Block or
Chip), the fourth and fifth cycles input a further
Coded sequence before the Erase confirm commandonthesixthcycle.Erasureofamemoryblock
may be suspended, in order to read data from
anotherblock or to program data inanotherblock,
and then resumed.
When power is first applied or if V
, the command interface is reset to Read
V
LKO
CC
Array.
mand. Subsequent cycles output the addressed
falls below
7/33
M29W800T, M29W800B
SIGNALDESCRIPTIONS
See Figure 1 and Table1.
AddressInputs(A0-A18). The addressinputsfor
thememoryarray are latchedduringawriteoperation on the falling edge at Chip Enable E or Write
EnableW. In Word-wide organisation the address
lines are A0-A18, in Byte-wide organisation
DQ15A–1acts as an additional LSB address line.
WhenA9 israised to V
, eithera Read Electronic
ID
Signature Manufacturer or Device Code, Block
Protection Status or a Write Block Protection or
Block Unprotection is enabled depending on the
combinationof levelson A0,A1, A12andA15.
Data Input/Outputs (DQ0-DQ7). These Inputs/Outputsare used in the Byte-wideand Wordwide organisations. The inpu t is data to be
programmed in the memory array or a command
to be written to the C.I. Both are latched on the
rising edge of Chip Enable E or Write Enable W.
The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
registerData Polling bit DQ7, the ToggleBits DQ6
and DQ2, the Error bit DQ5 or the EraseTimer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high
impedance when the chip is deselected or the
outputsaredisabledandwhenRPis ataLowlevel.
Data Input/Outputs (DQ8-DQ14and DQ15A–1).
These Inputs/Outputsare additionally used in the
Word-wide organisation.WhenBYTEisHighDQ8DQ14 and DQ15A–1 act as the MSB of the Data
Inputor Output,functioningas described for DQ0DQ7 above, and DQ8 - DQ15 are ’don’t care’ for
commandinputs or statusoutputs. When BYTEis
Low,DQ0-DQ14arehighimpedance,DQ15A–1is
theAddressA–1input.
Chip Enable (E). The Chip Enable inputactivates
the memory control logic, input buffers, decoders
andsenseamplifiers.E Highdeselectsthememory
andreducesthe powerconsumptiontothestandby
level. E can also be used to control writing to the
commandregister and to the memory array, while
Wremainsata lowlevel.TheChipEnablemust be
forcedto V
duringthe BlockUnprotectionopera-
ID
tion.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read
operation. When G is High the outputs are High
impedance. G must be forced to V
level during
ID
BlockProtectionand Unprotection operations.
WriteEnable(W).Thisinputcontrolswritingto the
CommandRegisterand Addressand Datalatches.
Byte/Word Organization Select (BYTE). The
BYTEinputselectstheoutputconfigurationfor the
device: Byte-wide (x8) mode or Word-wide (x16)
mode. When BYTEis Low,the Byte-widemode is
selectedand thedata isread and programmedon
DQ0-DQ7. In this mode, DQ8-DQ14 are at high
impedance and DQ15A–1 is the LSB address.
When BYTE is High, the Word-wide mode is selected and the data is read and programmed on
DQ0-DQ15.
Ready/Busy Output (RB). Ready/Busy is an
open-drainoutputandgivestheinternalstateofthe
P/E.C. of the device. When RB is Low, the device
is Busy with a Program or Erase operation and it
will not accept any additional program or erase
instructionsexcept theEraseSuspendinstruction.
WhenRB is High, thedeviceis readyforany Read,
Program or Erase operation. The RB will also be
Highwhen the memoryis put inEraseSuspendor
Standbymodes.
Reset/Block Temporary Unprotect Input (RP).
The RP Input provides hardware reset and protected block(s) temporary unprotection functions.
Resetof the memory is acheivedby pulling RP to
foratleastt
V
IL
. Whentheresetpulseisgiven,
PLPX
if the memoryis in Reador Standby modes, it will
be available for new operations in t
PHEL
after the
risingedgeofRP.If thememoryis in Erase,Erase
Suspend or Program modes the reset will take
duringwhichtheRBsignalwillbe held at VIL.
t
PLYH
The end of the memory reset will be indicated by
the rising edge of RB. A hardware reset during an
Erase or Program operation will corrupt the data
being programmed or the sector(s) being erased.
SeeTable 14 and Figure 9.
Temporary block unprotectionis made by holding
RP at V
. In this condition previously protected
ID
blockscan be programmed or erased.The transitionof RPfrom V
to VIDmustslowerthant
IH
PHPHH
See Table 15 and Figure 9. When RP is returned
from V
to VIHall blocks temporarily unprotected
ID
will be again protected.
V
Supply Voltage. The power supply for all
CC
operations(Read,Programand Erase).
Ground. VSSis the reference for all voltage
V
SS
measurements.
.
8/33
M29W800T, M29W800B
DEVICEOPERATIONS
See Tables 4, 5 and 6.
Read. Read operations are used to output the
contents of the Memory Array,the ElectronicSignature,theStatusRegisteror the BlockProtection
Status.Both Chip Enable E and Output Enable G
must be low in order to read the output of the
memory.
Write.WriteoperationsareusedtogiveInstruction
Commandstothe memory or to latch input data to
beprogrammed.Awrite operationis initiatedwhen
Chip Enable E isLow and Write Enable W is Low
withOutputEnableG High.Addressesarelatched
onthefallingedge of W or E whicheveroccurslast.
CommandsandInputDataarelatchedontherising
edgeof W or E whicheveroccursfirst.
OutputDisable. The data outputsarehighimpedancewhen the OutputEnable G is High with Write
EnableW High.
Standby. The memory is in standby when Chip
EnableE is Highand theP/E.C.is idle.The power
consumption is reduced to the standby level and
the outputs are high impedance, independent of
the Output Enable G or WriteEnable W inputs.
AutomaticStandby. After 150ns of bus inactivity
andwhen CMOS levels are drivingthe addresses,
the chip automatically enters a pseudo-standby
modewhereconsumptionis reducedto theCMOS
standbyvalue,while outputsstill drivethe bus.
ElectronicSignature. Two codes identifying the
manufacturer and thedevicecanbe read fromthe
memory. The manufacturer’s code for STMicroelectronicsis20h,thedevicecodeisD7hforthe
M29W800T(TopBoot)and 5BhfortheM29W800B
(Bottom Boot). These codes allow programming
equipment or applications to automatically match
their interface to the characteristics of the
M29W800.The ElectronicSignatureis outputby a
Read operationwhen the voltage applied to A9 is
andaddressinputsA1 isLow.The manufac-
atV
ID
turer code is output when the Address input A0 is
Low and the device code when this input is High.
Other Address inputs are ignored. The codes are
output on DQ0-DQ7.
TheElectronicSignaturecan alsobe read,without
raisingA9 to V
, bygiving the memorythe Instruc-
ID
tion AS. If the Byte-wide configuration is selected
thecodes areoutputonDQ0-DQ7with DQ8-DQ14
atHigh impedance;if the Word-wideconfiguration
isselectedthe codes are output on DQ0-DQ7with
DQ8-DQ15at 00h.
Block Protection. Each block can be separately
protected against Program or Erase on programming equipment. Block protection provides additional data security, as it disables all program or
eraseoperations.Thismodeisactivatedwhenboth
A9 and G are raised to V
and an address in the
ID
block is applied on A12-A18. Block protection is
initiatedon the edge of W falling to V
a delayof 100µs,the edge of W rising to V
. Then after
IL
IH
ends
theprotectionoperations.Blockprotectionverifyis
achievedby bringingG, E, A0and A6toV
, while W is atVIHandA9at VID. Underthese
toV
IH
andA1
IL
conditions,reading the data outputwill yield 01h if
the block defined by the inputs on A12-A18 is
protected.Any attempt to program or erasea protectedblockwill be ignoredby the device.
Block Temporary Unprotection. Any previously
protectedblock can be temporarilyunprotectedin
ordertochangestoreddata.Thetemporaryunprotection mode is activated by bringing RP to V
ID
During the temporary unprotection mode the previously protected blocks are unprotected. A block
can be selected and data can be modified by
executingtheEraseorPrograminstructionwiththe
RPsignalheldat V
. When RP is returnedto VIH,
ID
all the previously protected blocks are again protected.
Block Unprotection. All protected blocks can be
unprotected on programming equipment to allow
updating of bit contents. All blocks must first be
protectedbefore theunprotectionoperation.Block
unprotectionis activatedwhen A9, G and E are at
and A12, A15 at VIH. Unprotection is initiated
V
ID
bytheedgeofWfallingto V
. Afteradelayof10ms,
IL
the unprotection operation will end. Unprotection
verify is achievedby bringing G and E to V
A0 is at V
atV
ID
, A6 and A1 are at VIHand A9 remains
IL
. Inthese conditions,readingtheoutput data
IL
while
will yield 00h if the block defined by the inputs
A12-A18has been succesfully unprotected. Each
block must be separatelyverified by giving its address in order to ensure that it has been unprotected.
.
9/33
M29W800T, M29W800B
Table4. User Bus Operations
(1)
OperationEGWRPBYTEA0A1A6A9A12 A15
Read WordV
Read ByteV
Write WordV
Write ByteV
Output DisableV
StandbyV
ILVIL
ILVIL
ILVIH
ILVIH
ILVIH
IH
ResetXXXV
Block
Protection
Blocks
Unprotection
Block
Protection
Verify
Block
Unprotection
Verify
Block
Temporary
Unprotection
Notes: 1. X = V
(2,4)V
(2,4)
(2,4)
ILVIDVIL
(4)VIDVIDVIL
VILV
VILV
XX X V
or V
IL
2. Block Address must be given on A12-A18bits.
3. See Table6.
4. Operation performed onprogramming equipment.
IH
V
V
V
IH
IH
V
V
IH
IH
V
V
IL
IH
V
V
IL
IH
V
V
IH
IH
A0A1A6A9A12 A15
IH
V
A0A1A6A9A12 A15
IL
V
A0A1A6A9A12 A15 Data Input Data Input
IH
V
A0A1A6A9A12 A15
IL
XXXXXXXHi-ZHi-ZHi-Z
XXVIHXXXXXXXHi-ZHi-ZHi-Z
XXXXXXXHi-ZHi-ZHi-Z
IL
Pulse V
Pulse V
V
IL
IH
V
IL
IH
XXXXVIDXX X XX
IH
XXXXVIDVIHV
IH
V
XVILVIHVILVIDA12 A15XX
IH
V
XVILVIHVIHVIDA12 A15XX
IH
X XXXXXX X XX
ID
DQ15
A–1
Data
Output
Address
Input
Address
Input
XXX
IH
DQ8-
DQ14
Data
Output
Hi-Z
Hi-Z
DQ0-DQ7
Data
Output
Data
Output
Data
Input
Data
Input
Block
Protect
Status
Block
Protect
Status
(3)
(3)
Table5. Read Electronic Signature(followingAS instructionor with A9 = VID)