SGS Thomson Microelectronics M29W017D Datasheet

FEATURES SUMMARY

■ SUPPLY VOLTAGE

–V

2.7V to 3.6V for Program, Erase and

CC =

Read

■ ACCESS TIME: 70, 90ns

■ PROGRAMMING TIME

– 10µs per Byte typical

■ 32 UNIFORM 64 KByte MEMORY BLOCKS

■ PROGRAM/ERA SE CON T ROL LER

– Embedded Byte Program algorithms

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■ UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programm ing

■ TEMPORARY BLOCK UNPROTECTION

MODE

■ COMMON FLASH INTERFACE

– 64 bit Security Code

■ LOW POWER CONSUMPTION

– Standby and Automatic Standby

■ 100,000 PROGRAM/ER ASE CYCL ES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h
– Device Code: C8h

M29W017D

16 Mbit (2Mb x8, Uniform Block)

3V Supply Fl ash Me m ory

PRELIMINARY DATA

Figure 1. Packages

TSOP40 (N)

10 x 20mm

FBGA

TFBGA48 (ZA)
6 x 8 ball array

April 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1/36

M29W017D

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 16. Block Addresses, M29W017D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V

Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

V

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SS

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Erase Suspend Comma nd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Protect and Chip Unprotect Commands.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2/36

M29W017D

Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 14

STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

Figure 7. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Table 7. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 8. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 10. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 11. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 13. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline . . . . . . . . . . . . . . . . 24

TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mecha nical Data . . . . . . . . 24

TFBGA48 8x9mm – 6x8 active ball array – 0.80mm pitch, Bottom View Packag e Outline . . . . . . 25

TFBGA48 8x9mm – 6x8 active ball array – 0.80mm pitch, Package Mec hanical Data . . . . . . . . . 25

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 15. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

3/36

M29W017D

APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 16. Block Addresses, M29W017D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 17. Query Structure Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 18. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 19. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 20. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 21. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 22. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

APPENDIX C. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 23. Programmer Technique Bus Operations, BYTE = V

Figure 14. Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 15. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 16. In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 17. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

or VIL . . . . . . . . . . . . . . . . . . . . . 31

IH

4/36

SUMMARY DESCRIPTION

The M29W017D is a 16 Mbit (2Mb x8) non-volatile
memory that can be read, erased and repro­grammed. These operations can be performed us­ing a single low voltage (2.7 to 3 .6V) supply. On
power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or
EPROM.

The memory is divided into 32 blocks of 64KBytes
(see Table 16, Block Addresses) that can be
erased independently so it is pos sible to pres erve
valid data while old data is erased. Each block can
be protected independently to prev ent accidental
Program or Erase commands from modifying the
memory. Program and Erase com m ands are wri t­ten to the Command Interface of t he memory. An

process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase op eration can be de tected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.

Chip Enable, Output Enable and Write Enable sig­nals control the bus operation of the memory.
They allow simple conne ction to most m icropro­cessors, often without additional logic.

The memory is offer ed in TSOP40 (10 x 20mm) and
TFBGA48 (0.8mm pitch) pac kages. The memory is

supplied with all the bi ts erased (se t t o ’ 1’).

on-chip Program/Erase Controller simplifies the

Figure 2. Logi c D iag ram Table 1. Si gn a l Nam es

A0-A20 Address Inputs

M29W017D

A0-A20

W

RP

V

CC

21

E

G

M29W017D

V

SS

8

DQ0-DQ7

RB

AI04186

DQ0-DQ7 Data Inputs/Outputs
E
G
W
RP
RB
V

CC

V

SS

NC Not Connected Internally

Chip Enable
Output Enable
Write Enable
Reset/Block Temporary Unprotect
Ready/Busy Output
Supply Voltage
Ground

5/36

M29W017D

Figure 3. TSOP Connections

A16
A15
A14
A13
A12

1

40

A17
V

SS

A20
A19
A10

A11 DQ7

31
30

21

DQ6
DQ5
DQ4
V

CC

V

CC

NC
DQ3
DQ2
DQ1
DQ0
G
V

SS
E
A0

A9
A8

W
RP
NC

RB

A18

A7
A6
A5
A4
A3
A2
A1

10
11

20

M29W017D

AI04187

6/36

Figure 4. TFBGA Connections (Top view through package)

M29W017D

654321

A

B

C

D

E

F

G

H

A3

A4

A2

A1

A0

E

G

V

SS

A7

A18

A6

A5 NC

DQ0

NC

NC

DQ1

RB

NC

NC

DQ2

DQ3

V

CC

NC

W

RP

NC

NC

DQ5

NC

V

CC

DQ4

A9

A8

A11

A12

A19

A10

DQ6

DQ7

A14

A13

A15

A16

A17

NC

A20

V

SS

AI04188

7/36

M29W017D

Figure 5. Block Addresses

M29W017D

Block Addresses

1FFFFFh

1F0000h

1EFFFFh

1E0000h

1DFFFFh

1D0000h

1CFFFFh

02FFFFh

020000h

01FFFFh

010000h

00FFFFh

000000h

64 KByte

64 KByte

64 KByte

Total of 32

64 KByte Blocks

64 KByte

64 KByte

64 KByte

AI05429

8/36

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram, and Table 1, Sign al
Names, for a brief overview of the signals connect­ed to this device.

Address Inputs (A0-A20). The Address Inputs
select the cells i n the memory array to a ccess dur­ing Bus Read operations. During Bus Write opera­tions they control the commands sent to the
Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the internal state ma­chine.

Chip Enable (E

). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op­erations to be performed. When Chip Enable is
High, V

Output Enable (G

, all other pins are ignored.

IH

). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, controls

the Bus Write operation of the memory’s Com­mand Interf a c e.

Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that hav e b een
protected.

A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V

. After Reset/Block Temporary Unprotect

t

PLPX

goes High, V

, the memory will be ready for Bus

IH

Read and Bus Write operations after t
t

, whichever occurs last. See the Ready/Busy

RHEL

, for at least

IL

PHEL

or

Output section, Table 13 and Figure 13, Reset/
Temporary Unprotect AC Characteristics for more
details.

Holding RP

at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.

M29W017D

The transition from V
t

PHPHH

.

Ready/Busy Output (RB

is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V
pedance during Read mode, Auto Select mode
and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be­comes high-impedance. See Tabl e 13 and Figure
13, Reset/Temporary Unprotect AC Characteris­tics .

The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.

Supply Voltage (2.7V to 3.6V). VCC pro-

V

CC

vides the power supply for all operations (Read,
Program and Erase).

The Command Interface is disabled when the V
Supply Voltage is less than the L ockout Voltage,
V

. This prevents Bus Write operations from ac-

LKO

cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo­ry contents being altered will be invalid.

A 0.1µF capacitor should be connected between
the V

Supply Voltage pin and the VSS Ground

CC

pin to decouple the current surges from the power
supply. See Figure 10, AC Measurement Load Cir­cuit. T he PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I

Ground. VSS is the reference for all voltage

V

SS

measurements.

to VID must be slower than

IH

). The Ready/Busy pin

. Ready/Busy is high-im-

OL

.

CC3

CC

9/36

M29W017D

BUS OPERATIONS

There are five standard bus operations that control
the device. These are Bus Read, Bus Wri te, Out­put Disable, Standby and Automatic Standby. See
Tables 2, Bus Operations, for a summary. Typical­ly glitches of less than 5ns on Chip Enable or Write
Enable are ignored by t he mem ory and do not a f­fect bus operations.

Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com­mand Interface. A valid Bus Read operation in­volves setting the desired address on the Address
Inputs, applying a Low sig nal, V
and Output Enable and keeping Write Enable
High, V

. The Data Inputs/Outputs will output the

IH

value, see Figure 10, Read Mode AC Waveforms,
and Table 10, Read AC Characteristics, for details
of when the output becomes valid.

Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desire d address on t he Ad­dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs a re latched by the Com­mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En­able must remain High, V

IH

Write operation. See Figures 11 and 12, Write AC
Waveforms, and Tables 11 and 12, Write AC
Characteristics, for details of the timing require­ments.

Output Disa bl e . The Data Inputs/Outputs are in
the high impedance s tate when Output Enable is
High, V

.

IH

Standby. When Chip Enable is High, V
memory enters Standby mode and the Data In­puts/Outputs pins are placed in the high-imped-

, to Chip Enable

IL

, during the whole Bus

, the

IH

ance state. To reduce the S upply Current to the
Standby Supply Current, I
be held within V

± 0.2V. For the Standby current

CC

, Chip Enable should

CC2

level see Table 9, DC Characteristics.
During program or erase operations the memory

will continue to use the Program/Erase Supply
Current, I

, for Program or Erase operations un-

CC3

til the operation completes.
Automatic Standby. If CMOS levels (V

± 0.2V)

CC

are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re­duced to the Standby Supply Current, I

CC2

. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protec tio n. These bus opera­tions are intended for use by programming equip­ment and are not usually used in applications.
They require V

to be applied to some pins.

ID

Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying t he signals
listed in Tables 2, Bus Operations.

Block Protection and Blocks Unprotection.

Each block can be separately protected against
accidental Program or Erase. Protected blocks
can be unprotected to allow data to be changed.

There are two methods available for protecting
and unprotecting the blocks, one for use on pro­gramming equipment and the other for in-system
use. Block Protect and Chip Unprot ec t operat ions
are described in Appendix C.

Table 2. Bus Operations

Operation E G W

Bus Read
Bus Write
Output Disable X
Standby
Read Manufacturer

Code

Read Device Code

Note: X = VIL or VIH.

10/36

V

IL

V

IL

V

IH

V

IL

V

IL

Address Inputs

A0-A20

V

IL

V

IH

V

IH

X X X Hi-Z

V

IL

V

IL

V

Cell Address Data Output

IH

V

Command Address Data Input

IL

V

X Hi-Z

IH

A0 = VIL, A1 = VIL, A9 = VID,

V

IH

Others V
A0 = VIH, A1 = VIL,

V

IH

A9 = V

or V

IL

IH

, Others VIL or V

ID

IH

Data Inputs/Outputs

DQ7-DQ0

C8h

20h

COMMAND INTERFACE

All Bus Write operations t o the me mory are in ter­preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper­ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return­ing to Read mode. The long command sequences
are imposed to maximize data security.

Refer to Table 3, Commands, in conjunc tion with
the following text descriptions.

Read/Reset Command. The Read/Reset com­mand returns the memory to its Read mode where
it behaves like a ROM or EPROM, unless other­wise stated. It also resets t he errors in the S tatus
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.

The Read/Reset Command can be issued, be­tween Bus Write cycles before the start of a pro­gram or erase operation, to return the device to
read mode. Once the program or erase operation
has started the Read/Reset command is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.

Auto Select Command. The Auto Select com­mand is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re­quired to issue the Auto Select command. Once
the Auto Select comma nd is issued the memory
remains in Auto Select mode until a Read/Reset
command is issued. Read CFI Query and Read/
Reset commands are accepted in Auto Select
mode, all other commands are ignored.

From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V
may be set to either V

and A1 = VIL. The other address bits

IL

or VIH. The Manufa cturer

IL

Code for STMicroelectronics is 20h.
The Device Code can be read using a B us Read

operation with A0 = V
address bits may be set to e ither V

and A1 = VIL. The other

IH

or VIH. The

IL

Device Code for the M29W017D is C8h.
The Bl ock Protection Status of each block can be

read using a Bus Read operation with A0 = V
A1 = V

, and A 16 -A 20 spec ify i n g t he address of

IH

IL

the bl ock. The oth er addr ess bit s may b e set t o ei­ther V

or VIH. If t h e ad dr ess ed b loc k is pro tec te d

IL

then 01h is output on Data Inputs/Outputs DQ0­DQ7, otherwise 00h is output.

Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command re­quires four Bus Write operations, the final write op­eration latches the address and data in the internal
state machine and starts the Program/Erase Con­troller.

M29W017D

If the address falls in a pro tected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.

During the program operat ion the memo ry will ig­nore all commands. I t is n ot poss ible t o iss ue any
command to abort or pause the operation. Typical
program times are given in Table 4. Bus Read op­erations during the program o peration will output
the Status Register on the Data Inputs/Outputs.
See the section on the S tatus Register for more
details.

After the program operation has completed the
memory will return to the Read mode, unle ss an
error has occurred. When an error occurs the
memory will continue to output the Status Regis­ter. A Read/Reset command must be issued to re­set the error condition and return to Read mode.

Note that the Program command cannot change a

bit set at ’0’ bac k to ’1’. One of the E rase Com­mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.

Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memo­ry. When the cycle time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com­mands. Three Bus Write operations are requ ired
to issue the Unlock Bypass command.

Once the Unlock Bypas s command has bee n is­sued the memory will only accept the Unloc k By­pass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.

Unlock Bypass Program Command. The Un­lock Bypass Prog ra m command can be u sed to
program one address in the memory array at a
time. The command requires two Bus Write oper­ations, the final write operation latches the ad­dress and data in the internal state machine and
starts the Program/Erase Controller.

The Program operation using the Unlock Bypass

,

Program command behaves identically to the Pro­gram operation using the Program command. A
protected block cannot be programmed; the oper­ation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Re set
command, which l eaves the d evice in Unlo ck By­pass Mode. See the Program command for details
on the behavior.

Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return t o
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command. Read/Reset

11/36