M29W008T and M29W008B are replaced
respectively by the M29W008AT and
M29W008AB
2.7V to 3.6V SUPPLY VOLTAG E for
PROGRAM, ERASE and READ OPERATIONS
FAST A CCES S TIME : 100ns
FAST PROGRAMMING TIME: 10µs typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte
– Status Register bits and Ready/Busy Output
MEMOR Y BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MOD ES
– Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DA TA RETE NT ION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code, M29W008T: D2h
– Device Code, M29W008B: DCh
DESCRIPTION
The M29W008 is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte basis
using only a single 2.7V to 3.6V V
Program and Erase operations the necessary high
voltages are generated internally. The device can
also be programmed in standard programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against programing and erase on programming equipment,
and temporarily unprotected to make changes in
supply. For
CC
M29W008T
M29W008B
8 Mbit (1Mb x8, Boot Block)
NOT FOR NEW DESIGN
TSOP40 (N)
10 x 20 mm
Figure 1. Logic Diagram
V
CC
A0-A19
W
RP
20
E
G
M29W008T
M29W008B
V
SS
8
DQ0-DQ7
RB
AI02189
June 19991/30
This is information on a product still in production but not recommended for new designs.
M29W008T, M29W008B
Figure 2. TSOP Pin Connections
A16
A15
A14
A13
A12
A11
A9
A8
W
RP
NC
RB
A18
A6
A5
A4
A3
A2
A1
Warning:
NC = Not Connected.
DESCRIPTION
1
M29W008T
10
M29W008B
11
2021
AI02190
(Cont’d)
40
31
30
A17
V
SS
NC
A19
A10
DQ7
DQ6
DQ5
DQ4
V
CC
V
CC
NC
DQ3
DQ2A7
DQ1
DQ0
G
V
SS
E
A0
the application. Each block can be programmed
and erased over 100,000 cycles.
Instructions for Read/Reset, Auto Select for reading the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase, Erase
Suspend and Resume are written t o the device in
cycles of commands to a Command Interface using
standard microprocessor write timings. The device
is offered in TSOP40 (10 x 20mm) package.
Organisation
The M29W008 is organised as 1Mb x 8. The memory uses the address inputs A0-A19 and the Data
Input/Outputs DQ0-DQ7. Memory control is provided by Chip Enable
Enable
W inputs.
A Reset/Block T emporary Unprotection
E, Output Enable G and Write
RP tri-level
input provides a hardware reset when pulled Low,
and when held High (at V
) temporarily unprotects
ID
blocks previously protected allowing them to be
programed and erased. Erase and Program operations are controlled by an internal Program/Erase
Controller (P/E.C.). Status Register data output on
DQ7 provides a Data Polling signal, and DQ6 and
DQ2 provide Toggle signals to indicate the state of
the P/E.C operations. A Ready/Busy R
B output
indicates the completion of the internal algorithms.
T ab le 2. Absolute Maximum Ratings
SymbolParameterValueUnit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
V
(A9, E, G, RP)
Notes:
1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress rating s only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Depends on range.
2/30
Ambient Operating Temperature
Temperature Under Bias–50 to 125
Storage Temperature–65 to 150
Input or Output Voltages–0.6 to 5 V
Supply Voltage–0.6 to 5 V
(2)
A9, E, G, RP Voltage–0.6 to 13.5 V
(1)
(3)
–40 to 85
C
°
C
°
C
°
M29W008T, M29W008B
Memory Blocks
The devices feature asymmetrically blocked architecture providing system memory integration. Both
M29W008T and M29W008B devices have an array
of 19 blocks, one Boot Block of 16 Kbytes, two
Parameter Blocks of 8 Kbytes, one Main B lock of
32 Kbytes and fifteen Main Blocks of 64 Kbytes.
The M29W008T has the Boot Block at the top of
the memory address space and the M29W008B
locates the Boot Block starting at the bottom. The
memory maps are showed in Figure 3. E ach block
can be erased separately, any combination of
blocks can be specified for multi-block erase or the
entire chip may be erased. The Erase operations
are managed automatically by the P/E.C. The block
erase operation can be suspended in order to read
from or program to any block not being ersased,
and then resumed.
Block protection provides additional data security.
Each block can be separately protected or unprotected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotected in the application.
Bus Operations
The following operations can be performed usi ng
the appropriate bus cycles: Read (Array , E lectronic
Signature, Block Protection Status), Write command, Output Disable, Standby, Reset, Block Protection, Unprotection, Protection Verify,
Unprotection Verify and Blo ck Temporary Unprotection. See Tables 4 and 5.
Command Interface
Instructions, made up of commands written in cycles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and fifth
cycles are used to input Coded cycles to the C.I.
This Coded sequence is the same for all Program/Erase Controller instructions. The ’Command’ itself and its confirmation, when applicable,
are given on the third, four th or sixth cycles. Any
incorrect command or any improper command sequence will reset the device to Read Array mode.
Instructions
Seven instructions are defined to perform Read
Array , Auto Select (to read the Electronic Signature
or Block Protection Status), Program, Block Erase,
Chip Erase, Erase Suspend and Er ase Resume.
The internal P/E.C. automatically handles all timing and verification of the Program and Erase
operations. The Status Register Data Polling, Toggle, Error bits and the R
B output may be read at
any time, during programming or erase, to monitor
the progress of the operation.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all instructions (see Table 8). The third cycle inputs the
instruction set-up command. Subsequent cycles
output the addressed data, Electronic Signature or
Block Protection Status for Read operations. In
order to give additional data protection, the instructions for Program and Block or Chip Erase require
further command inputs. For a P rogram instruction,
the fourth command cycle inputs the address and
data to be programmed. For an Erase instruction
(Block or Chip), the fourth and fifth cycles input a
further Coded sequence before the Erase confirm
command on the sixth cycle. Erasure of a memory
block may be suspended, in order to read data from
another block or to program data in another block,
and then resumed.
When power is first applied or if Vcc falls below
, the command interface is reset to Read
V
LKO
Array.
SIGNAL DESCRIP TIONS
See Figure 1 and T able 1.
Address Inputs (A0-A19)
. The address inputs for
the memory array are latched during a write operation on the falling edge of Chip E nable
Enable
W. When A9 is raised to VID, either a Read
E or Write
Electronic Signature Manufacturer or Dev ice Code,
Block Protection Status or a W rite Block P rotection
or Block Unprotection is enabled depending on t he
combination of levels on A0, A 1, A12 and A 15.
Data Input/Outputs (DQ0-DQ7).
The input is data
to be programmed in the memory arr ay or a command to be written to t he C.I. Both are latched on
the rising edge of Chip Enable
E or Write Enable
W. The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
register Data Polling bit DQ7, the Toggle Bits DQ6
and DQ2, the Error bit DQ5 or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable
Output Enable
G are active. The output is high
E and
impedance when the chip is deselected or the
outputs are disabled and when
The Chip Enable input activates
Chip Enable (
E).
RP is at a Low level.
the memory control logic, input buffers, dec oders
and sense amplifiers.
E High deselects the memory
and reduces the power consumption to the standby
E can also be used to control writing to the
level.
command register and to the memory array, while
W remains at a low level. The Chip Enable must be
forced to V
during the Block Unprotection opera-
ID
tion.
3/30
M29W008T, M29W008B
Figure 3A. Top Boot Block Memory Map and Block Address Table
outputs through the data buffers during a read
operation. When
impedance.
G is High the outputs are High
G must be forced to VID level during
Block Protection and Unprotection operations.
Write Enable (
This input controls writing to the
W).
Command Register and Address and Data latches.
Ready/Busy Output (R
Ready/Busy is an
B).
open-drain output and gives the internal state of the
P/E.C. of the device. When R
B is Low, the device
is Busy with a Program or Erase operation and it
When R
Program or Erase operation. T he R
High when the memory is put in Erase Suspend or
Standby modes.
Reset/Block Temporary Unprotect Input (
The
tected block(s) temporary unprotection functions.
Reset of the memory is acheived by pulling
V
if the memory is in Read or Standby modes, it will
be available for new operations in t
rising edge of
B is High, the device is ready for any Read,
RP Input provides hardware reset and pro-
for at least t
IL
. When the reset pulse is given,
PLPX
RP.
will not accept any additional program or erase
instructions except the Erase Suspend instruction.
If the memory is in Erase, Erase Suspend or Program modes the reset will take t
B signal will be held at VIL. The end of the
the R
during which
PLYH
memory reset will be indicated by the rising edge
B. A hardware reset during an Erase or Pro-
of R
gram operation will corrupt the data being programmed or the sector(s) being erased. See Table
14 and Figure 9.
Temporary block unprotection is made by holding
RP at VID. In this condition previously protected
blocks can be programmed or erased. The transi-
RP from VIH to VID must slower than t
tion of
(See Table 15 and Figure 9). When
from V
to VIH all blocks temporarily unprotected
ID
will be again protected.
Supply Voltage.
V
CC
The power supply for all
operations (Read, Program and Erase).
is the reference for all voltage
Ground.
V
SS
V
SS
measurements.
RP is returned
PHPHH
.
7/30
M29W008T, M29W008B
DEVICE O PERATIONS
See Tables 4, 5 and 6.
Read operations are used to output the
Read.
contents of the Memory Array, the Electronic Signature, the Status Register or the Block Protection
Status. Both Chip Enable
E and Output Enable G
must be low in order to read the output of the
memory.
Write operations are used to give Instruction
Write.
Commands to the memory or to latch input data to
be programmed. A write operation is initiated when
Chip Enable
with Output Enable
on the falling edge of
E is Low and Write Enable W is Low
G High. Addresses are latched
W or E whichever occurs last.
Commands and Input Data are latched on the rising
edge of
Output Disable.
ance when the Output Enable
Enable
Standby.
Enable
W or E whichever occurs first.
The data outputs are high imped-
G is High with Write
W High.
The memory is in standby when Chip
E is High and the P/E .C. is idle. T he power
consumption is reduced to the standby level and
the outputs are high impedance, independent of
the Output Enable
Automatic Standby.
G or Write Enable W inputs.
After 150ns of bus inactivity
and when CMOS levels are driving the addresses,
the chip automatically enters a pseudo-standby
mode where consumption is reduced to the CMOS
standby value, while outputs still drive the bus.
Electronic S ignature.
Two codes identifying the
manufacturer and the device can be read from the
memory. The manufacturer’s code for STMicroelectronics is 20h, the device code is D2h for the
M29W008T (Top Boot) and DCh for the
M29W008B (Bottom Boot). These codes allow programming equipment or applications to aut omatically match their interface to the characteristics of
the M29W008. The Electronic Signature is output
by a Read operation when the voltage applied to
A9 is at V
and address inputs A1 is Low. The
ID
manufacturer code is output when the Address
input A0 is Low and the device code when this input
is High. Other Address inputs are ignored. The
Electronic Signature can also be read, without raising A9 to V
, by giving the memory the Instruction
ID
AS.
Block Protection.
Each block can be separately
protected against Program or Erase on programming equipment. Block protection provides additional data security, as it disables all program or
erase operations. This mode is activated when both
A9 and
G are raised to VID and an address in the
block is applied on A13-A19. Block protection is
initiated on the edge of
a delay of 100µs, the edge of
W falling to VIL. Then after
W rising to VIH ends
the protection operations. Block protection verify is
achieved by bringing
, while W is at VIH and A9 at VID. Under these
to V
IH
G, E, A0 and A6 to VIL and A1
conditions, reading the data output will yield 01h if
the block defined by the inputs on A13-A19 is
protected. Any attempt to program or erase a protected block will be ignored by the device.
Block Temporary Unprotection.
Any previously
protected block can be temporarily unprot ected in
order to change stored data. The temporary unprotection mode is activated by bringing
RP to VID.
During the temporary unprotection mode the previously protected blocks are unprotected. A block
can be selected and data can be modified by
executing the Erase or Program instruction with the
RP signal held at VID. When RP is returned to VIH,
all the previously protected blocks are again protected.
Block Unprotection.
All protected blocks can be
unprotected on programming equipment to allow
updating of bit contents. All blocks must first be
protected before the unprotection operation. Block
unprotection is activated when A9,
and A12, A15 at VIH. Unprotection is initiated
V
ID
by the edge of
W falling to VIL. After a delay of 10ms,
G and E are at
the unprotection operation will end. Unprotection
verify is achieved by bringing
A0 is at V
at V
ID
, A6 and A1 are at VIH and A9 remains
IL
. In these conditions, reading the output data
G and E to VIL while
will yield 00h if the block defined by the inputs
A13-A19 has been succesfully unprotected. Each
block must be separately verified by giving its address in order to ensure that it has been unprotected.
8/30
M29W008T, M29W008B
T ab le 4. User Bus Operations
(1)
OperationEGWRPA0A1A6A9A12A15DQ0-DQ7
Read ByteV
Write ByteV
Output DisableV
Standby V
ResetXXXV
Block
Protection
(2,4)
Blocks
Unprotection
VIL VIDVIL PulseV
V
(4)
V
IL
IL
IL
IH
ID
IL
V
IH
V
IH
XXVIHXXXXXX Hi-Z
V
ID
V
IH
V
IL
V
IH
VIL PulseV
V
V
V
A0A1A6A9A12A15Data Output
IH
A0A1A6A9A12A15Data Input
IH
IH
IH
IH
XXXXXX Hi-Z
XXXXXX Hi-Z
IL
XXXVIDXX X
XXXVIDV
V
IH
IH
Block
Protection
(2,4)
Verify
V
V
IL
IL
V
IH
V
V
IH
V
IL
V
IH
V
IL
ID
A12A15
Protect
Status
Block
Unprotection
(2,4)
Verify
V
V
IL
IL
V
IH
V
V
IH
V
IL
V
IH
V
IH
ID
A12A15
Protect
Status
Block
Temporary
XX XV
ID
XXXXXX X
Unprotection
Notes:
1. X = V
2. Block Address must be given on A13-A19 bits.
3. See Table 6.
4. Operation performed on programming equipment.
IL
or V
IH
X
Block
(3)
Block
(3)
T able 5. Read Electronic Signature (following AS instruction or with A9 = VID)
CodeDeviceEGWA0A1
Manufact. CodeV
Device Code
M29W008TV
M29W008BV
IL
IL
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
IL
V
IH
V
IH
V
IL
V
IL
V
IL
T ab le 6. Read Block Protection with AS Instruction