3/21
M29F100BT, M29F100BB
The blocks in the memory are asymmetrically arranged, see Tables 3A and 3B, Block Addresses.
The first or last 64 Kbytes have been divided into
four additional blocks. The 16 Kbyte Boot Block
can beused forsmall initialization codeto startthe
microprocessor, the two 8 Kbyte Parameter
Blocks can be used for parameter storage and the
remaining 32K is a small MainBlock wherethe application may be stored.
Chip Enable, OutputEnable andWrite Enable signals control the bus operation of the memory.
They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm)
and SO44 packages. Access times of45ns, 70ns,
90ns and120ns are available. The memory is supplied with all the bits erased (set to ’1’).
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of thesignals connected to this device.
Address Inputs (A0-A15). The Address Inputs
select the cells in the memory array to access during Bus Read operations. During BusWrite operations they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the datastored at the selected
address during a Bus Readoperation. During Bus
Write operations they represent the commands
sentto theCommand Interface ofthe internal state
machine.
Data Inputs/Outputs (DQ8-DQ14). The Data Inputs/Outputs output thedata stored at theselected
address during a Bus Readoperation when BYTE
is High, VIH. When BYTE is Low, VIL, these pins
are not usedand are high impedance.During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
pin; DQ15A–1Low will select the LSB of theWord
on the other addresses, DQ15A–1 High will select
the MSB. Throughout thetext consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing BusRead and Bus Write operations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W). The WriteEnable, W, controls
the Bus Write operation of the memory’s Command Interface.
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device atthese or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions forextended periods may affect device reliability. Refer also tothe STMicroelectronics SURE Program and other relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
Symbol Parameter Value Unit
T
A
Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C
Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C
Ambient Operating Temperature (Temperature Range Option 3) –40 to 125 °C
T
BIAS
Temperature Under Bias –50 to 125 °C
T
STG
Storage Temperature –65 to 150 °C
V
IO
(2)
Input or Output Voltage –0.6 to 6 V
V
CC
Supply Voltage –0.6 to 6 V
V
ID
Identification Voltage –0.6 to 13.5 V