SGS Thomson Microelectronics M29F100BT90M1T, M29F100BT90M1, M29F100BT, M29F100BB90N1, M29F100BB90M6 Datasheet

1/21

PRELIMINARY DATA

July 1999

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M29F100BT

M29F100BB

1 Mbit (128Kb x8 or 64Kb x16, Boot Block)

Single Supply Flash Memory

■ SINGLE 5V±10% SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPERATIONS

■ ACCESS TIME: 45ns

■ PROGRAMMING TIME

–8µs per Byte/Word typical

■ 5 MEMORY BLOCKS

– 1 BootBlock (Top or Bottom Location)
– 2 Parameterand 2 Main Blocks

■ PROGRAM/ERASE CONTROLLER

– Embedded Byte/Word Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy OutputPin

■ ERASE SUSPEND and RESUME MODES

– Read and Programanother Block during

Erase Suspend

■ UNLOCKBYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

■ TEMPORARY BLOCK UNPROTECTION

MODE

■ LOW POWER CONSUMPTION

– Standby andAutomatic Standby

■ 100,000 PROGRAM/ERASE CYCLESper

BLOCK

■ 20 YEARS DATA RETENTION

– Defectivity below 1 ppm/year

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h
– M29F100BTDevice Code: 00D0h
– M29F100BB Device Code:00D1h

44

1

TSOP48(N)

12 x 20mm

SO44 (M)

Figure 1. Logic Diagram

AI02916

16

A0-A15

W

DQ0-DQ14

V

CC

M29F100BT

M29F100BB

E

V

SS

15

G

RP

DQ15A–1
BYTE
RB

M29F100BT, M29F100BB

2/21

Figure 2A. TSOP Connections

DQ3

DQ9

DQ2

A6

DQ0

W

A3

RB

DQ6

A8

A9

DQ13

NC

A10 DQ14

A2

DQ12

DQ10

DQ15A–1

V

CC

DQ4

DQ5

A7

DQ7

NC
NC

AI02917

M29F100BT
M29F100BB

12

1

13

24 25

36

37

48

DQ8

NC

NC

A1

NC

A4

A5

DQ1

DQ11

G

A12

A13

NC

A11

BYTE

A15
A14

V

SS

E
A0

RP

V

SS

Figure 2B. SO Connections

G
DQ0
DQ8

A3

A0

E

V

SS

A2
A1

A13

V

SS

A14
A15

DQ7

A12

NC
BYTE

DQ15A–1

DQ5DQ2

DQ3

V

CC

DQ11

DQ4

DQ14

A9

WRB

A4

NC RP

A7

AI02918

M29F100BT
M29F100BB

8

2
3
4
5
6
7

9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
2322

20

19

18

17DQ1

DQ9

A6
A5

DQ6
DQ13

44

39
38
37
36
35
34
33

A11

A10

DQ10

21

DQ12

40

43

1

42
41

NC A8

Table 1. Signal Names

A0-A15 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
E Chip Enable
G Output Enable
W Write Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
BYTE Byte/Word Organization Select
V

CC

Supply Voltage

V

SS

Ground

NC Not Connected Internally

SUMMARY DESCRIPTION

The M29F100B is a 1Mbit (128Kbx8 or 64Kb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per­formed using a single 5V supply.On power-up the
memory defaultsto its Readmode where it can be
read in the same way as a ROM or EPROM. The
M29F100B is fully backward compatible with the
M29F100.

The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands arewrit­ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process ofprogramming or erasing the memory by
taking care of all of the specialoperations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.

3/21

M29F100BT, M29F100BB

The blocks in the memory are asymmetrically ar­ranged, see Tables 3A and 3B, Block Addresses.
The first or last 64 Kbytes have been divided into
four additional blocks. The 16 Kbyte Boot Block
can beused forsmall initialization codeto startthe
microprocessor, the two 8 Kbyte Parameter
Blocks can be used for parameter storage and the
remaining 32K is a small MainBlock wherethe ap­plication may be stored.

Chip Enable, OutputEnable andWrite Enable sig­nals control the bus operation of the memory.
They allow simple connection to most micropro­cessors, often without additional logic.

The memory is offered in TSOP48 (12 x 20mm)
and SO44 packages. Access times of45ns, 70ns,
90ns and120ns are available. The memory is sup­plied with all the bits erased (set to ’1’).

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of thesignals connect­ed to this device.

Address Inputs (A0-A15). The Address Inputs
select the cells in the memory array to access dur­ing Bus Read operations. During BusWrite opera­tions they control the commands sent to the
Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data In­puts/Outputs output the datastored at the selected
address during a Bus Readoperation. During Bus
Write operations they represent the commands

sentto theCommand Interface ofthe internal state
machine.

Data Inputs/Outputs (DQ8-DQ14). The Data In­puts/Outputs output thedata stored at theselected
address during a Bus Readoperation when BYTE
is High, VIH. When BYTE is Low, VIL, these pins
are not usedand are high impedance.During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.

Data Input/Output or Address Input (DQ15A-1).

When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
pin; DQ15A–1Low will select the LSB of theWord
on the other addresses, DQ15A–1 High will select
the MSB. Throughout thetext consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In­puts to include this pin when BYTE is Low except
when stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates
the memory, allowing BusRead and Bus Write op­erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, con­trols the Bus Read operation of the memory.

Write Enable (W). The WriteEnable, W, controls
the Bus Write operation of the memory’s Com­mand Interface.

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device atthese or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi­tions forextended periods may affect device reliability. Refer also tothe STMicroelectronics SURE Program and other relevant qual­ity documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

Symbol Parameter Value Unit

T

A

Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C
Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C
Ambient Operating Temperature (Temperature Range Option 3) –40 to 125 °C

T

BIAS

Temperature Under Bias –50 to 125 °C

T

STG

Storage Temperature –65 to 150 °C

V

IO

(2)

Input or Output Voltage –0.6 to 6 V

V

CC

Supply Voltage –0.6 to 6 V

V

ID

Identification Voltage –0.6 to 13.5 V

M29F100BT, M29F100BB

4/21

Table 3A. M29F100BT Block Addresses

Size

(Kbytes)

Address Range

(x8)

Address Range

(x16)

16 1C000h-1FFFFh E000h-FFFFh

8 1A000h-1BFFFh D000h-DFFFh

8 18000h-19FFFh C000h-CFFFh
32 10000h-17FFFh 8000h-BFFFh
64 00000h-0FFFFh 0000h-7FFFh

Reset/Block Temporary Unprotect (RP). The Re­set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or totem­porarily unprotect all Blocks that have been pro­tected.

A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
t

PLPX

. After Reset/Block Temporary Unprotect
goes High, VIH, the memory will be ready for Bus
Read and Bus Write operations after t

PHEL

or

t

RHEL

, whicheveroccurs last. See the Ready/Busy
Output section, Table 14 and Figure 10, Reset/
Temporary Unprotect AC Characteristics for more
details.

Holding RP at VIDwill temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIHtoVIDmust be slower than
t

PHPHH

.

Ready/Busy Output (RB). The Ready/Busy pin
is anopen-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedanceduring Readmode, AutoSelect
mode and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be­comes high-impedance. See Table14 and Figure
10, Reset/Temporary Unprotect AC Characteris­tics.

During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy will remain Low during

Table 3B. M29F100BB Block Addresses

Size

(Kbytes)

Address Range

(x8)

Address Range

(x16)

64 10000h-1FFFFh 8000h-FFFFh
32 08000h-0FFFFh 4000h-7FFFh

8 06000h-07FFFh 3000h-3FFFh
8 04000h-05FFFh 2000h-2FFFh

16 00000h-03FFFh 0000h-1FFFh

Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.

The use ofan open-drain output allows theReady/
Busy pins fromseveral memories tobe connected
to asingle pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.

Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the 8-bit and 16-bit Bus modes of
the memory. When Byte/Word Organization Se­lect isLow, VIL, the memory is in 8-bit mode, when
it is High, VIH, the memory is in 16-bit mode.

VCCSupply Voltage. The VCCSupply Voltage
supplies the power for all operations (Read, Pro­gram, Erase etc.).

The Command Interface is disabledwhen the V

CC

Supply Voltage is less than the Lockout Voltage,
V

LKO

. Thisprevents Bus Write operationsfrom ac­cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming orerasing during
this time thenthe operation aborts and the memo­ry contents being altered will be invalid.

A 0.1µF capacitor should be connected between
the VCCSupply Voltage pin and the VSSGround
pin to decouplethe current surges from the power
supply. The PCB track widthsmust be sufficient to
carry the currents required during program and
erase operations, I

CC4

.

Vss Ground. The VSSGround is the reference
for all voltage measurements.

5/21

M29F100BT, M29F100BB

Table 4A. Bus Operations, BYTE = V

IL

Note: X = VILor VIH.

Table 4B. Bus Operations, BYTE = V

IH

Note: X = VILor VIH.

Operation E G W

Address Inputs

DQ15A–1, A0-A15

Data Inputs/Outputs

DQ14-DQ8 DQ7-DQ0

Bus Read V

IL

V

IL

V

IH

Cell Address Hi-Z Data Output

Bus Write

V

IL

V

IH

V

IL

Command Address Hi-Z Data Input

Output Disable X

V

IH

V

IH

X Hi-Z Hi-Z

Standby

V

IH

X X X Hi-Z Hi-Z

Read Manufacturer
Code

V

IL

V

IL

V

IH

A0 = VIL,A1=VIL,A9=VID,
Others V

IL

or V

IH

Hi-Z 20h

Read Device Code

V

IL

V

IL

V

IH

A0 = VIH,A1=VIL,A9=VID,
Others V

IL

or V

IH

Hi-Z

D0h (M29F100BT)
D1h (M29F100BB)

Operation E G W

Address Inputs

A0-A15

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Bus Read

V

IL

V

IL

V

IH

Cell Address Data Output

Bus Write

V

IL

V

IH

V

IL

Command Address Data Input

Output Disable X

V

IH

V

IH

X Hi-Z

Standby

V

IH

X X X Hi-Z

Read Manufacturer
Code

V

IL

V

IL

V

IH

A0 = VIL,A1=VIL,A9=VID,
Others V

IL

or V

IH

0020h

Read Device Code

V

IL

V

IL

V

IH

A0 = VIH,A1=VIL,A9=VID,
Others V

IL

or V

IH

00D0h (M29F100BT)
00D1h (M29F100BB)

BUS OPERATIONS

There are five standardbusoperations that control
the device. These are Bus Read, Bus Write, Out­put Disable, Standby and Automatic Standby. See
Tables 4A and 4B, Bus Operations, for a summa­ry. Typically glitches of less than 5ns on Chip En­able or Write Enable are ignored by the memory
and do not affect bus operations.

Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com­mand Interface. A valid Bus Read operation in­volves setting the desiredaddress on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 7, Read Mode AC Waveforms,
and Table 11, Read AC Characteristics, fordetails
of when the output becomes valid.

Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad­dress Inputs. The Address Inputs are latched by
the Command Interface onthe falling edgeof Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com­mand Interface on the rising edge of Chip Enable
or Write Enable,whichever occursfirst.OutputEn­able must remain High, VIH, during the whole Bus
Write operation. See Figures 8 and 9, Write AC
Waveforms, and Tables 12 and 13, Write AC
Characteristics, for details of the timing require­ments.

Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.

M29F100BT, M29F100BB

6/21

Standby. When Chip Enable is High, VIH, the
Data Inputs/Outputs pins are placed in the high­impedance state and the Supply Current is re­duced to the Standby level.

When Chip Enable is at VIHthe Supply Current is
reduced to the TTL Standby Supply Current,I

CC2

.
To furtherreduce the SupplyCurrent tothe CMOS
Standby Supply Current, I

CC3

, ChipEnable should
be held within VCC± 0.2V. For Standby current
levels see Table 10, DC Characteristics.

During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I

CC4

, forProgram or Erase operationsun-

til the operation completes.
Automatic Standby. If CMOS levels (VCC± 0.2V)

are usedto drive thebus and the busis inactivefor
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re­duced tothe CMOS Standby Supply Current,I

CC3

.
The Data Inputs/Outputs will still output data if a
Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera­tions are intended for use by programming equip­ment and are not usually used in applications.
They require VIDto be applied to some pins.

Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 4A and 4B, Bus Operations.

Block Protection and BlocksUnprotection. Each
block can be separately protected against acci­dental Program or Erase.Protected blocks can be
unprotected to allow data to be changed.

There are two methods available for protecting
and unprotecting the blocks, one for use on pro­gramming equipment and the other for in-system
use. For further information refer to Application
Note AN1122, Applying Protection and Unprotec­tion to M29 Series Flash.

COMMAND INTERFACE

All Bus Write operations to the memory are inter­preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-

ations. Failure toobserve a valid sequence of Bus
Write operations will result in the memory return­ing to Readmode. The long command sequences
are imposed to maximize data security.

The address used for the commands changes de­pending on whether the memory is in 16-bit or 8­bit mode. See either Table 5A, or 5B, depending
on the configuration that is being used, for a sum­mary of the commands.

Read/Reset Command. The Read/Reset com­mand returns the memory to its Readmode where
it behaves like a ROM or EPROM. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.

If the Read/Reset command is issued during a
Block Erase operation orfollowing a Programming
or Erase errorthen the memory will take upto 10µs
to abort. During the abort period no validdata can
be read from the memory. Issuing a Read/Reset
command during a Block Erase operation will
leave invalid data in the memory.

Auto Select Command. The Auto Select com­mand is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re­quired to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until another com­mand is issued.

From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VILandA1 = VIL. The otheraddress bits
may be set to either VILor VIH. The Manufacturer
Code for STMicroelectronics is 0020h.

The Device Code can be read using a Bus Read
operation with A0 = VIHand A1 = VIL. The other
address bits may be set to either VILor VIH. The
Device Code for the M29F100BT is 00D0h and for
the M29F100BB is 00D1h.

The Block Protection Status of each block can be
read using a Bus Read operation with A0 = VIL,
A1 = VIH, and A12-A15 specifying the address of
the block. The other address bits may be set toei­ther VILor VIH. If the addressed block is protect­ed then 01h is output on Data Inputs/Outputs
DQ0-DQ7, otherwise 00h is output.

7/21

M29F100BT, M29F100BB

Table 5A. Commands, 16-bit mode, BYTE = V

IH

Table 5B. Commands, 8-bit mode, BYTE = V

IL

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A15, DQ8-DQ14 and DQ15 are Don’t Care.
DQ15A–1 is A–1 when BYTE is V

IL

or DQ15when BYTE is VIH.

Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, readManufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, BlockErase. After these commands read the Status Register until the Program/Erase

Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write
Operations until the Timeout Bit is set.

Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory asnormal until another command is issued.
Erase Suspend. After the EraseSuspend command readnon-erasing memory blocks as normal, issue AutoSelect and Program commands

on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/

Erase Controller completes and the memory returns to Read Mode.

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset

1X F0

3 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass

Program

2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset

1X F0

3 AAA AA 555 55 X F0
Auto Select 3 AAA AA 555 55 AAA 90
Program 4 AAA AA 555 55 AAA A0 PA PD
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass

Program

2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30