SGS Thomson Microelectronics M28W800CT, M28W800CB Datasheet

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FEATURES SUMMARY

■ SUPPLY VOLTAGE

–V –V –V

■ ACCE SS TIME: 70, 85, 90,10 0ns

■ PROGRAMMING TIME:

= 2.7V to 3.6V Core Power Supply

= 1.65V to 3.6V for Input/Output

DDQ

= 12V for fast Program (optional)

– 10µs typical – Double Word Programming Option

■ COMMON FLASH INTERFACE

– 64 bit Security Code

■ MEMORY BLOCKS

– Parameter Blocks (Top or Bottom location) – M ain Blocks

■ BLOCK LOCKING

– All blocks locked at Power Up – Any combinat ion of blocks can be locked

for Block Lock-Down

–WP

■ SECURITY

– 64 bit user Programmable OT P cells – 64 bit uniqu e device identifier – One Parameter Block Permanently Lo ckable

■ AUTOMAT IC S TAND-BY M ODE

■ PROGRAM and ERASE SUSPEND

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Top Device Code, M28W800CT: 88CCh – Bottom Device Code, M28W800CB: 88CDh

M28W800CT

M28W800CB

8 Mbit (512Kb x16, Boot Block)

3V Supply Flash Memory

Figure 1. Packages

FBGA

TFBGA46 (ZB)

6.39 x 6.37mm

TSOP48 (N)

12 x 20mm

1/49May 2002

M28W800CT, M28W800CB

TABLE OF CONTENTS

SUMMARYDESCRIPTION...........................................................5

Figure2.LogicDiagram ..........................................................5

Table 1. Signal Nam es . . . ........................................................5

Figure 3. TSOP Connections.......................................................6

Figure 4. TFBGA Connections (Top view through package). ..............................7

Figure5.BlockAddresses.........................................................8

Figure6.SecurityBlockandProtectionRegisterMemoryMap............................8

SIGNALDESCRIPTIONS............................................................9

AddressInputs(A0-A18)..........................................................9

Data Input/Output (DQ0-DQ15). . . ..................................................9

ChipEnable(E). ................................................................9

Output Enabl e (G). ..............................................................9

Write Enable (W). . ..............................................................9

WriteProtect(WP)...............................................................9

Reset(RP).....................................................................9

Supply Voltage..............................................................9

Supply Voltage.............................................................9

DDQ

ProgramSupplyVoltage ......................................................9

Ground. ...................................................................9

BUSOPERATIONS................................................................10

Read.........................................................................10

Write.........................................................................10

OutputDisable.................................................................10

Standby. . ....................................................................10

Automatic Standby. .............................................................10

Reset........................................................................10

Read Electroni c Signature Command ...............................................11

Table2.BusOperations.........................................................10

COMMANDINTERFACE ...........................................................11

ReadMemoryArrayCommand....................................................11

ReadStatusRegisterCommand...................................................11

Read Electroni c Signature Command ...............................................11

ReadCFIQueryCommand.......................................................11

BlockEraseCommand..........................................................11

ProgramCommand.............................................................11

Double Word Program Command . .................................................12

ClearStatusRegisterCommand...................................................12

Program/Erase Suspend Command ................................................12

Program/EraseResumeCommand ................................................12

ProtectionRegisterProgramCommand.............................................12

BlockLock-DownCommand......................................................13

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M28W800CT, M28W800CB

Table3.Commands ............................................................14

Table4.ReadElectronicSignature.................................................14

Table 5. Read Block Lock Signature ................................................15

Table6.ReadProtectionRegisterandLockRegister ..................................15

Table7.Program,EraseTimesandProgram/EraseEnduranceCycles ....................15

BLOCKLOCKING.................................................................16

Reading a Block’s Lock Status . . . .................................................16

LockedState..................................................................16

UnlockedState ................................................................16

Lock-DownState...............................................................16

LockingOperationsDuringEraseSuspend ..........................................16

Table8.BlockLockStatus.......................................................17

Table9.ProtectionStatus........................................................17

STATUSREGISTER...............................................................18

Program/EraseControllerStatus(Bit7).............................................18

Erase Suspend Status (Bit 6) .....................................................18

EraseStatus(Bit5).............................................................18

ProgramStatus(Bit4)...........................................................18

Status(Bit3)...............................................................18

ProgramSuspendStatus(Bit2)...................................................18

BlockProtectionStatus(Bit1).....................................................19

Reserved(Bit0)................................................................19

Table10.StatusRegisterBits.....................................................19

MAXIMUMRATING................................................................20

Table11.AbsoluteMaximumRatings...............................................20

DCandACPARAMETERS .........................................................21

Table 12. Operating and AC Measurement Conditions..................................21

Figure7.ACMeasurementI/OWaveform ...........................................21

Figure 8. AC Measurement Load Circuit . . . ..........................................21

Table 13. Capacitance...........................................................21

Table14.DCCharacteristics......................................................22

Figure9.ReadModeACWaveforms...............................................23

Table15.ReadACCharacteristics.................................................23

Figure 10. Write AC Waveforms, Write Enable Controlled . . .............................24

Table 16. Write AC Characteristics, Write Enable Co ntrolled .............................25

Figure11.WriteACWaveforms,ChipEnableControlled................................26

Table17.WriteACCharacteristics,ChipEnableControlled .............................27

Figure12.Power-UpandResetACWaveforms.......................................28

Table18.Power-UpandResetACCharacteristics ....................................28

PACKAGE MECHANICAL . . . .......................................................29

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M28W800CT, M28W800CB

Figure13.TSOP48-48leadPlasticThinSmallOutline,12x20mm,PackageOutline ........29

Table 19. TSOP48 - 48 lead Plas tic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 29 Figure 14. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline30 Table20.TFBGA466.39x6.37mm-8x6ballarray,0.75mmpitch,PackageMechanicalData...30

Figure 15. TFBGA46 Daisy Chain - Package Connections (Top view through package) ........31

Figure 16. TFBGA46 Daisy Chain - PCB Connections proposal (Top view through package ) ....31

PARTNUMBERING ...............................................................32

Table21.OrderingInformationScheme.............................................32

Table22.DaisyChainOrderingScheme............................................32

REVISIONHISTORY...............................................................33

Table23.DocumentRevisionHistory...............................................33

APPENDIX A. BLOCK ADDRES S T ABLES . . ..........................................34

Table 24. Top Boot Block Addresses, M28W800CT ....................................34

Table25.BottomBootBlockAddresses,M28W800CB.................................34

APPENDIXB.COMMONFLASHINTERFACE(CFI) .....................................35

Table26.QueryStructureOverview................................................35

Table 27. CFI Query Identification String . . ..........................................35

Table28.CFIQuerySystemInterfaceInformation.....................................36

Table29.DeviceGeometryDefinition...............................................37

Table 30. Primary Algorithm-Specific Extended Query Table .............................38

Table31.SecurityCodeArea.....................................................39

APPENDIX C. FLOWCHARTS AND PSEUDO CODES....................................40

Figure 17. Program Flowchart and Pseudo Code. . ....................................40

Figure 18. Double Word Program Flowchart and Pseudo Code ...........................41

Figure 19. Program Suspend & Resum e Flowchart and Pseudo Code .....................42

Figure 20. Erase Flowc hart and Pseudo Code ........................................43

Figure 21. Erase S us pend & Resume Flowchart and Pseudo Code. .......................44

Figure 22. Locking Operations Flowchart and Pseudo Code .............................45

Figure23.ProtectionRegisterProgramFlowchartandPseudoCode......................46

APPENDIXD.COMMANDINTERFACEANDPROGRAM/ERASECONTROLLERSTATE.......47

Table32.WriteStateMachineCurrent/Next,sheet1of2................................47

Table33.WriteStateMachineCurrent/Next,sheet2of2................................48

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SUMMARY DESCRIPTION

The M28W800C isa 8Mbit (512Kbit x16) non-volatileFlashmemorythatcanbeerasedelectrically at the block level and programmed in-system on a Word-by-Word basis. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. V

1.65V. An optional 12V V

allows to drive the I/O pin down t o

DDQ

power supply is pro-

vided to speed up customer programming. The device features an asymmetrical blocked ar-

chitecture. The M 28W800C has an array of 23 blocks: 8 Parameter Blocks of 4 KWord and 15 Main Blocks of 32 KWord. M28W800CT has the Parameter Blocks at the top of the memory address space while the M28W800CB locates the Parameter Blocks starting from the bottom. The memory maps are shown in Figure 5, Block Addresses.

The M28W800C features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an addi tional hardware protection against program and erase. When V

≤ V

all blocks are protected against

PPLK

program or erase. All blocks are l oc k ed at powerup.

Each block can be erased separately. Erase can be suspended in order to perform ei the r read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cy cles.

The device includ es a 128 bit Protection Register and a Security Block to increase the protection of a system desi gn. The Protection Register is divided into two 64 bit segments, the first one contains a unique device number writte n by ST, while the second one is one-time-programmable by the user. The user programmable segment can be permanently protected. The Security Block, parameter bl oc k 0, can be permanently protected by the user. Figure 6, shows the Security Block and Protection Register Memory Map.

Program and Erase c omm ands are written to the Command Interface of the memory. An on-chip Program/Erase Control ler takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

M28W800CT, M28W800CB

ThememoryisofferedinTSOP48(10X20mm) and TFBGA46 (6.39 x 6.37mm , 0.75mm pitch) packages and is supplied with all the bits erased (set to ’1’).

Figure 2. Logic Diagram

DDQVPP

A0-A18

M28W800CT M28W800CB

Table 1. Signal Names

A0-A18 Address Inputs DQ0-DQ15 Data Input/Output E G W RP WP V

DDQ

NC Not Connected Internally

Chip Enable Output Enable Write Enable Reset Write Protect Core Power Supply Power Supply for

Input/Output Optional Supply Voltage for

Fast Program & Erase Ground

DQ0-DQ15

AI03806

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M28W800CT, M28W800CB

Figure 3. TSOP Connections

A15 A14 A13 A12 A11

A16 V

DDQ

DQ15 DQ7

A10 DQ14

37 36

DQ6 DQ13 DQ5 DQ12 DQ4 V

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G V

E A0

NC NC

NC A18 A17

A9 A8

A7 A6 A5 A4 A3 A2 A1

M28W800CT M28W800CB

24 25

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AI03807

Figure 4. TFBGA Connections (Top view through package)

M28W800CT, M28W800CB

87654321

DDQ

DQ15

DQ7V

A8A11A13

DQ13

RP A18

DQ11

DQ12

DQ4

DQ2

A7V

DQ0DQ9DQ3DQ6

DQ1DQ10V

A2A5A17WA10A14

A1A3A6A9A12A15

A0EDQ8DQ5DQ14A16

AI03805

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M28W800CT, M28W800CB

Figure 5. Block Addresses

M28W800CT

Top Boot Block Addresses

7FFFF

7F000

78FFF

78000

77FFF

70000

0FFFF

08000

07FFF

00000

4 KWords

32 KWords

Total of 8

4 KWord Blocks

Total of 15

32 KWord Blocks

M28W800CB

Bottom Boot Block Addresses

7FFFF

78000

77FFF

70000

0FFFF

08000

07FFF

07000

00FFF

00000

32 KWords

4 KWords

Total of 15

32 KWord Blocks

Total of 8

4 KWord Blocks

AI04385

Note: Also see Appendix A, Tables 24 and 25 for a full listing of the Block Addresses.

Figure 6. Security Block and Protection Reg ister Memory Map

PROTECTION REGISTER

SECURITY BLOCK

Parameter Block # 0

88h

85h 84h

81h 80h

User Programmable OTP

Unique device number

Protection Register Lock 2 1 0

AI03523

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SIGNAL DESCRIPTIONS

See Fig ure 2 Logic Diagram and T able 1,Signal Names, f or a briefoverview of thesignals connected to this device.

Address Inputs (A0-A18). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at t he s elected address during aBus Read operation or inputsa command orthedatatobeprogrammedduringaWriteBus operation.

Chip Enable (E

). The Chip Enable input acti-

vates the memory co ntrol logic, input buffers, decoders andsense amplifiers. When ChipEnable is

and Reset is at VIHthe device is in active

at V

mode. When Chip Enable is at V

the memory is

deselected, the outputs are high impedan ce and the power consumption is reduced to the stand-by level.

Output Enable (G

). The Output Ena ble controls

data outputs during the Bus Read operation of the memory.

WriteEnable(W

). Th e Write Enable controls the

Bus Write operation of the memory’s Command Interface. Thedata and address inputs are latched ontherisingedgeofChipEnable,E,orWriteEnable, W

Write Protect (W P

, whichever occurs f irst.

). Write Protect i s an input that gives an additional ha rdware protection for each block. When Write Protect is at V

, the Lock-

Down is enabled and the protection status of the block cannot bechanged. When WriteProtect isat V

, the Loc k -Down is disabled and the block can

be locked or unlocked. (referto Table 6, Read Protection Register and Protection Register Lock).

Reset (RP

wareresetofthememory.WhenResetisatV

). The Reset input provides a hard-

the memory is in reset mode: the outputs are high impedance and the current consum pti on is minimized. After Reset all blocks are in the Locked

M28W800CT, M28W800CB

state. WhenReset isat V operation. Exiting reset mode the device enters read array mode, but a negative trans ition of Chip Enable or a change of the address is required to ensure valid data outputs.

Supply Voltage. VDDprovides the power

supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Eras e).

Supply Voltage. V

DDQ

power supply to the I/O pins and enables al l Outputs tobe powered independentlyfrom V canbetiedtoVDDor can use a s eparate supply.

Program Supply Voltage. VPPis both a

control input and a power supply pin. The two functions are selected by the voltage range applied t o the pin. The Supply V olt age V Program Supply Voltage V anyorder.

is kept in a low voltage range (0V to 3.6V)

If V

is seen as a control input. In this case a volt-

age lowerthan V

PPLK

against program or erase, while V ables these functions (see Table 14, DC Charac teristics for the relevant values). V sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effectand program or eraseoperations continue.

is in the range 11.4V to 12.6V it acts as a

If V

power supply pin. In this cond ition V stable until the Program/Erase al gorithm is completed (see Table 16 and 17).

Ground. VSSis the reference for all voltage

measurements.

Note: Each device in a system should have V

DD,VDDQ

and VPPdecoupled with a 0.1µF capacitor close to the pin. See Figure 8, AC M easurement Load Circu it. Th e PCB trace widths

should be sufficient to carry the required V program and erase currents.

, thedevice isin normal

DDQ

provides the

canbeappliedin

gives an absolute protection

DD.VDDQ

and the

PP1

is only

must be

en-

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M28W800CT, M28W800CB

BUS OPERATIONS

There are six standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby, Aut omatic Standby and Reset. See Table 2, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chip Enable or Write Enable are ignoredby the memory and do not affect bus operations.

Read. Read B us opera tions are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output E nablemustbeatV eration. The Chip Enable input sh ould be used to enable the device. Output Enable should be used to gat e data onto the output. The data r ead depends on the previous command written to the memory (see Command Interface section). See Figure 9, Read Mode AC Waveforms, and Table 15, Read AC Characteristics, for details of when the output becomes valid.

Read mode is the default state of the device when exiting Reset or after power-up.

Write. B us Write ope rations write Commands to the mem ory or latchInput Data tobe programmed. A write operation is initiated when Chip Enable and Write Enable are at V

. Commands, Input Data and Addresses are

latched on the rising edge of Write Enable or Chip Enable, whichever occurs first.

in order t o perform a read op-

with Output Enable at

See Figures 10 and 11, Write AC Waveforms, and Tables 16 and 17, Write AC Characteristics, for details of the timing requirements.

Output Disable. The data outputs are high impedance when t he Output Enable is at V

Standby. Standby disables most of the internal circuitryallowing a substantialreduction of the c urrent consumption. The memory is in st and-by when Chip Enable is at V

andthedeviceisin

read mode. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently f rom the OutputEnable or Write Enable inputs. If Chip Enable switches to V

during a program or erase operation, the de-

vice enters Standby mode when finished. Automatic Standby. Autom atic Standby pro-

vides a low power consumpt ion state during Read mode. Following a read operation, the device enters Automatic Standby after 150ns of bus inactivity even if Chip Enable is Low, V current is reduced to I

. The data Inputs/Out-

DD1

, and the supply

puts will still output data if a bus Read operation is in progress.

Reset. Durin g Reset mode when Output Ena ble is Low, V

, the m emory is deselected and the out-

puts are high impedance. The memory is in Reset mode when Reset is at V

. The power cons ump-

tion is reduced to theStan dby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to V

during a Pro-

gram or Eras e, this operation is aborted and the memory content is no longer valid.

Table 2. Bus Operations

Operation E G W RP WP

Bus Read Bus Write Output Disable Standby Reset X X X

Note: X = VILor VIH,V

10/49

V V V

=12V±5%.

PPH

X Don't Care Data Output

X X Don't Care Hi-Z X Don't Care Hi-Z X Don't Care Hi-Z

or V

PPH

DQ0-DQ15

Data Input

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Com mands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all t imings and verifies the correct execution of the Program and Erase c ommands. The Program/Erase Cont roll er provides a Status Register whose output may be r ead at any time during, to monitor the progress of the operation, or the Program/Erase states. See Appendix 21, Table 32, Write State Machine Current/Next, for a summary of the Command Interface.

The Command Interface is res et to Read mode when power is first applied, when exiting from Reset or whenever V

is lower than V

LKO

.Command sequences must be followed exactly. Any invalid c ombination ofcommands willreset the device to Read mode. Refer to Table 3, Commands, in conjunction with the text descriptions below.

Read Memory Array Command

TheReadcommandreturnsthememorytoits Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent read operations will read the addressed location and output the data. When a device Reset oc c urs, the memory defaults to Read mode.

Read Status Register Co m m and

The Status Register indi cates when a program or erase operation is complete and the success or failure of the operation itself. Issue a Read Status Register comma nd to rea d the Stat us Register’s contents. Subsequent Bus Read operations read the Status Register at any address, until another command isissued. See Tabl e 10, Status Register Bits, for details on the definitions of the bits.

The Read Status Regi ster command may be issued at any time, ev en during a Program /Erase operation. Any Read atte mpt during a Program/ Erase op eration will automatically output the content of the Stat us Register.

Read Electronic Signature Command

The Read Electronic Signature command reads the Manufacturer and DeviceCodes and theBlock Locking Status, or the Protection Register.

The Read Electronic Signat ure command consists of one write cycle, a subsequent read will output the Manufacturer Code, the Device Code, the Block Lock and Lock-Down Status, or the Protection and Lock Register. See Ta bles 4, 5 and 6 for the valid address.

Read CFI Query Command

The Read Query Comm and is used to read data from the Com mo n Flash Interface (CFI) Memory Area, allowing programming equi pment or ap pli-

M28W800CT, M28W800CB

cations to automatically match their interface to the characteristics of the device. One Bus Write cycle is required to issue the Read Query C ommand. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. See Appendix B, Common Fl as h Interface, Tables 26, 27, 28, 29, 30 and 31 for details on the information contained in the Common Flash Interface memory area.

Block Erase Command

TheBlockErasecommandcanbeusedtoerase a block. It setsall the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the Erase operation w ill abort, the data inthe block willnot be changed and the Status Register will output the error.

Two Bus Write cycles are required to issue the command.

■ Th e first bus cyclesets up the Erase c ommand.

■ Th e s econd latches the block address in the

internal state machine and starts the P ro gram/ Erase Controller.

If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts.

Erase aborts if Reset turns to V cannot beguaranteed when theErase operation is aborted, the block must be erased again.

During Erase operations the memory will accept the Read Status Register command and the Program/Erase Suspend command, all other commands will be ignored. Typical Erase times are given in Table 7, Program, E ras e Times and Program/Erase Endurance Cycles.

See Appendix C , Figure 20, Erase Flowchart and Pseudo Code, for a suggested flowchart for using the Erase command.

Program Command

The memory array can be programmed word-byword. Two bus write cycles are required to issue the Program Command.

■ Th e first bus cycle s ets up the Program

command.

■ Th e secondlatches theAddress andthe Datato

be written and star ts the Program/Erase Controller.

During Program operations the memory will accept the Read S tatus Register command and the Program/Erase Suspend c ommand. Typical Program t im es are given in Table 7, Program, Erase Times and Program/E r as e E ndurance Cycles.

Programming aborts if Reset goes to V integrity cannot be guaranteed when the program operation is aborted, the block containing the

. As dat a integ rity

. As data

11/49

M28W800CT, M28W800CB

memory location must be erased and reprogrammed.

See Appendix C, Figure 17 , Program Flowchart and Pseudo Code, for the flowchart for using the Program comman d.

Double Word Program Command

Thisfeat ure isoffered toimprove the programming throughput, writing a page of two adjacent words in parallel.The two words must differ only for the address A0. Programming should not be attempted when V executed if V

isnot atV

is below V

PPH

. The c ommand can be

but the result is not

PPH

guaranteed. Three bus write cycles are neces sary to issue the

Double Word Program c ommand.

■ Th e f irst bus cycle sets up the Double Word

Program Command.

■ The second bus cycle latches the Address and

theDataofthefirstwordtobewritten.

■ The third bus cyclelatches the Address and the

Data of the second word to bewritten and st arts the Program/Erase Controlle r.

Read operations out put the Status Register content after the programming has started. Programming aborts if Reset goes to V

. As data integrity

cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed.

See Appendix C, Figure 18, Double Word Program Flowchart and Pseudo Code, for the flowchart for using the Double Word Program command.

Clear Status Register Command

The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 i n the Status R egister to ‘0’. One bus write cycle is required to issue the Clear Status Register command.

The bits in the Status Register do not automatically return t o ‘0’ when a new Program or Erase command is issued. Th e error bits in the Status Register should be cleared before attempting a new Program or Erase command.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to pause a Pr ogram or Erase operation. One bus write cycle is required to issue the Program/Erase command and pause the Program/Erase cont roller.

During Program/Erase Suspend theCommand Interface will accept the Program/Erase Resume, Read A rray , Read StatusRegister, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Program, Block Lock, Block Lock-Down or Protection Program commands will also be ac-

cepted. The block being erased may be protected by issuing the Block Protect, BlockL oc k or Protection Program commands. When the Program/ Erase Resume command is issued the operation will complete. Only the blocks not being erased may be read or programmed correctly.

During a Program/Erase Su sp end, the device can be placed in a pseudo-standby mode by taking Chip Enable to V Reset turns to V

. P rogram/Erase is abort ed if

See A ppendix C, Figure 19, Program or Double Word Program Suspend & Resume Flowchart and Pseudo Code, and Figure 21, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts forusing the Program/Erase Suspend command.

Program/Erase Resume Command

The Program/Erase Resume command can be used to restart the Program/Eras e Controller after a Program/Erase Suspend operation has paused it. One Bus W rite cycle is required to issue the command. Once the command is issued subsequent Bus Read operations read the Status Register.

Protection Register Program Command

The Protection Register P rogram command is used to P rogram the 64 bit user One-Time-Programmable (OTP) segment of the Protection Register. The segment is program med 16 bits at a time. When shipped all bits in the segm ent are set to ‘1’. The user can onlyprogram the bits to ‘0’.

Two write cycles are required to issue the Protection Register Program command.

■ Th e first bus cycle s ets up the Prot ec ti on

■ Th e secondlatches theAddress andthe Datato

be written to the Protection Register and starts the Program/Erase Controlle r.

Read operations out put the Status Register content after the programming has started.

The segment can be protected by program mi ng bit 1 of the Protection Loc k Register. Bit 1 of the Protection Lock Register protects bit 2 of the Protection Lock Register. Programming bit 2 of the Protection Lock Register wi ll result in a permanent protection of the Security Block (see Figure 6 , Security Block and Protection Register Memory Map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection

12/49

M28W800CT, M28W800CB

The Protection Register Program cannot be suspended. See Appendix C, Figure 23, Protection Register Program Flowchart and P s eudo Code, for the flowchart for using the Protection Register Program comman d.

Block Lock Command

The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are lock ed at power-up or reset.

Two Bus Write cycles are required to issue the Block Lock comm and.

■ Th e first bus cycle s ets up the Block Lock

command.

■ The second Bus Write cycle latches the block

address.

The lock status c an be monitored f or each block using the Read E lectronic Signature command. Table. 9 shows the protection statu s after issuing a Block Lock command.

The Block Lock bits are volatile, once set they remain set until a hardware reset or power-down/ power-up. They are cleared by a Blocks Unlock command. Refer to the section, Block Lo cking, for a detailed explanatio n.

Block Unlock Command

The Blocks Unlock command is used to u nlock a block, allowing the block to be programmed or

erased. Two Bus Write cy cles are required to issue the Blocks Unl ock command.

■ Th e first bus cycle s ets up the Block Unlock

command.

■ The second Bus Write cycle latches the block

address.

The lock status c an be monitored f or each block using the Read E lectronic Signature command. Table. 9 shows the protection statu s after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation.

Block Lock-Down Command

A locked block cannot be Programmed or Erased, or have its protection status changed when WP low, V

.WhenWPis high, V

the Lock-Down

IH,

function is disabled and the locked blocks can be individually unlocked by the Block Unlo ck command.

Two Bus Write cycles are required to issue the Block Lock-Down com mand.

■ Th e first bus cycle s ets up the Block Lock

command.

■ The second Bus Write cycle latches the block

address.

The lock status c an be monitored f or each block using the Read E lectronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table. 9 shows the protection status after issuing a Block Lock-Down command. Refer to the section, Block Locking, for a detai led explanation.

13/49

M28W800CT, M28W800CB

Table 3. Commands

Bus Write Operations

(3)

No. of

Cycles

3 Write X 30h Write Addr 1

Commands

Read Memory Array 1+ Write X FFh

Read Status Register 1+ Write X 70h

Read Electronic Signature 1+ Write X 90h

Read CFI Query 1+ Write X 98h Read CFI Addr Query

Erase 2 Write X 20h Write

Program 2 Write X

Double Word Program

Clear StatusRegister 1 Write X 50h Program/Erase Suspend 1 Write X B0h Program/Erase Resume 1 Write X D0h

Block Lock 2 Write X 60h Write

1st Cycle 2nd Cycle 3nd Cycle

Bus

Op.

Addr Data

40h or

10h

Bus

Op.

Read

Write Addr

Addr Data

Read

Addr

Signature

Addr

Block

Addr

Block

Address

(2)

Data

Status

Signature

D0h

Data Input

01h

Bus

Op.

Write Addr 2

Addr Data

Data Input

Block Unlock 2 Write X 60h Write

Block Lock-Down 2 Write X 60h Write

Protection Register Program

Note: 1. X = Don't Care.

2. The signature addresses are listed in Tables 4, 5 and 6.

3. Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.

2 Write X C0h Write

Block

Address

Block

Address

D0h

2Fh

Data Input

Table 4. Read Electronic Signature

Code Device E G W A0 A1 A2-A7 A8-A18 DQ0-DQ7 DQ8-DQ15

Manufacture. Code

M28W800CT

Device Code

M28W800CB

Note: RP =VIH.

ILVIH

IHVIL

0 Don't Care 20h 00h

0 Don't Care CCh 88h 0 Don't Care CDh 88h

14/49

M28W800CT, M28W800CB

Table 5. Read Block Lock Signature

Block Status E G W A0 A1 A2-A7 A8-A11 A12-A18 DQ0 DQ1 DQ2-DQ15

Locked Block Unlocked Block Locked-Down

Block

Note: 1. A Locked-Down Block can be locked "DQ0 = 1" or unlocked "DQ0 = 0"; see Block Locking section.

ILVILVIHVILVIH

VILVILVIHVILV

ILVILVIHVILVIH

0 Don't Care Block Address 1 0 00h 0 Don't Care Block Address 0 0 00h

0 Don't Care Block Address

Table 6. Read Pr otecti on Register and Lock Register

Word E

Lock

Unique ID 0 Unique ID 1 Unique ID 2 Unique ID 3 OTP 0 OTP 1 OTP 2 OTP 3

G W A0-A7 A8-A18 DQ0 DQ1 DQ2 DQ3-DQ7 DQ8-DQ15

ILVILVIH

VILVILV V

ILVILVIH

80h Don'tCare 0

OTP Prot.

data 81h Don't Care ID data ID data ID data ID data ID data 82h Don't Care ID data ID data ID data ID data ID data

83h Don't Care ID data ID data ID data ID data ID data 84h Don't Care ID data ID data ID data ID data ID data 85h Don't Care OTP data OTP data OTP data OTP data OTP data 86h Don't Care OTP data OTP data OTP data OTP data OTP data 87h Don't Care OTP data OTP data OTP data OTP data OTP data 88h Don't Care OTP data OTP data OTP data OTP data OTP data

Security

prot. data

(1)

00h 00h

1 00h

Table 7. Pro gram, Erase Times and Program/Erase Endurance Cycles

Parameter Test Conditions

Word Program Double Word Program

Main Block Program

Parameter Block Program

Main Block Erase

Parameter Block Erase

PP=VDD

=12V±5%

PP=VDD

=12V±5%

PP=VDD

=12V±5%

PP=VDD

=12V±5%

PP=VDD

Program/Erase Cycles (per Block) 100,000 cycles

M28W800C

Unit

Min Typ Max

10 200 µs 10 200 µs

0.16 5 s

0.32 5 s

0.02 4 s

0.04 4 s 110 s 110 s

0.8 10 s

15/49

M28W800CT, M28W800CB

BLOCK LOCKING

The M28W800C features an instant, individual block locking scheme that allows any block to be lockedorunlockedwithnolatency.Thislocking scheme has three levels of protection.

■ Lock/Unlock - this first level allows software-

only control of block locking.

■ Lock-Down - this second level requires

hardware interaction before locking can be changed.

■ V

Thelockstatusofeachblockcanbesetto Locked, Unlocked, and Lock-Down. Table 9, defines all of the possible protection states (W P DQ1, DQ0), an d Appendix C, Figure 22, shows a flowchart for the loc k ing operations.

ReadingaBlock’sLockStatus

The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subsequent reads at the address specified in Table 5, will output the lock status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set w hen enteringLock-Down.DQ 1 indicates theLock-Down status and is set by the Lock-Down command. It cannot becle ared by software, only by a hardware reset or power-down.

The following sections explain the operat ion of the locking system.

Locked State

The default status of all blocks on power-up or a fter a hardware reset is Locked (states (0,0,1) or (1,0,1)). L oc ked block s are fully protected from any program orerase. Any program orerase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software commands.An Unlocked block can beLocked byissuing the Lock c ommand.

Unlocked State

Unlocked b lock s (states (0,0,0), (1,0,0) (1,1, 0)), can be programmed or erased. All unlocked blocks returnto the Locked state after a hardware reset or when the device is powered-down. The status of an unlocked bloc k can be changed to Locked or Locked-Down using the appropriate

≤ V

- the third level offers a complete

PPLK

hardware protec tion against programand erase on all blocks.

software commands. A locked block can be unlocked by issuing the Unlock command.

Lock-Down State

Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their lock status cannot be changed using software commands alone. A Lockedor U nlocked blockcanbe Locked-Downby issuing the Lock-Dow n command. L ocke d-Down blocks revert to the Locked state when the device is reset or powered-down.

The Loc k-Do wn function is dependent on t he WP input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When

=1 (VIH) the Lock-Down function is disabled

WP (1,1,1) and Loc k ed-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, w here they canbe erasedand programmed. These blocks can then be relocked (1,1,1) and unlocked (1,1,0) as desired wh ile WP remains hig h. When WP is low , blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WP

was high. Device reset or power-down resets allblocks , including those in Lock-Down, to the Locked state.

Locking Operation s During Erase Suspend

Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress.

To change block locking during an erase operation, first write the Erase Suspend command, then check the status register until it indic ates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the protection status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command.

If a block is locked or locked-down duringan erase suspend of the same block, the locking status bits will be changed immediately, but w hen the erase is resumed, the erase operation will complete.

Locking operations cannot be performed during a program su sp end. Refer to Appendix D, Command Interface and Program/Erase Controller State, for detailed information on which commands are valid during erase suspend.

16/49

Table 8. Block Lock Status

Item Address Data

M28W800CT, M28W800CB

Block Lock Configuration

LOCK

Block is Unlocked DQ0=0

xx002

Block is Locked DQ0=1

Block is Locked-Down DQ1=1

Table 9. Protection Status

Protection Status

(WP, DQ1, DQ0)

Current State

Current

Program/Erase

(1)

Allowed

After

Block Lock

Command

Next Protection Status

(WP, DQ1, DQ0)

After

Block Unlock

Command

1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0

1,0,1

(2)

no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1

0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0

0,0,1

(2)

no 0,0,1 0,0,0 0,1,1 1,0,1 0,1,1 no 0,1,1 0,1,1 0,1,1

Note: 1. The protection status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block)

as read in the Read Electronic Signature command with A1 = V

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP

3. A WP

transition to VIHon a locked block will restore the previous DQ0 value, giving a 111 or 110.

andA0=VIL.

(1)

After Block

Lock-Down

Command

status.

After

transition

1,1,1 or 1,1,0

(3)

17/49

M28W800CT, M28W800CB

STATUS REGISTER

The Stat us Register provides information on t he current or previous Program or Erase operation. The various bits convey information and errors on the operation. To read the Status register the Read S t atu s Register commandcan be issued,refer to Read Status Register Command section. To output the contents, the Status Register is latched on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to V able or Output Enable must be toggled to update the latched data.

Bus R ead operations from any address always read the Status Register during Program and Erase operations.

The bits in the Status Register are summarized in Table 10, Status Regist er Bits. Refer to Table 10 in conjunction with the following text descriptions.

Program/Erase Controller Status (Bit 7). The Program/Erase Controller Status bit indi cates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is Low (set to ‘0’), the Program/Erase Controller is active; when the bit i s High (set to ‘1’), the Program/Erase Controller is inactive, and the device is ready to process a new command.

The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Cont roller pauses. After the Program/Erase Controller pauses the bit is High .

During Program, Erase, operations the Program/ EraseControllerStatusbitcanbepolledtofindthe end of the operation. Other bit s in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High.

After the Program/Erase Controller completes its operation the Erase Status, Program Status, V Status andBlock Lock Status bitsshould be tested for errors.

Erase Suspend Status (Bit 6). T he Erase Suspend Status bit indicates that an Erase operation has been suspended or is going to be suspended. When the Erase Suspend Status bit isH igh (set to ‘1’), a Program /Erase Suspend comman d has been issued and the memory is waiting for a Program/Erase Resume command.

The Erase Suspend Status should only be considered valid when the Program/Erase ControllerStatus bitis High (Program/Erase Controller inactive). Bit 7 is set within 30µs of the Program/Erase Sus pend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode.

. Either Chip En-

When a Program/Erase Resume command is issued the Erase Suspend Status bit re turns Low.

Erase Status (Bit 5). The EraseStatus bit ca n be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase Status bit i s High (set to ‘1’), the Program/ Erase Controller has applied the maximum number of pulses to the block and still failed to verify thatthe block haserased correctly.The Erase Status bit s hould be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive).

Once setHigh, the Erase Status bitcan only be reset Low by a Clear Status Re giste r command or a hardware reset. If set High it should be reset before a new Program or Eras e command is issued, otherwise the new command will appear to fail.

Program Status (Bit 4). The Program St atu s bit is used to identify a Program failure. When the Program Status bi t is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive).

Once set High, the Program Status bit can only be reset Low by a Clear Status Register comm and or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail.

Status (Bit 3). The VPPStatus bit can be

used to identify an invalid voltage on the V during Program and Eras e operations. The V

pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if V

When theV age on theV when theV

becomes invalid during an operat ion.

Status bitis Low (set to ‘0’),the volt-

pin wassampled at avali d voltage;

Status bit is High (set to‘1’), the V

pin has a voltage th at is below the VPPLockout Voltage, V

, the memory is protected and Pro-

PPLK

gram and Erase operations cannot be performed. Onceset High, the V

Status bitcan onlybe reset

Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Eras e command is issued, otherwise the new command will appear to fail.

Program Suspend Status (Bit 2). The Program Suspend Status bit indicates that a Program operation has been suspended. When the Program Suspend Status bit is High (set to ‘1’), a Program/ Erase Suspend command has been issued and the memory is waitin g f or a Program/Erase Resume command. The Program Suspend Status should only be considered valid when the Pro-

18/49

M28W800CT, M28W800CB

gram/Erase ControllerStatus bit is High (Program/ Erase Controller inactive). Bit2 is set within 5µs of the Program/Erase Suspen d command being issued therefore the memory may still complete the operation rather than entering the Suspend mode.

When a Program/Erase Resume command is issued t he Program Suspend S tatus bitreturns Low.

Block Protection Status (Bit 1). The Block ProtectionStatusbitcanbeusedtoidentifyifaProgram or Erase operation has tried to modify the contents of a locked block.

When the B lock Protection Status bit is High (set to ‘1’), a Program or Erase operation has b een attemptedonalockedblock.

Once set High, the Block Protection Status bi t can only be resetL ow by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail.

Reserved (Bit 0). Bit 0 of the Status Register is reserved. Its value must be masked.

Note: Refer to Appendix C, F lowch arts and Pseudo Codes, for u sing the Status Register.

Table 10. Status Register Bits

Bit Name Logic Level Definition

7 P/E.C. Status

6 Erase Suspend Status

5 Erase Status

4 Program Status

'1' Ready '0' Busy '1' Suspended '0' Inprogress or Completed '1' Erase Error '0' Erase Success '1' Program Error '0' Program Success

Status

2 Program Suspend Status

1 Block Protection Status

0 Reserved

Note: Logic level '1' is High, '0' is Low.

'1' '0' '1' Suspended '0' InProgress or Completed '1' Program/Erase on protected Block, Abort '0' Nooperation to protected blocks

VPPInvalid, Abort

19/49

M28W800CT, M28W800CB

MAXIMUM RATING

Stressingthedeviceabovetheratinglistedinthe Absolute Maximum Ratings table may c ause permanent damage to the device. These are stress ratings onlyand operation of the device at theseor any other conditions above those indicated in t he Operating sections of this specif ication is not im-

Table 11. Abso lu te Maximum Ratings

Symbol Parameter

BIAS

STG

DD,VDDQ

Note: 1. Depends on range.

Ambient Operating Temperature Temperature Under Bias – 40 125 °C Storage Temperature – 55 155 °C Input or Output Voltage – 0.6 Supply Voltage – 0.6 4.1 V Program Voltage – 0.6 13 V

(1)

plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality doc uments.

Value

Min Max

–40 85 °C

+0.6

DDQ

Unit

20/49

DC AND AC PARAMETERS

This s ec t ion summ arizes the operating and measurement condit ions, and the D C and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests perform ed under the Measure-

ment Conditions summari ze d in Table 12, Operating and AC Meas urement Conditions. Designers should check that the operating conditions in their circuit match the measureme nt conditions when relying on the quoted parameters.

Table 12. Operating and AC Measuremen t Conditions

M28W800CT, M28W800CB

Parameter

70 85 90 100

Min Max Min Max Min Max Min Max

Supply Voltage

Supply Voltage (V

DDQ

≤ V

2.7 3.6 2.7 3.6 2.7 3.6 2.7 3.6 V

2.7 3.6 2.7 3.6 2.7 3.6 1.65 3.6 V

)

Ambient Operating Temperature – 40 85 – 40 85 –40 85 – 40 85 °C Load Capacitance (C

)

50 50 50 50 pF Input Rise and Fall Times 5 5 5 5 ns Input Pulse Voltages Input and Output Timing Ref.

Voltages

0toV

DDQ

/2 V

0toV

DDQ

/2 V

0toV

DDQ

/2 V

0toV

DDQ

Figure 7. AC Measurement I/O Waveform Figure 8. AC Measurement Load Circuit

DDQ

AI00610

DDQ

25kΩ

Units

DEVICE UNDER

TEST

0.1µF

CL includes JIG capacitance

Table 13. Capacitance

Symbol Parameter Test Condition Min Max Unit

OUT

=0V

6pF

12 pF

OUT

Note: Sampled only, not 100% tested.

Input Capacitance Output Capacitance

25kΩ

AI00609C

21/49

M28W800CT, M28W800CB

Table 14. DC Ch aracteristics

Symbol Parameter Test Condition Min Typ Max Unit

DD1

DD2

DD3

DD4

DD5

PP1

PP2

PP3

PP4

PP1

PPH

PPLK

LKO

Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Stand-by or

Automatic Stand-by) Supply Current

(Reset)

Supply Current (Program)

Supply Current (Erase)

Supply Current (Program/Erase Suspend)

Program Current (Read or Stand-by)

Program Current (Reset)

Program Current (Program)

Program Current (Erase)

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage Program Voltage (Program or

Erase operations) Program Voltage

(Program or Erase operations)

Program Voltage (Program and Erase lock-out)

VDDSupply Voltage (Program and Erase lock-out)

0V≤ V

=VSS,G=VIH,f=5MHz

Program in progress

Erase in progress

Erase suspended

Program in progress

Erase in progress

= 100µA, VDD=VDDmin,

DDQ=VDDQ

= –100µA, VDD=VDDmin,

DDQ=VDDQ

≤ V

DDQ

≤ V

OUT≤VDDQ

DDQ

±0.2V,

± 0.2V

=VSS± 0.2V

=12V±5%

PP=VDD

=12V±5%

PP=VDD

DDQ

PP>VDD

≤ V

±0.2V,

=VSS± 0.2V

=12V±5%

PP=VDD

=12V±5%

PP=VDD

≥ 2.7V

DDQ

≥ 2.7V 0.7 V

DDQ

min

±1 µA

±10 µA

10 20 mA 15 50 µA

15 50 µA

10 20 mA

520mA

50 µA

400 µA

5µA 5µA

10 mA

5µA

10 mA

5µA

–0.5 0.4 V –0.5 0.8 V

–0.4 V

DDQ

DDQ DDQ

+0.4 +0.4

0.1 V

–0.1

DDQ

1.65 3.6 V

11.4 12.6 V

V V

22/49

Figure 9. Read M ode AC Waveforms

M28W800CT, M28W800CB

tAVAV

A0-A18

tAVQV

tELQX

tGLQX

DQ0-DQ15

ADDR. VALID

CHIP ENABLE

Table 15. Read AC Characteristics

Symbol Alt Parameter

AVAV

AVQV

AXQX

EHQX

EHQZ

ELQV

ELQX

GHQX

GHQZ

GLQV

GLQX

Note: 1. Sampled only, not 100% tested.

2. G

Address Valid to Next Address Valid Min 70 85 90 100 ns

Address Valid to Output Valid Max 70 85 90 100 ns

ACC

(1)

Address Transition to Output Transition Min 0 0 0 0 ns

(1)

Chip Enable High to Output Transition Min 0 0 0 0 ns

(1)

Chip Enable High to Output Hi-Z Max 20 20 25 30 ns

(2)

Chip Enable Low to Output Valid Max 70 85 90 100 ns

(1)

Chip Enable Low to Output Transition Min 0 0 0 0 ns

(1)

Output Enable High to Output Transition Min 0 0 0 0 ns

(1)

Output Enable High to Output Hi-Z Max 20 20 25 30 ns

(2)

Output Enable Low to Output Valid Max 20 20 30 35 ns

(1)

Output Enable Low to Output Transition Min 0 0 0 0 ns

OLZ

maybe delayed by up to t

ELQV-tGLQV

after the falling edge of E without increasing t

tELQV

tGLQV

OUTPUTS ENABLED

VALID

tEHQX

tEHQZ

tGHQX

tGHQZ

VALID

DATA VALID STANDBY

M28W800C

70 85 90 100

ELQV

tAXQX

AI03808b

Unit

23/49

M28W800CT, M28W800CB

Figure 10. Write AC Waveforms, Write Enable Controlled

AI03809b

tWHAX

PROGRAM OR ERASE

tAVAV

VALIDA0-A18

tAVWH

tWHGL

tELQV

tWHEL

tQVWPL

STATUS REGISTER

tQVVPL

READ

1st POLLING

STATUS REGISTER

OR DATA INPUT

24/49

tELWL tWHEH

tVPHWH

SET-UP COMMAND CONFIRM COMMAND

tWPHWH

tWHWL

tWHDXtDVWH

tWLWH

DQ0-DQ15 COMMAND CMD or DATA

Table 16. Write A C Characteristics, Write Enable Controlled

Symbol Alt Parameter

AVAV

AVWH

DVWH

ELWL

ELQV

QVVPL

QVWPL

VPHWH

WHAX

WHDX

WHEH

WHEL

WHGL

WHWL

WLWH

WPHWH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V

(1,2)

(1)

Write Cycle Time Min 70 85 90 100 ns

Address Valid to Write Enable High Min 45 45 50 50 ns

Data Valid to Write Enable High Min 45 45 50 50 ns

Chip Enable Low to Write Enable Low Min 0 0 0 0 ns

Chip Enable Low to Output Valid Min 70 85 90 100 ns Output Valid to VPPLow

Min 0 0 0 0 ns

Output Valid to Write Protect Low Min 0 0 0 0 ns

VPSVPP

High to Write Enable High

Min 200 200 200 200 ns

Write Enable High to Address Transition Min 0 0 0 0 ns Write Enable High to Data Transition Min 0 0 0 0 ns Write Enable High to Chip Enable High Min 0 0 0 0 ns Write Enable High to Chip Enable Low Min 25 25 30 30 ns Write Enable High to Output Enable Low Min 20 20 30 30 ns

Write Enable High to Write Enable Low Min 25 25 30 30 ns

WPH

Write Enable Low to Write Enable High Min 45 45 50 50 ns

Write Protect High to Write Enable High Min 45 45 50 50 ns

is seen as a logic input (VPP<3.6V).

M28W800CT, M28W800CB

M28W800C

Unit

70 85 90 100

25/49

M28W800CT, M28W800CB

Figure 11. Write AC Waveforms, Chip Enable Controlled

AI03810b

tEHAX

PROGRAM OR ERASE

tAVAV

VALIDA0-A18

tAVEH

tEHGL

tELQV

tQVWPL

CMD or DATA STATUS REGISTER

tQVVPL

READ

1st POLLING

STATUS REGISTER

OR DATA INPUT

CONFIRM COMMAND

26/49

tWLEL tEHWH

tVPHEH

POWER-UP AND

SET-UP COMMAND

tWPHEH

tEHEL

tEHDX

tELEH

tDVEH

DQ0-DQ15 COMMAND

Table 17. Write A C Characteristics, Chip Enable Controlled

Symbol Alt Parameter

AVAV

AVEH

DVEH

EHAX

EHDX

EHEL

EHGL

EHWH

ELEH

ELQV

QVVPL

QVWPL

VPHEH

WLEL

WPHEH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V

(1,2)

(1)

Write Cycle Time Min 70 85 90 100 ns

Address Valid to Chip Enable High Min 45 45 50 50 ns

Data Valid to Chip Enable High Min 45 45 50 50 ns

Chip Enable High to Address Transition Min 0 0 0 0 ns

Chip Enable High to Data Transition Min 0 0 0 0 ns

Chip Enable High to Chip Enable Low Min 25 25 30 30 ns

CPH

Chip Enable High to Output Enable Low

Chip Enable High to Write Enable High Min 0 0 0 0 ns

Chip Enable Low to Chip Enable High Min 45 45 50 50 ns

Min 25 25 30 30 ns

Chip Enable Low to Output Valid Min 70 85 90 100 ns Output Valid to VPPLow

Min 0 0 0 0 ns

Data Valid to Write Protect Low Min 0 0 0 0 ns

VPSVPP

High to Chip Enable High

Min 200 200 200 200 ns Write Enable Low to Chip Enable Low Min 0 0 0 0 ns Write Protect High to Chip Enable High Min 45 45 50 50 ns

is seen as a logic input (VPP<3.6V).

M28W800CT, M28W800CB

M28W800C

Unit

70 85 90 100

27/49

M28W800CT, M28W800CB

Figure 12. Power-Up and Reset AC Waveforms

E, G

tPHWL

tPHEL

tPHGL

tPHWL

tPHEL

tPHGL

tVDHPH

VDD, VDDQ

Power-Up Reset

Table 18. Power-Up and Reset AC Characteri stics

Symbol Parameter Test Condition

PHWL

PHEL

PHGL

PLPH

VDHPH

Note: 1. The device Reset is possible but not guaranteed if t

Reset High to Write Enable Low, Chip Enable Low, Output Enable Low

(1,2)

Reset Low to Reset High Min 100 100 100 100 ns

(3)

Supply Voltages High to Reset High Min 50 50 50 50 µs

2. Sampled only, not 100% tested.

3. It is important to assert RP

in order to allow proper CPU initialization during power up or reset.

PLPH

During

Program

and Erase

others Min 30 30 30 30 ns

< 100ns.

tPLPH

AI03537b

M28W800C

Unit

70 85 90 100

Min 50 50 50 50 µs

28/49

M28W800CT, M28W800CB

PACKAGE MECHANICAL

Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

1 N

N/2

DIE

TSOP-a

Note: Drawing is not to scale.

LA1 α

Table 19. TSOP 48 - 48 lead Pla stic Thin Small Outline, 12 x 20mm, Package Mechanical Data

Symbol

A 1.20 0.0472 A1 0.05 0.15 0.0020 0.0059 A2 0.95 1.05 0.0374 0.0413

B 0.17 0.27 0.0067 0.0106

C 0.10 0.21 0.0039 0.0083 D 19.80 20.20 0.7795 0.7953

D1 18.30 18.50 0.7205 0.7283

E 11.90 12.10 0.4685 0.4764

e 0.50 – – 0.0197 – –

L 0.50 0.70 0.0197 0.0279

α 0° 5° 0° 5°

N48 48

CP 0.10 0.0039

Typ Min Max Typ Min Max

mm inches

29/49

M28W800CT, M28W800CB

Figure 14. TFBGA46 6.39x6.37m m - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline

E1E

BALL "A1"

ddd

Note: Drawing is not to scale.

BGA-Z13

Table 20. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75m m pitch, Package Mech ani cal Data

Symbol

Typ Min Max Typ Min Max

A 1.200 0.0472 A1 0.200 0.0079 A2 1.000 0.0394

b 0.400 0.350 0.450 0.0157 0.0138 0.0177

D 6.390 6.290 6.490 0.2516 0.2476 0.2555

D1 5.250 – – 0.2067 – –

ddd 0.100 0.0039

E 6.370 6.270 6.470 0.2508 0.2469 0.2547

e 0.750 – – 0.0295 – –

millimeters inches

E1 3.750 – – 0.1476 – –

FD 0.570 – – 0.0224 – – FE 1.310 – – 0.0516 – – SD 0.375 – – 0.0148 – – SE 0.375 – – 0.0148 – –

30/49

M28W800CT, M28W800CB

Figure 15. TFBGA46 Daisy Chain - Package C onnections (Top view through package)

87654321

Figure 16. TFBGA46 Daisy Chain - PCB Connections proposal (Top view through package)

87654321

START

POINT

END

POINT

AI03860

AI03861

31/49

M28W800CT, M28W800CB

PART NUMBERING

Table 21. Ordering Information Scheme

Example: M28W800CT 90 N 6 T

Device Type

M28

Operating Voltage

W=V

Device Function

800C = 8 Mbit (512Kb x16), Boot Block

Array Matrix

T=TopBoot B = Bottom Boot

Speed

70 = 70 ns 85 = 85 ns 90 = 90 ns 100 = 100 ns

= 2.7V to 3.6V; V

= 1.65V to 3.6V

DDQ

Package

N = TSOP48: 12 x 20 mm ZB = TFBGA46: 6.39 x 6.37mm, 0.75 mm pitch

Temperature Range

1 = 0 to 70 °C 6 = –40 to 85 °C

Option

T = Tape & Reel Packing

Table 22.Daisy Chain Ordering Scheme

Example: M28W800C -ZB T

Device Type

M28W800C

Daisy Chain

-ZB = TFBGA46: 6.39 x 6.37mm, 0.75 mm pitch

Option

T = Tape & Reel Packing

Note:Devices areshipped from thefactory with thememory content bitserased to ’1’.For a listof available

options (Speed, Pack age, etc...) or forfurther information on any aspect of this device, ple as e contact the ST Sales Office nearest to you.

32/49

M28W800CT, M28W800CB

REVISION HISTORY

Table 23. Docum ent Revision History

Date Version Revision Details

January 2001 -01 First Issue

10-May-2001 -02 Completely rewritten and restructured, 70ns and 85ns speed class added. 29-May-2001 -03 Corrections to CFI data and Block Address Table. 31-May-2001 -04 Package changes - TFBGA45 replaced by TFBGA46.

02-Jul-2001 -05 Corrections to Table 3. Commands (Lock, Unlock, Lock-Down)

Document status changed from Preliminary Data to Datasheet V

Maximum changed to 3.3V

31-Oct-2001 -06

16-May-2002 -07

DDQ

Commands Table, Read CFI Query Address on 1st cycle changed to ‘X’ (Table 3)

description clarified (Table 16)

WHEL

Maximum changed to 3.6V, TFBGA package dimensions added to description.

DDQ

33/49

M28W800CT, M28W800CB

APPENDIX A. BLOCK ADDRESS TABLES

Table 24. Top Bo ot Block Addresses, M28W800CT

0 4 7F000-7FFFF 1 4 7E000-7EFFF 2 4 7D000-7DFFF 3 4 7C000-7CFFF 4 4 7B000-7BFFF 5 4 7A000-7AFFF 6 4 79000-79FFF 7 4 78000-78FFF 8 32 70000-77FFF

9 32 68000-6FFFF 10 32 60000-67FFF 11 32 58000-5FFFF 12 32 50000-57FFF 13 32 48000-4FFFF 14 32 40000-47FFF 15 32 38000-3FFFF

Size

(KWord)

Address Range

Table 25. Bottom Boot Block Addresses, M28W800CB

22 32 78000-7FFFF 21 32 70000-77FFF 20 32 68000-6FFFF 19 32 60000-67FFF 18 32 58000-5FFFF 17 32 50000-57FFF 16 32 48000-4FFFF 15 32 40000-47FFF 14 32 38000-3FFFF 13 32 30000-37FFF 12 32 28000-2FFFF 11 32 20000-27FFF 10 32 18000-1FFFF

9 32 10000-17FFF 8 32 08000-0FFFF 7 4 07000-07FFF

Size

(KWord)

Address Range

16 32 30000-37FFF 17 32 28000-2FFFF 18 32 20000-27FFF 19 32 18000-1FFFF 20 32 10000-17FFF 21 32 08000-0FFFF 22 32 00000-07FFF

6 4 06000-06FFF 5 4 05000-05FFF 4 4 04000-04FFF 3 4 03000-03FFF 2 4 02000-02FFF 1 4 01000-01FFF 0 4 00000-00FFF

34/49

M28W800CT, M28W800CB

APPENDIX B. COMMON FLASH INTERFACE (CFI)

TheCommonFlashInterfaceisaJEDECapproved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing param eters, density information and functions supported by the memory. The system can i nterface easily with the device, enabling th e software to upgrad e itself when necessary.

When the CFI Query Command (RCFI) is issued the device enters CFI Query mode and the data

Table 26. Query Structure Overview

Offset Sub-section Name Description

00h Reserved Reserved for algorithm-specific information 10h CFI Query Identification String Command set ID and algorithm data offset

1Bh System Interface Information Device timing & voltage information

27h Device Geometry Definition Flash device layout

P Primary Algorithm-specific Extended Query table

A Alternate Algorithm-specific Extended Query table

Note: Query data are alwayspresentedon the lowest orderdata outputs.

structure is read from the m emory. Tables 26, 27, 28, 29, 30 and 31 show the addresses us ed to retrieve the data.

The CFI data structu re also contains a security area where a 64 bit unique security number iswritten (see Table 31, Security Code area). T his area can be accessed only in Read mode by the final user. It is im pos sible to change the security number after it has been written by ST. Issue a Read command to return to Read mode.

Additional information specific to the Primary Algorithm (optional)

Additional information specific to the Alternate Algorithm (optional)

Table 27. CFI Query Identification String

Offset Data Description Value

00h 0020h Manufacturer Code ST

01h

02h-0Fh reserved Reserved

10h 0051h "Q"

11h 0052h Query Unique ASCII String "QRY" "R" 12h 0059h "Y" 13h 0003h 14h 0000h 15h 0035h 16h 0000h 17h 0000h 18h 0000h 19h 0000h

1Ah 0000h

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

88CCh 88CDh

Device Code

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm

Address for Primary Algorithm extended Query table (see Table 29) P = 35h

Alternate Vendor Command Set and Control Interface ID Code second vendor specified algorithm supported (0000h means none exists)

Address for Alternate Algorithm extended Query table (0000h means none exists)

compatible

Top

Bottom

Intel

35/49

M28W800CT, M28W800CB

Table 28. CFI Query System Interface Information

Offset Data Description Value

Logic Supply Minimum Program/Erase or Write voltage

1Bh 0027h

1Ch 0036h

1Dh 00B4h

1Eh 00C6h

1Fh 0004h 20h 0004h 21h 000Ah 22h 0000h 23h 0005h 24h 0005h 25h 0003h 26h 0000h

bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV

Logic Supply Maximum Program/Erase or Write voltage

bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV

Typical time-out per single word program = 2 Typical time-out for Double Word Program = 2 Typical time-out per individual block erase = 2 Typical time-out for full chip erase = 2

Maximum time-out for word program = 2 Maximum time-out for Double Word Program = 2 Maximum time-out per individual block erase = 2

Maximum time-out for chip erase = 2

times typical

µs

times typical

µs ms

times typical

2.7V

3.6V

11.4V

12.6V

16µs 16µs

NA 512µs 512µs

36/49

Table 29. Device Geometry Definition

Offset Word

Mode

27h 0014h 28h

29h

2Ah 2Bh

2Ch 0002h

2Dh 2Eh

2Fh 30h

31h 32h

M28W800CT

33h 34h

2Dh 2Eh

2Fh 30h

31h 32h

M28W800CB

33h 34h

Data Description Value

Device Size = 2

0001h 0000h

0002h 0000h

000Eh 0000h

0000h 0001h

0007h 0000h

0020h 0000h

0007h 0000h

0020h 0000h

000Eh 0000h

0000h 0001h

Flash Device Interface Code description

Maximum number of bytes in multi-byte program or page = 2 Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing contiguous Erase Blocks of the same size.

Region 1 Information Number of identical-size erase block = 000Eh+1

Region 1 Information Block size in Region 1 = 0100h * 256 byte

Region 2 Information Number of identical-size erase block = 0007h+1

Region 2 Information Block size in Region 2 = 0020h * 256 byte

Region 1 Information Number of identical-size erase block = 0007h+1

Region 1 Information Block size in Region 1 = 0020h * 256 byte

Region 2 Information Number of identical-size erase block = 000Eh+1

Region 2 Information Block size in Region 2 = 0100h * 256 byte

in number of bytes

M28W800CT, M28W800CB

1 MByte

x16

Async.

64 KByte

8 KByte

64 KByte

37/49

M28W800CT, M28W800CB

Table 30. Primary Algorithm-Specific Extend ed Query Table

Offset

P = 35h

(1)

(P+0)h = 35h 0050h (P+1)h = 36h 0052h "R" (P+2)h = 37h 0049h "I" (P+3)h = 38h 0031h Major version number, ASCII "1" (P+4)h = 39h 0030h Minor version number, ASCII "0"

Data Description Value

Primary Algorithm extended Query table unique ASCII string “PRI”

"P"

(P+5)h = 3Ah 0066h Extended Query table contents for Primary Algorithm. Address (P+5)h (P+6)h = 3Bh 0000h (P+7)h = 3Ch 0000h (P+8)h = 3Dh 0000h

contains less significant byte.

bit 0 Chip Erase supported (1 = Yes, 0 = No) bit 1 Suspend Erase supported (1 = Yes, 0 = No) bit 2 Suspend Program supported (1 = Yes, 0 = No) bit 3 Legacy Lock/Unlock supported (1 = Yes, 0 = No) bit 4 Queued Erase supported (1 = Yes, 0 = No) bit 5 Instant individual block locking supported (1 = Yes, 0 = No) bit 6 Protection bits supported (1 = Yes, 0 = No) bit 7 Page mode read supported (1 = Yes, 0 = No) bit 8 Synchronous read supported (1 = Yes, 0 = No) bit 31 to 9 Reserved; undefined bits are ‘0’

No Yes Yes

(P+9)h = 3Eh 0001h Supported Functions after Suspend

Read Array, Read Status Register and CFI Query are always supported during Erase or Program operation

bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No)

bit 7 to 1 Reserved; undefined bits are ‘0’ Yes (P+A)h = 3Fh 0003h Block Lock Status (P+B)h = 40h 0000h

Defines which bits in the Block Status Register section of the Query are implemented. Address (P+A)h contains less significant byte

bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No)

bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

Yes Yes

bit 15 to 2 Reserved for future use; undefined bits are ‘0’ (P+C)h = 41h 0030h V

Logic Supply Optimum Program/Erase voltage (highest performance)

3V bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV

(P+D)h = 42h 00C0h V

Supply Optimum Program/Erase voltage

12V bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV

(P+E)h = 43h 0001h Number of Protection register fields in JEDEC ID space.

"00h," indicates that 256 protection bytes are available

(P+F)h = 44h 0080h Protection Field 1: Protection Description

(P+10)h = 45h 0000h 00h

(P+11)h = 46h 0003h 8 Byte

(P+12)h = 47h 0003h 8 Byte

This field describes user-available. One Time Programmable (OTP) Protection register bytes. Some are pre-programmed with device unique serial numbers. Others are user programmable. Bits 0–15 point to the Protection register Lock byte, the section’s first byte. The following bytes are factory pre-programmed and user-programmable.

80h

bit 0 to 7 Lock/bytes JEDEC-plane physical low address bit 8 to 15 Lock/bytes JEDEC-plane physical high address

bit 16 to 23 "n" such that 2 bit 24 to 31 "n" such that 2

= factory pre-programmed bytes

= user programmable bytes

(P+13)h = 48h Reserved

Note: 1. See Table 27, offset 15 for P pointer definition.

38/49

Table 31. Security Code Area

Offset Data Description

80h 00XX Protection Register Lock 81h XXXX 82h XXXX 83h XXXX 84h XXXX 85h XXXX 86h XXXX 87h XXXX 88h XXXX

64 bits: unique device number

64 bits: User Programmable OTP

M28W800CT, M28W800CB

39/49

M28W800CT, M28W800CB

APPENDIX C. FLOWCHARTS AND P SEUDO CODES

Figure 17. Program Flowchart and Pseudo Code

Start

Write 40h or 10h

Write Address

& Data

Read Status

b7 = 1

YES

b3 = 0

YES

b4 = 0

YES

b1 = 0

YES

End

VPP Invalid

Error (1, 2)

Program to Protected

Block Error (1, 2)

Program

program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0x40) ; /*or writeToFlash (any_address, 0x10) ; */

writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;

if (status_register.b4==1) /*program error */ error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;

}

AI03538b

Note: 1. Status check of b1 (Protected Block), b3 (VPPInvalid) and b4 (Program Error) can be made after each program operation or after

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

40/49

Figure 18. Double Word Program Flowchart and Pseudo Code

Start

M28W800CT, M28W800CB

Write 30h

Write Address 1

& Data 1 (3)

Write Address 2

& Data 2 (3)

Read Status

b7 = 1

YES

b3 = 0

YES

b4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

double_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2) { writeToFlash (any_address, 0x30) ;

writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ /*Memory enters read status state after the Program command*/

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;

if (status_register.b4==1) /*program error */ error_handler ( ) ;

YES

b1 = 0

YES

End

Note: 1. Status check of b1 (Protected Block), b3 (VPPInvalid) and b4 (Program Error) can be made after each program operation or after

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;

}

AI03539b

41/49

M28W800CT, M28W800CB

Figure 19. Prog ram Suspend & Resume Flowchart and Pseudo Code

Start

program_suspend_command ( ) {

Write B0h

Write 70h

Read Status

writeToFlash (any_address, 0xB0) ; writeToFlash (any_address, 0x70) ;

/* read status register to check if program has already completed */

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

b7 = 1

YES

b2 = 1

YES

Write FFh

Read data from

another address

Write D0h

Program Continues

Program Complete

Write FFh

Read Data

} while (status_register.b7== 0) ;

if (status_register.b2==0) /*program completed */ { writeToFlash (any_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/

} else { writeToFlash (any_address, 0xFF) ; read_data ( ); /*read data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ } }

AI03540b

42/49

Figure 20. Erase Flowchart and Pseudo Code

Start

Write 20h

Write Block

Address & D0h

M28W800CT, M28W800CB

erase_command ( blockToErase ) { writeToFlash (any_address, 0x20) ;

writeToFlash (blockToErase, 0xD0) ; /* only A12-A20 are significannt */ /* Memory enters read status state after

the Erase Command */

Read Status

YES

VPP Invalid

Error (1)

Command

Sequence Error (1)

Erase to Protected

Block Error (1)

b7 = 1

b3 = 0

b4, b5 = 1

b5 = 0 Erase Error (1)

b1 = 0

End

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;

if ( (status_register.b4==1) && (status_register.b5==1) ) /* command sequence error */ error_handler ( ) ;

if ( (status_register.b5==1) ) /* erase error */ error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;

}

AI03541b

Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.

43/49

M28W800CT, M28W800CB

Figure 21. Erase Suspend & Resu m e Flowchart and Pseudo Code

Start

Write B0h

Write 70h

Read Status

b7 = 1

b6 = 1

Write FFh

Read data from

another block

Program/Protection Program

Block Protect/Unprotect/Lock

or or

Write D0h

Erase Continues

YES

Erase Complete

Write FFh

Read Data

erase_suspend_command ( ) { writeToFlash (any_address, 0xB0) ;

writeToFlash (any_address, 0x70) ; /* read status register to check if erase has already completed */

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b6==0) /*erase completed */ { writeToFlash (any_address, 0xFF) ;

read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/

} else { writeToFlash (any_address, 0xFF) ; read_program_data ( ); /*read or program data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume erase*/ } }

44/49

AI03542b

Figure 22. Locking Operations Flowchart and Pseudo Code

Start

M28W800CT, M28W800CB

Write 60h

Write

01h, D0h or 2Fh

Write 90h

Read Block

Lock States

Locking change

confirmed?

YES

Write FFh

End

locking_operation_command (address, lock_operation) { writeToFlash (any_address, 0x60) ; /*configuration setup*/

if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ;

writeToFlash (any_address, 0x90) ;

if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/

writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/ }

AI04364

45/49

M28W800CT, M28W800CB

Figure 23. Protection Register Program Flowchart and Pseudo Code

Start

Write C0h

Write Address

& Data

Read Status

b7 = 1

YES

b3 = 0

YES

b4 = 0

YES

b1 = 0

YES

End

VPP Invalid

Error (1, 2)

Program to Protected

Block Error (1, 2)

Program

protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0xC0) ;

writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;

if (status_register.b4==1) /*program error */ error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;

}

AI04381

Note: 1. Status check of b1 (Protected Block), b3 (VPPInvalid) and b4 (Program Error) can be made after each program operation or after

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

46/49

M28W800CT, M28W800CB

APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE

Table 32. Write State Machine Current/Next, sheet 1 of 2.

Current

StateSRbit 7

Read Array “1” Array Read Array Prog.Setup Ers. Setup Read Array Read Sts. Read Array

Read

Status

Read

Elect.Sg.

Read CFI

Query

Lock Setup “1” Status Lock Command Error

Lock Cmd

Error Lock

(complete) Prot. Prog.

Setup

Prot. Prog.

(continue)

Prot. Prog. (complete)

Prog.Setup “1” Status Program

Program

(continue) Prog.Sus

Status

Prog.Sus

Read Array

Prog.Sus

Read

Elect.Sg.

Prog.Sus

Read CFI

Program

(complete)

Erase Setup

Erase

Cmd.Error

Erase

(continue) Erase Sus

Read Sts

Erase Sus

Read Array

Erase Sus

Read

Elect.Sg.

Erase Sus

Read CFI

Erase

(complete)

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.

“1” Status Read Array

“1”

“1” CFI Read Array

“1” Status Read Array

“1” Status Protection Register Program

“0” Status Protection Register Program continue

“1” Status Read Array

“0” Status Program (continue)

“1” Status

“1” Array

“1”

“1” CFI

“1” Status Read Array

“1” Status Erase Command Error

“1” Status Read Array

“0” Status Erase (continue)

“1” Status

“1” Array

“1”

“1” CFI

“1” Status Read Array

Data

When

Read

Electronic Signature

Read Array (FFh)

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Program

Setup

(10/40h)

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program Suspend to

Read Array

Program Suspend to

Read Array

Program Suspend to

Read Array

Program Suspend to

Read Array

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Command Input (and Next State)

Erase Setup

(20h)

Erase Setup

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Setup

Erase

Confirm

(D0h)

Lock

(complete)

Program

(continue)

Program

(continue)

Program

(continue)

Program

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Prog/Ers Suspend

(B0h)

Read Array

Lock Cmd

Error

Read Array

Prog. Sus

Read Sts

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array Read Array

Erase

CmdError

Read Array

Erase Sus

Read Sts

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array Read Array

Prog/Ers

Resume

(D0h)

Lock

(complete)

Program

(continue)

Program

(continue)

Program

(continue)

Program

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Read

Status

(70h)

Read

Status

Read

Status

Read

Status

LockCommand Error

Read

Status

Read

Status

Read

Status

Program (continue)

Prog. Sus

Read Sts

Prog. Sus

Read Sts

Prog. Sus

Read Sts

Prog. Sus

Read Sts

Read

Status

Erase Command Error

Read

Status

Erase (continue)

Erase Sus

Read Sts

Erase Sus

Read Sts

Erase Sus

Read Sts

Erase Sus

Read Sts

Read

Status

Read Array

Read Array Read Array

Read Array

Read Array Read Array

Clear

Status

(50h)

Prog. Sus

Erase Sus

47/49

M28W800CT, M28W800CB

Table 33. Write State Machine Current/Next, sheet 2 of 2.

Command Input (and Next State)

Current State

Read Array ReadElect.Sg. Read CFI Query Lock Setup

Read Status Read Elect.Sg. Read CFIQuery Lock Setup

Read Elect.Sg. Read Elect.Sg. Read CFI Query Lock Setup

Read CFI Query Read Elect.Sg. Read CFI Query Lock Setup

Lock Setup Lock Command Error Lock (complete)

Lock Cmd Error Read Elect.Sg. Read CFI Query Lock Setup

Lock (complete) Read Elect.Sg. Read CFI Query Lock Setup

Prot. Prog.

Setup

Prot. Prog.

(continue)

Prot. Prog. (complete)

Prog. Setup Program

Program

(continue)

Prog.Suspend

Read Status

Prog.Suspend

Read Array

Prog.Suspend

ReadElect.Sg.

Prog.Suspend

Read CFI

Program

(complete)

EraseSetup EraseCommand Error

Erase

Cmd.Error

Erase (continue) Erase (continue)

Erase Suspend

Read Status

Erase Suspend

Read Array

Erase Suspend ReadElect.Sg.

Erase Suspend

Read CFI Query

Erase

(complete)

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.

Read Elect.Sg.

(90h)

Read Elect.Sg. Read CFI Query Lock Setup

Prog. Suspend Read Elect.Sg.

Read Elect.Sg. Read CFIQuery Lock Setup

Read Elect.Sg. Read CFI Query Lock Setup

Erase Suspend

Read Elect.Sg.

Erase Suspend

Read Elect.Sg.

Erase Suspend

Read Elect.Sg.

Erase Suspend

Read Elect.Sg. Read Elect.Sg. Read CFI Query Lock Setup

Read CFI

Query

(98h)

Prog. Suspend

Read CFI Query

Prog. Suspend

Read CFI Query

Prog. Suspend

Read CFI Query

Prog. Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Lock Setup

(60h)

Protection Register Program

Protection Register Program (continue)

LockSetup Erase Suspend Read Array

Prot. Prog.

Setup (C0h)

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Program (continue)

Program SuspendReadArray

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Lock Confirm

(01h)

Confirm (2Fh)

Lock Down

Read Array

Unlock

Confirm

(D0h)

Program

(continue)

Program

(continue)

Program

(continue)

Program

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

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M28W800CT, M28W800CB

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49/49

SGS Thomson Microelectronics M28W800CT, M28W800CB Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual