SGS Thomson Microelectronics M28W800BT, M28W800BB Datasheet

FEATURES SUMMARY

■ SUPPLY VOLTAGE

–V –V –V

■ ACCE SS TIME: 70, 85, 90,10 0ns

■ PROGRAMMING TIME

= 2.7V to 3.6V Core Power Supply

= 1.65V to 3.6V for Input/Output

DDQ

= 12V for fast Program (optional)

– 10µs typical – Double Word Programming Option

■ COMMON FLASH INTERFACE

– 64 bit Security Code

■ MEMORY BLOCKS

– Parameter Blocks (Top or Bottom location) – M ain Blocks

■ BLOCK PROTECTION onTWO PARAMETER

BLOCKS –WP

for Block Protection

■ AUTOMAT IC S TAND-BY M ODE

■ PROGRAM and ERASE SUSPEND

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Top Device Code, M28W800BT: 8892h – Bottom Device Code, M28W800BB: 8893h

M28W800BT

M28W800BB

8 Mbit (512Kb x16, Boot Block)

3V Supply Flash Memory

Figure 1. Packages

FBGA

TFBGA46 (ZB)

6.39 x 6.37mm

TSOP48 (N)

12 x 20mm

1/42May 2002

M28W800BT, M28W800BB

TABLE OF CONTENTS

SUMMARYDESCRIPTION...........................................................5

Figure2.LogicDiagram ..........................................................5

Table 1. Signal Nam es . . . ........................................................5

Figure 3. TSOP Connections.......................................................6

Figure 4. TFBGA Connections (Top view through package). ..............................7

Figure5.BlockAddresses.........................................................8

SIGNALDESCRIPTIONS............................................................9

AddressInputs(A0-A18)..........................................................9

Data Input/Output (DQ0-DQ15). . . ..................................................9

ChipEnable(E). ................................................................9

Output Enabl e (G). ..............................................................9

Write Enable (W). . ..............................................................9

WriteProtect(WP)...............................................................9

Reset(RP).....................................................................9

Supply Voltage..............................................................9

Supply Voltage.............................................................9

DDQ

ProgramSupplyVoltage ......................................................9

Ground. ...................................................................9

BUSOPERATIONS................................................................10

Read.........................................................................10

Write.........................................................................10

OutputDisable.................................................................10

Standby. . ....................................................................10

Automatic Standby. .............................................................10

Reset........................................................................10

Table2.BusOperations.........................................................10

COMMANDINTERFACE ...........................................................11

ReadMemoryArraycommand....................................................11

ReadStatusRegisterCommand...................................................11

Read Electroni c Signature Command ...............................................11

ReadCFIQueryCommand.......................................................11

BlockEraseCommand..........................................................11

ProgramCommand.............................................................11

Double Word Program Command . .................................................12

ClearStatusRegisterCommand...................................................12

Program/Erase Suspend Command ................................................12

Program/EraseResumeCommand ................................................12

BlockProtection................................................................12

Table3.Commands ............................................................13

Table4.ReadElectronicSignature.................................................13

Table5.MemoryBlocksProtectionTruthTable.......................................13

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M28W800BT, M28W800BB

Table6.Program,EraseTimesandProgram/EraseEnduranceCycles ....................14

STATUSREGISTER...............................................................15

Program/EraseControllerStatus(Bit7).............................................15

Erase Suspend Status (Bit 6) .....................................................15

EraseStatus(Bit5).............................................................15

ProgramStatus(Bit4)...........................................................15

Status(Bit3)...............................................................15

ProgramSuspendStatus(Bit2)...................................................15

BlockProtectionStatus(Bit1).....................................................16

Reserved(Bit0)................................................................16

Table7.StatusRegisterBits......................................................16

MAXIMUMRATING................................................................17

Table8.AbsoluteMaximumRatings................................................17

DCandACPARAMETERS .........................................................18

Table 9. Operating and AC Measurement Conditions...................................18

Figure6.ACMeasurementI/OWaveform ...........................................18

Figure 7. AC Measurement Load Circuit . . . ..........................................18

Table 10. Device Capac itanc e.....................................................18

Table11.DCCharacteristics......................................................19

Figure8.ReadACWaveforms....................................................20

Table12.ReadACCharacteristics.................................................20

Figure 9. Write AC Waveforms, Write Enable Controlled . . . .............................21

Table 13. Write AC Characteristics, Write Enable Co ntrolled .............................22

Figure10.WriteACWaveforms,ChipEnableControlled................................23

Table14.WriteACCharacteristics,ChipEnableControlled .............................24

Figure11.Power-UpandResetACWaveforms.......................................25

Table15.Power-UpandResetACCharacteristics ....................................25

PACKAGE MECHANICAL . . . .......................................................26

Figure12.TSOP48-48leadPlasticThinSmallOutline,12x20mm,PackageOutline ........26

Table 16. TSOP48 - 48 lead Plas tic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 26 Figure 13. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline27 Table17.TFBGA466.39x6.37mm-8x6ballarray,0.75mmpitch,PackageMechanicalData...27

Figure 14. TFBGA46 Daisy Chain - Package Connections (Top view through package) ........28

Figure 15. TFBGA46 Daisy Chain - PCB Connections proposal (Top view through package ) ....28

PARTNUMBERING ...............................................................29

Table18.OrderingInformationScheme.............................................29

Table19.DaisyChainOrderingScheme............................................29

REVISIONHISTORY...............................................................30

Table20.DocumentRevisionHistory...............................................30

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M28W800BT, M28W800BB

APPENDIX A. BLOCK ADDRES S T ABLES . . ..........................................31

Table 21. Top Boot Block Ad dres se s, M28W800BT ....................................31

Table22.BottomBootBlockAddresses,M28W800BB.................................31

APPENDIXB.COMMONFLASHINTERFACE(CFI) .....................................32

Table23.QueryStructureOverview................................................32

Table 24. CFI Query Identification String . . ..........................................32

Table25.CFIQuerySystemInterfaceInformation.....................................33

Table26.DeviceGeometryDefinition...............................................34

Table 27. Primary Algorithm-Specific Extended Query Table .............................35

Table28.SecurityCodeArea.....................................................35

APPENDIX C. FLOWCHARTS AND PSEUDO CODES....................................36

Figure 16. Program Flowchart and Pseudo Code. . ....................................36

Figure 17. Double Word Program Flowchart and Pseudo Code ...........................37

Figure 18. Program Suspend & Resum e Flowchart and Pseudo Code .....................38

Figure 19. Erase Flowc hart and Pseudo Code ........................................39

Figure 20. Erase S us pend & Resume Flowchart and Pseudo Code. .......................40

APPENDIXD.COMMANDINTERFACEANDPROGRAM/ERASECONTROLLERSTATE.......41

Table29.WriteStateMachineCurrent/Next..........................................41

4/42

SUMMARY DESCRIPTION

The M28W800B isa 8 Mbit (512Kbit x 16) non-volatileFlashmemorythatcanbeerasedelectrically at the block level and programmed in-system on a Word-by-Word basis. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. V

1.65V. An optional 12V V

allows to drive the I/O pin down t o

DDQ

power supply is pro-

vided to speed up customer programming. The device features an asymmetrical blocked ar-

chitecture. The M28W800B has an array of 23 blocks: 8 Parameter Blocks of 4 KWord and 15 Main Blocks of 32 KWord. M28W800BT has the Parameter Blocks at the top of the memory address space while the M28W800BB locates the Parameter Blocks starting from the bottom. The memory maps are shown in Figure 5, Block Addresses.

Parameter blocks 0 and 1 can be protected from accidental programming or erasure. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended t o read data in any other block and then resumed. Each block can be program med and erased over 100,000 cycles.

Program and Erase c omm ands are written to the Command Interface of the memory. An on-chip Program/Erase Control ler takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

The memory is offered in TSOP 48 (10 X 20mm), and TFBGA46 (6.39 x 6.37mm , 0.75mm pitch) packages and is supplied with all the bits erased (set to ’1’).

M28W800BT, M28W800BB

Figure 2. Logic Diagram

DDQVPP

A0-A18

Table 1. Signal Names

A0-A18 Address Inputs DQ0-DQ15 Data Input/Output E G W RP WP V

M28W800BT M28W800BB

Chip Enable Output Enable Write Enable Reset Write Protect Core Power Supply

DQ0-DQ15

AI03581

DDQ

NC Not Connected Internally

Power Supply for Input/Output

Optional Supply Voltage for Fast Program & Erase

Ground

5/42

M28W800BT, M28W800BB

Figure 3. TSOP Connections

A15 A14 A13 A12 A11

A16 V

DDQ

DQ15 DQ7

A10 DQ14

37 36

DQ6 DQ13 DQ5 DQ12 DQ4 V

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G V

E A0

NC NC

NC A18 A17

A9 A8

A7 A6 A5 A4 A3 A2 A1

M28W800BT M28W800BB

24 25

AI03582

6/42

Figure 4. TFBGA Connections (Top view through package)

M28W800BT, M28W800BB

87654321

A13

DDQ

DQ7V

A8A11

DQ13

RP A18

DQ11

DQ12

DQ4

DQ2

A7V

DQ0DQ9DQ3DQ6DQ15V

DQ1DQ10V

A2A5A17WA10A14

A1A3A6A9A12A15

A0EDQ8DQ5DQ14A16

AI03805

7/42

M28W800BT, M28W800BB

Figure 5. Block Addresses

M28W800BT

Top Boot Block Addresses

7FFFF

7F000

78FFF

78000

77FFF

70000

0FFFF

08000

07FFF

00000

4 KWords

32 KWords

Total of 8

4 KWord Blocks

Total of 15

32 KWord Blocks

M28W800BB

Bottom Boot Block Addresses

7FFFF

78000

77FFF

70000

0FFFF

08000

07FFF

07000

00FFF

00000

32 KWords

4 KWords

Total of 15

32 KWord Blocks

Total of 8

4 KWord Blocks

AI04384

Note: Also see Appendix A, Tables 21 and 22 for a full listing of the Block Addresses.

8/42

SIGNAL DESCRIPTIONS

See Fig ure 2 Logic Diagram and T able 1,Signal Names, f or a briefoverview of thesignals connected to this device.

Address Inputs (A0-A18). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at t he s elected address during aBus Read operation or inputsa command or data to be programmed during a Write Bus operation.

Chip Enable (E

). The Chip Enable input acti-

vates the memory co ntrol logic, input buffers, decoders andsense amplifiers. When ChipEnable is

and Reset is at VIHthe device is in active

at V

mode. When Chip Enable is at V

the memory is

deselected, the outputs are high impedan ce and the power consumption is reduced to the stand-by level.

Output Enable (G

). The Output Ena ble controls

data outputs during the Bus Read operation of the memory.

WriteEnable(W

). Th e Write Enable controls the

Bus Write operation of the memory’s Command Interface. Thedata and address inputs are latched ontherisingedgeofChipEnable,E,orWriteEnable, W

Write Protect (W P

, whichever occurs f irst.

). Write Protect is an input to protect or unprotect the two lockable parameter blocks. When Write Protect is at V

, t he lockable

blocks are protected and Program or Erase operations are not possible. When Write Protec t is at V

, t he lockable blocks are unprotected and can

be programmed or erased (refer to Table 4, Memory Blocks Protection Truth).

Reset (RP

wareresetofthememory.WhenResetisatV

). The Reset input provides a hard-

the memory is in reset mode: the outputs are high impedance and the current consum pti on is mini-

M28W800BT, M28W800BB

mized. When Reset is at V mal operation. Exiting reset mode the device enters read array mode, b ut a negative transition of Chip Enable or a change of the address is required to ensure v alid data outputs.

Supply Voltage. VDDprovides the power

supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Eras e).

Supply Voltage. V

DDQ

power supply to the I/O pins and enables al l Outputs tobe powered independentlyfrom V canbetiedtoVDDor can use a s eparate supply.

Program Supply Voltage. VPPis both a

control input and a power supply pin. The two functions are selected by the voltage range applied t o the pin. The Supply V olt age V Program Supply Voltage V anyorder.

is kept in a low voltage range (0V to 3.6V)

If V

is seen as a control input. In this case a volt-

age lowerthan V

PPLK

against program or erase, while V ables these functions (see Table 11, DC Charac teristics for the relevant values). V sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effectand program or eraseoperations continue.

is in the range 11.4V to 12.6V it acts as a

If V

power supply pin. In this cond ition V stable until the Program/Erase al gorithm is completed (see Table 13 and 14).

Ground. VSSis the reference for all voltage

measurements.

Note: Each device in a system should have V

DD,VDDQ

and VPPdecoupled with a 0.1µF capacitor close to the pin. See Figure 7, AC M easurement Load Circu it. Th e PCB trace widths

should be sufficient to carry the required V Program and Erase currents.

, the device is in nor-

DDQ

provides the

canbeappliedin

gives an absolute protection

DD.VDDQ

and the

PP1

is only

must be

en-

9/42

M28W800BT, M28W800BB

BUS OPERATIONS

There are six standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby, Aut omatic Standby and Reset. See Table 2, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chip Enable or Write Enable are ignoredby the memory and do not affect bus operations.

Read. Read B us opera tions are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output E nablemustbeatV eration. The Chip Enable input sh ould be used to enable the device. Output Enable should be used to gat e data onto the output. The data r ead depends on the previous command written to the memory (see Command Interface section). See Figure 8, Read Mode AC Waveforms, and Table 12, Read AC Characteristics, for details of when the output becomes valid.

Read mode is the default state of the device when exiting Reset or after power-up.

Write. B us Write ope rations write Commands to the mem ory or latchInput Data tobe programmed. A write operation is initiated when Chip Enable and Write Enable are at V

. Commands, Input Data and Addresses are

latched on the rising edge of Write Enable or Chip Enable, whichever occurs first.

in order t o perform a read op-

with Output Enable at

See Figures 9 and 10, Write AC Waveforms, and Tables 13 and 14, Write AC Characteristics, for details of the timing requirements.

Output Disable. The data outputs are high impedance when t he Output Enable is at V

Standby. Standby disables most of the internal circuitryallowing a substantialreduction of the c urrent consumption. The memory is in st and-by when Chip Enable is at V

andthedeviceisin

read mode. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently f rom the OutputEnable or Write Enable inputs. If Chip Enable switches to V

during a program or erase operation, the de-

vice enters Standby mode when finished. Automatic Standby. Autom atic Standby pro-

vides a low power consumpt ion state during Read mode. Following a read operation, the device enters Automatic Standby after 150ns of bus inactivity, even if Chip Enable is low, V current is reduced to I

. The data Inputs/Out-

DD1

, and the supply

puts will still output data. Reset. Durin g Res et mode, when Output Enable

is low, V

, the memory is deselected and the out-

puts are high impedance. The memory is in Reset mode when Reset is at V

. The power cons ump-

tion is reduced to theStan dby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to V

during a Pro-

gram or Eras e, this operation is aborted and the memory content is no longer valid.

Table 2. Bus Operations

Operation E G W RP WP

Read Write Output Disable Standby Reset X X X

Note: X = VILor VIH,V

10/42

V V V V

=12V±5%.

PPH

X Don't Care Data Output

X X Don't Care Hi-Z X Don't Care Hi-Z X Don't Care Hi-Z

or V

PPH

DQ0-DQ15

Data Input

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Com mands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all t imings and verifies the correct execution of the Program and Erase c ommands. The Program/Erase Cont roll er provides a Status Register whose output may be read at any time, to monitor the progress of an operation, or the Program/ Erase states. See Appendix D, Table 29, Write State Machine Current/Next, for a summa ry o f the Command Interface.

The Command Interface is res et to Read mode when power is first applied, when exiting from Reset or whenever V

is lower than V

LKO

.Command sequences must be followed exactly. Any invalid c ombination ofcommands willreset the device to Read mode. Refer to Table 3, Commands, in conjunction with the text descriptions below.

Read Memory Array command

TheReadcommandreturnsthememorytoits Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent read operations will read the addressed location and output the data. When a device Reset oc c urs, the memory defaults to Read mode.

Read Status Register Co m m and

The Status Register indi cates when a program or erase operation is complete and the success or failure of the operation itself. Issue a Read Status Register comma nd to rea d the Stat us Register’s contents. Subsequent Bus Read operations read the S tatus Register, at any addres s, until another command is issued. See Table 7, Status Register Bits, for details on the definitions of the bits.

The Read Status Regi ster command may be issued at any time, ev en during a Program /Erase operation. Any Read atte mpt during a Program/ Erase op eration will automatically output the content of the Stat us Register.

Read Electronic Signature Command

The Read Electronic Signature command reads the Manufacturer and Device Codes.

The Read Electronic Signat ure command consists of one write cycle, a subsequent read will output the Manufacturer or the Device Code dependi ng on the levelsof A0. The Manufacturer Code is output when th e address line A0 is at V Code is output when A 0 is at V A7 must be kept to V

, other addresses are ig-

, the Device

. Addres s es A1-

nored. The cod es are output on DQ0-DQ7 with DQ8-DQ15 at 00h. (see Table 4)

M28W800BT, M28W800BB

Read CFI Query Command

The Read Query Comm and is used to read data fromtheCommonFlashInterface(CFI)Memory Area, allowing programm ing equipment or ap plications to automatically match their interface to the characteristics of the device.

One Bus Write cycle is required to issue the Read Query Command. Once the c ommand is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. See Appendix B, Common Flash Interface, Tables 23, 24, 25, 26, 27 and 28 for details on the information contained in the Common Flash Interface memory area.

Block Erase Command

TheBlockErasecommandcanbeusedtoerase a block. It setsall the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the Erase operation w ill abort, the data inthe block willnot be changed and the Status Register will output the error.

Two Bus Write cycles are required to issue the command.

■ The first bus cycle sets up the Erase command.

■ Th e s ec ond latches the block address in the

internal state machine and starts the P ro gram/ Erase Controller.

If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts.

Erase aborts if Reset turns to V cannot beguaranteed when theErase operation is aborted, the block must be erased again.

During Erase operations the memory will only accept the Read S tatus Register command and the Program/Erase Suspend command, allother commands will be ignored. Typical Erase times are given in Table 6, Program, E ras e Times and Program/Erase Endurance Cycles.

See Appendix C, Figure 19, Erase Flowchart and Pseudo Code, for the flowchartfor using theErase command.

Program Command

The memory array can be programmed word-byword. Two bus write cycles are required to issue the Program command.

■ Th e first bus cycle s ets up the Program

command.

■ Th e secondlatches theAddress andthe Datato

be written and star ts the Program/Erase Controller.

During Program operations the memory will only accept the Read Status Register command and the Program/Erase Suspe nd c ommand. All other

. As dat a integ rity

11/42

M28W800BT, M28W800BB

commands will be ignored. Typical Program times are given in Table 6, Progra m, E ras e Times and Program/Erase Endurance Cy c les.

Programming aborts if Reset goes to V

. As data

integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed.

See Appendix C, Figure 16 , Program Flowchart and Pseudo Code, for the flowchart for using the Program comman d.

Double Word Program Command

Thisfeat ure isoffered toimprove the programming throughput, writing a page of two adjacent words in parallel.The two words must differ only for the address A0. Programming should not be attempted when V

executed if V

isnot atV

is below V

. The c ommand can be

PPH

but the result is not

PPH

guaranteed. Three bus write cycles are neces sary to issue the

Double Word Program c ommand.

■ Th e f irst bus cycle sets up the Double Word

Program comm and.

■ The second bus cycle latches the Address and

theDataofthefirstwordtobewritten.

■ The third bus cyclelatches the Address and the

Data of the second word to bewritten and st arts the Program/Erase Controlle r.

Read operations out put the Status Register content after the programming has started. Programming aborts if Reset goes to V

. As data integrity

cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed.

See Appendix C, Figure 17, Double Word Program Flowchart and Pseudo Code, for the flowchart for using the Double Word Program command.

Clear Status Register Command

The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 i n the Status R egister to ‘0’. One bus write cycle is required to issue the Clear Status Register command.

The bits in the Status Register do not automatically return t o ‘0’ when a new Program or Erase command is issued. Th e error bits in the Status Register should be cleared before attempting a new Program or Erase command.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to pause a Pr ogram or Erase operation. One bus write cycle is required to issue the Program/Erase command and pause the Program/Erase cont roller.

During Program/Erase Suspend theCommand Interface will accept the Program/Erase Resume, Read A rray , Read StatusRegister, Read E lectronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Program command will also be accepted. Only the blocks not being erased may be read or programmed correctly.

During a Program/Erase Su sp end, the device can be placed in a pseudo-standby mode by taking Chip Enable to V Reset turns to V

. P rogram/Erase is abort ed if

See Appendix C, Figure 18, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 20, Erase Suspend & Res ume Flowchart and Pseudo Codefor flowchartsfor usingthe Program/ Erase Suspend c ommand.

Program/Erase Resume Command

The Program/Erase Resume command can be used to restart the Program/Eras e Controller after a Program/Erase Suspend operation has paused it. One Bus W rite cycle is required to issue the command. Once the command is issued subsequent Bus Read operations read the Status Register.

See A ppendix C, Figure 18, Program or Double Word Program Suspend & Resume Flowchart and Pseudo Code, and Figure 20, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/Erase Resume command.

Block Protection

Two parameter/lockable blocks (blocks #0 and #1) can be protected against Program or E ras e operations. Unprotected blocks can be program med or erased.

To protect t he two lockable blocks set Write Protect to V

. WhenVPPis below V

allblocks are

PPLK

protected. Any attempt to Program or Erase protected blocks will abort, the data in the block will not be changed and the Status Regis ter outputs the error.

Table 5, Memory Blocks Protection Truth Table, defines the protection methods.

12/42

Table 3. Commands

M28W800BT, M28W800BB

Bus Write Operations

(3)

No. of

Cycles

3 Write X 30h Write Addr 1

Commands

Read Memory Array 1+ Write X FFh

Read Status Register 1+ Write X 70h Read X

Read Electronic Signature 1+ Write X 90h

Read CFI Query 1+ Write X 98h

Erase 2 Write X 20h Write

Program 2 Write X

Double Word Program

Clear StatusRegister 1 Write X 50h Program/Erase Suspend 1 Write X B 0h Program/Erase Resume 1 Write X D0h

Note: 1. X = Don't Care.

2. A0=V

3. Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.

outputs Manufacturercode,A0=VIHoutputs Device code. Address A7-A1 must be VIL.

1st Cycle 2nd Cycle 3nd Cycle

Bus

Op.

Addr Data

40h or

10h

Bus

Op.

Read

Write Addr

Addr Data

Signature

Addr

CFI Addr Query

Block

Read

Addr

(2)

Data

Status

Signature

D0h

Data Input

Bus

Op.

Write Addr 2

Addr Data

Data Input

Table 4. Read Electronic Signature

Code Device E G W A0 A1-A7 A8-A18 DQ0-DQ7 DQ8-DQ15

Manufact. Code

Device Code

Note: RP =VIH.

M28W800BT

M28W800BB

V V V

Don't Care 20h 00h

Don't Care 92h 88h

Don't Care 93h 88h

Table 5. Memo ry Blocks Protection T ruth Table

(1)

or V

Note: 1. X = Don't Care

2. V

(2)

PPH

(2)

PPH

must also be greater than the Program Voltage Lock Out V

RP WP

(1)

X Protected Protected X Protected Protected

Lockable Blocks

(blocks #0 and #1)

Other Blocks

Protected Unprotected

Unprotected Unprotected

PPLK

13/42

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