SGS Thomson Microelectronics M28W640CT, M28W640CB Datasheet

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FEATURES SUMMARY

■ SUPPLY VOLTAGE

–V –V –V

■ ACCESS TIME

= 2.7V to 3.6V Core Power Supply

= 1.65V to 3.3V for Input/Output

DDQ

= 12V for fast Program (optional)

– 3.0V to 3.6V: 80ns – 2.7V to 3.6V: 90ns

■ PROGRAMMING TIME:

– 10µs typical – Double W ord Programming Option – Quadruple Word Program ming Option

■ COMMON FLASH INTERFACE

■ MEMORY BLOCKS

– Parameter Blocks (Top or Bottom location) – M ain Blocks

■ BLOCK LOCKING

– All blocks locked at Power Up – Any combination of blocks ca n be locked

for Block Lock-Down

–WP

■ SECURITY

– 128 bit user Programmable OTP cells – 64 bit unique device identifier – One Parameter B lock Permanent ly Lockable

■ AUTOMAT IC STAND-BY MODE

■ PROGRAM and ERASE SUSPEND

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Top Dev ice Code, M28W640CT: 8848h – Bottom Device Code, M28W640CB: 8849h

M28W640CT

M28W640CB

64 Mbit (4Mb x16, Boot Block)

3V Supply Flash Memory

PRELIMINARY DATA

Figure 1 . Packages

FBGA

TFBGA48 (ZB) 8 x 6 ball array

TSOP48 (N)

12 x 20mm

November 2001

This is preliminary information on anew product nowin development or undergoing evaluation. Details are subject to change without notice.

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M28W640CT, M28W640CB

TABLE OF CONTENTS

SUMMARYDESCRIPTION...........................................................5

Figure2.LogicDiagram ..........................................................5

Table 1. Signal Names . . . ........................................................5

Figure 3. TSOP Connec tions.......................................................6

Figure 4. TFBGA Connect ions (Top view through package). ..............................7

Figure5.BlockAddresses.........................................................8

Figure6.SecurityBlockMemoryMap................................................8

SIGNALDESCRIPTIONS............................................................9

AddressInputs(A0-A21)..........................................................9

Data I nput /O utpu t (DQ0-DQ15). . . ..................................................9

ChipEnable(E). ................................................................9

Output Enable (G). ..............................................................9

Write E nable (W). . ..............................................................9

WriteProtect(WP)...............................................................9

Reset(RP).....................................................................9

Supply V olt age (2.7V to 3.6V) ..................................................9

Supply Vo lta ge (1.65V to VDD).................................................9

DDQ

ProgramSupplyVoltage ......................................................9

Ground. ...................................................................9

BUSOPERATIONS................................................................10

Read.........................................................................10

Write.........................................................................10

OutputDisable.................................................................10

Standby. . ....................................................................10

Automatic Standby. .............................................................10

Reset........................................................................10

Read Electronic Signature C ommand ...............................................11

Table2.BusOperations.........................................................10

COMMANDINTERFACE ...........................................................11

ReadMemoryArrayCommand....................................................11

ReadStatusRegisterCommand...................................................11

Read Electronic Signature C ommand ...............................................11

ReadCFIQueryCommand.......................................................11

BlockEraseCommand..........................................................11

ProgramCommand.............................................................11

Double Word Program Comm and . .................................................12

ClearStatusRegisterCommand...................................................12

Program/Erase Suspend Command ................................................12

Program/EraseResumeCommand ................................................12

ProtectionRegisterProgramCommand.............................................13

BlockLock-DownCommand......................................................13

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M28W640CT, M28W640CB

Table3.Commands............................................................14

Table4.ReadElectronicSignature.................................................14

Table 5. Read Block Lock Signature ................................................15

Table6.ReadProtectionRegisterandLockRegister ..................................15

Table7.Program,EraseTimesandProgram/EraseEnduranceCycles ....................16

BLOCKLOCKING.................................................................16

LockedState..................................................................16

UnlockedState ................................................................16

Lock-DownState...............................................................17

Reading a Block’s Lock Status . . . .................................................16

LockingOperationsDuringEraseSuspend ..........................................17

Table8.BlockLockStatus .......................................................17

Table9.ProtectionStatus........................................................18

STATUSREGISTER...............................................................19

Program/EraseControllerStatus(Bit7).............................................19

Erase Suspend Status (Bit 6) .....................................................19

EraseStatus(Bit5).............................................................19

ProgramStatus(Bit4)...........................................................19

Status(Bit3)...............................................................19

ProgramSuspendStatus(Bit2)...................................................19

BlockProtectionStatus(Bit1).....................................................20

Reserved(Bit0)................................................................20

Table10.StatusRegisterBits.....................................................20

MAXIMUMRATING................................................................21

Table11.AbsoluteMaximumRatings...............................................21

DCandACPARAMETERS .........................................................22

Table 12. Operating and AC Measurement C onditions..................................22

Figure7.ACMeasurementI/OWaveform ...........................................22

Figure 8. AC Measurement Load Circuit. . . ..........................................22

Table 13. Capacitance...........................................................22

Table14.DCCharacteristics......................................................23

Figure9.ReadACWaveforms....................................................24

Table15.ReadACCharacteristics.................................................24

Figure 10. Write AC Wavef orms, Write Enable Controlled . . .............................25

Table 16. Write AC Characteristics, Write Enable Controlled .............................26

Figure11.WriteACWaveforms,ChipEnableControlled................................27

Table17.WriteACCharacteristics,ChipEnableControlled .............................28

Figure12.Power-UpandResetACWaveforms.......................................29

Table18.Power-UpandResetACCharacteristics ....................................29

PACKAGE MECHANICAL . . . .......................................................30

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M28W640CT, M28W640CB

Figure13.TSOP48-48leadPlasticThinSmallOutline,12x20mm,PackageOutline ........30

Table 19. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package M echanical Data . 30

Figure14.TFBGA48-8x6ballarray,0.75mmpitch,BottomViewPackageOutline .........31

Table20.TFBGA48-8x6ballarray,0.75mmpitch,PackageMechanicalData.............31

Figure 15. TFBGA48 Daisy Chain - Package Connections (Top view through package) ........32

Figure 16. TFBGA48 Daisy Chain - P C B Connections propo sal (Top view through package)....32

PARTNUMBERING ...............................................................33

Table21.OrderingInformationScheme.............................................33

Table22.DaisyChainOrderingScheme............................................33

REVISIONHISTORY...............................................................34

Table23.DocumentRevisionHistory...............................................34

APPENDIX A. BLOCK ADDRESS TABLES . . ..........................................35

Table 24. Top Boot Block Addresses, M28W640CT....................................35

Table25.BottomBootBlockAddresses,M28W640CB.................................37

APPENDIXB.COMMONFLASHINTERFACE(CFI) .....................................39

Table26.QueryStructureOverview................................................39

Table 27. CFI Query Identification String . . ..........................................39

Table28.CFIQuerySystemInterfaceInformation.....................................40

Table29.DeviceGeometryDefinition...............................................41

Table 30. Primary Algorithm-Specific Extended Query Table .............................42

Table31.SecurityCodeArea.....................................................43

APPENDIX C. FLOWCHARTS AND P SEUDO CODES....................................44

Figure 17. Program Flowchart and Pseudo Code . . ....................................44

Figure 18. Double Word P rogram Flowchart and Pseudo Code ...........................45

Figure 19. Quadruple Word Program Flowchart and Pseudo Code . .......................46

Figure 20. Program Suspend & Resume Flowchart and Pseudo Code .....................47

Figure 21. Erase Flowchart and Pseudo Code ........................................48

Figure 22. Erase Suspend & Resume Fl owchart and Pseudo Code. .......................49

Figure 23. Locking Operations Flowchart and Pseudo Code .............................50

APPENDIXD.COMMANDINTERFACEANDPROGRAM/ERASECONTROLLERSTATE.......52

Table32.WriteStateMachineCurrent/Next,sheet1of2................................52

Table33.WriteStateMachineCurrent/Next,sheet2of2................................53

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SUMMARY DESCRIPTION

The M28W640C is a 64 Mbit (4 Mbit x 16)non-volatileFlashmemorythatcanbeerasedelectrically at the block leveland programmed in-system on a Word-by-Word basis. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. V

1.65V. An optional 12V V

allows to drive the I/O pin down to

DDQ

power supply is pro-

vided to speed up customer programming. The device features an asymmetrical blocked ar-

chitecture. The M28W640C has an array of 135 blocks: 8 Parameter Blocks of 4 KWord and 127 Main Blocks of 32 KWord. M28W640CT has the Parameter Blocks at the top of the memory address space while the M28W640CB locates the Parameter Blocks starting from the bottom. The memory maps are shown in Figu re 5, Block Addresses.

The M28W640C features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When V

≤ V

all blocksare protected against

PPLK

program or eras e. All blocks are locked at Power Up.

Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resum ed. Program can be sus pended to read d ata in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles.

The device includes a 192 b it Protection Register and a Security Block to increase the protection of a system design. The Protection Register is divided into a 64 bit segment and a 128 bit segment. The 64 bit segment contains a unique device number written by ST, while the second one is onetime-programmable by the user. The user programmable segment can be permanently prot ec ted. The Security Block, parameter block 0, can be permanently protected by the user. Figure 6, shows the Security Block M emory Map.

Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Control ler takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

M28W640CT, M28W640CB

ThememoryisofferedinTSOP48(12X20mm) and TFBG A48 (0.75mm pitch) packages and is suppliedwithallthebitserased(setto’1’).

Figure 2. Logic Diagram

DDQVPP

A0-A21

M28W640CT M28W640CB

Table 1. Signal Names

A0-A21 Address Inputs DQ0-DQ15 Data Input/Output E G W RP WP V

DDQ

NC Not Connected Internally

Chip Enable Output Enable Write Enable Reset Write Protect Core Power Supply Power Supply for

Input/Output Optional Supply Voltage for

Fast Program & Erase Ground

DQ0-DQ15

AI04378

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M28W640CT, M28W640CB

Figure 3. TSOP Connections

A15 A14 A13 A12 A11

A16 V

DDQ

DQ15 DQ7

A10 DQ14

37 36

DQ6 DQ13 DQ5 DQ12 DQ4 V

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G V

E A0

A21 A20

WP A19 A18 A17

A9 A8

A7 A6 A5 A4 A3 A2 A1

M28W640CT M28W640CB

24 25

AI04379

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Figure 4. TFBGA Connections (Top view through package)

M28W640CT, M28W640CB

87654321

A13

DDQ

DQ7V

A8A11

DQ13

RP A18

A21

DQ11

DQ12

DQ4

WP A19

A20

DQ2

A7V

DQ0DQ9DQ3DQ6DQ15V

DQ1DQ10V

A2A5A17WA10A14

A1A3A6A9A12A15

A0EDQ8DQ5DQ14A16

AI04380

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M28W640CT, M28W640CB

Figure 5. Block Addresse s

M28W640CT

Top Boot Block Addresses

3FFFFF

3FF000

3F8FFF

3F8000

3F7FFF

3F0000

00FFFF

008000

007FFF

000000

Note: Also see Appendix A, Tables 24 and 25 for a full listing of the Block Addresses.

4 KWords

Total of 8

4 KWord Blocks

4 KWords

32 KWords

Total of 127

32 KWord Blocks

32 KWords

Bottom Boot Block Addresses

3FFFFF

3F8000 3F7FFF

3F0000

00FFFF

008000

007FFF

007000

000FFF

000000

M28W640CB

32 KWords

Total of 127

32 KWord Blocks

32 KWords

4 KWords

Total of 8

4 KWord Blocks

4 KWords

AI04386

Figure 6. Security Block Memory Map

Parameter Block # 0

8Ch

85h 84h

81h 80h

User Programmable OTP

Unique device number

Protection Register Lock 2 1 0

AI04397

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SIGNAL DESCRIPTIONS

See Fig ure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signalsconnected to this device.

Address Inputs (A0-A21). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Int erface of the int ernal state machine.

Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at t he s elected address during a Bus Read operation or inputs a command orthedatatobeprogrammedduringaWriteBus operation.

Chip Enable (E

). The Chip Enable input acti-

vates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is

and Reset is at VIHthe device is in active

at V

mode. When Chip Enable is at V

the m emory is

deselected, the outputs are hi gh impedance and the power consumption is reduced to the stand-by level.

Output Enable (G

). The Output Ena ble controls

data outputs during the Bus Read operation of the memory.

WriteEnable(W

). Th e Write E nable controls the

Bus Write operation of the memory’s Command Interface. The dataand address inputs are latched ontherisingedgeofChipEnable,E,orWriteEnable, W

Write Protect (WP

, whichever occurs first.

). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at V

, the Lock-

Down is enabled and the protection status of the block cannot be c hanged. When Write Protect is at V

, the Lock-Down is disabled and the block can

be lock ed or unlocked. (refer to Table 6, ReadProtection Register and Protection Register Lock).

Reset (RP

wareresetofthememory.WhenResetisatV

). The Reset input provides a hard-

the memory is in reset mode: the outputs are high impedance and the current consumption is minimized. After Reset all blocks are in the Locked state. WhenRe set is at V

, thedevice is in normal

M28W640CT, M28W640CB

operation. Exiting reset mode the device enters read array mode, but a negative trans ition of Chip Enable or a change of the address is required to ensure valid data outputs.

Supply Voltage (2.7V to 3.6V). VDDpro-

vides the power supply t o the internal core of the memory dev ice. It is the main power supply for all operations (Read, Program and Erase).

Supply Voltage (1.65V to VDD). V

DDQ

provides the power supply to the I/O pins and enables all Outputs to be powered independently from V

DD.VDDQ

separate supply.

Program Supply Voltage. VPPis both a

control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. The Supply Voltage V Program Supply Voltage V anyorder.

is kept in a low voltage range (0V to 3.6V)

If V

is seen as a control input. In this case a volt-

age lower than V against program or erase, while V ables these func tions (see Table 14, DC Characteristics for the relevant values). V sampled at the beginning of a program or eras e; a change in its value after the operation has started does not have any effect on Program or Erase, however for Double or Quadruple Word Program the results are uncertain.

If V

is in the range 11.4V to 12.6V it acts as a

power supply pi n. In this condition V stable until the Program/Erase algorithm is completed (see Table 16 and 17).

Ground. VSSis the reference for all voltage

measurements.

Note: Each device i n a system should have V

DD,VDDQ

pacitor close to the pin. See Figure 8 , AC Mea-

surement Load Circuit. Th e P CB trace widths should be sufficient to carry the required V program and erase currents.

canbetiedtoVDDor can use a

canbeappliedin

gives an absolute protection

PPLK

and VPPdecoupled with a 0.1µF ca-

DDQ

and the

en-

PP1

is only

must be

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M28W640CT, M28W640CB

BUS OPERATIONS

There are s ix standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby, Automatic Standby and Reset. See Table 2, B us Operations, for a summary.

Typically glitch es of less t han 5ns on Chip Enable or Write Enable areignored by the memory and do not affect bus operations.

Read. Read B us operations are used to ou tput the contents of the Memory Array, the Electronic Signature, the Status R egister and the Comm on Flash Interface. Both Chip E nable and Output EnablemustbeatV eration. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data r ead depends on the previous command written to the memory (see Command Interface s ec tion). See Figure 9, Read Mode AC Waveforms , a nd Table 15, Read AC Charac t erist ics, for details of when the output becomes valid.

Read mode is the default stat e of t he device when exiting Reset or after power-up.

Write. B us Write operations write Commands to the memory or latch Input Data to be programmed. A write operation is initiated when Chip Enable and Write Enable are at V

. Commands, Input Data and Addresses are

latched on the rising edge of Write Enable or Chip Enable, whichever occurs first.

in order to perform a read op-

with Output Enable at

See Figures 10 and 1 1, WriteAC Waveforms, and Tables 16 and 17, Write AC Characteristics, for details of the timing requirements.

Output Disable. The data outputs are high impedance when the Output Enable is at V

Standby. S tandby disables most of the internal circuitryallowing a substantial reduction of t he current consumption. The memory is in stand-by when Chip Enable is at V

andthedeviceisin

read mode. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from theOutput E nable or Write Enable inputs. If Chip Enable switches to V

during a program or erase operation, the de-

vice enters Standby mode when finished. Automatic Standby. Automatic Standby pro-

vides a low power cons umption state during Read mode. Following a read operation, the device enters Automatic Standby after 150ns of bus inactivity even if Chip Enable is Low, V current is reduced to I

. The data I nputs/Out-

DD1

, and the supply

puts will still output data if a bus Read operation is in progress.

Reset. During Reset mode when Output Ena ble is Low, V

, the memory is deselec ted andthe ou t-

puts are high impedance. The memory is in Reset mode when Reset is at V

. The power consump-

tion is reduc ed to the Standby level, independent ly from the Chip Enable, Output Enable or Write E nable inputs. If Reset is pulled to V

during a Pro-

gram or Erase, this operation is aborted and the memory conten t is no longer valid.

Table 2. Bus Operations

Operation E G W RP WP

Bus Read Bus Write Output Disable Standby Reset X X X

Note: X = VILor VIH,V

10/54

V V V

=12V±5%.

PPH

X Don't Care Data Output

X X Don't Care Hi-Z X Don't Care Hi-Z X Don't Care Hi-Z

or V

PPH

DQ0-DQ15

Data Input

COMMAND INTERFACE

All B us Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Pr ogram/Erase Controller provides a Status Register whose output may be read at any time during, to monitor the progress of the operation, or the Program/Erase states. See Appendix 22, Table 32, Write State Machine Current/Next, for a summary of the Command Interface.

The Command Interface is res et to Read mode when power is f irst applied, when exiting from R eset or whenever V

is lower than V

LKO

.Command sequences must be followed exactly. A ny invalid c ombination of c ommands will reset the device to Read mode. Refer to Table 3, Commands, in conjunction with the text descriptions below.

Read Memory Array Command

TheReadcommandreturnsthememorytoits Read mode. O ne Bus Write cycle is requ ired toissue the Read Mem ory Array command and return the memory to Read mode. S ubs equent read operations will read the addressed location and output the data. When a device Reset occ urs, the memory defaults to Read m ode.

Read Status Register Command

The Status Regist er indicates when a program or erase operation is complete and the success or failure of the operation itself. Issue a Read Status Register command to read the Stat us Register’s contents. Subsequent Bus Read operations read the Status Register at any address, u nti l another command isissued. See Table 10, Status Register Bits, for details on the definitions of the bits.

The Re ad Status Register command may be issued at any time, even during a Program/Erase operation. Any Read atte mpt during a Program/ Erase operation will automatically output the content of the Status Register.

Read Electronic Signature Command

The Read Electronic Sig natu re command reads the Manufacturer and Device Codes and the B lock Locking S tatus, or the Protection Regis ter.

The Read Electronic Signature command consists of one write cycle, a subsequent read will output the Manufacturer Code, the D ev ice Code, the Block Lock and Lock-Down Status, o r the Protection and Lock R egister. S ee Tables 4, 5 and 6 for the valid address.

Read CFI Query Command

The Read Query Command is used t o read dat a from the Commo n Flash Interface (CFI) Memory Area, allowing programming equi pment or appli-

M28W640CT, M28W640CB

cations to automatically match their interface to the characteristics of t he device. One Bus Write cycle is required to issue the Read Query Com mand. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. See Appendix B, Common Flas h Interface, Tables 26, 27, 28, 29, 30 and 31 for det ails on the information c ontained in the Common Flash Interface memory area.

Block Erase Command

TheBlockErasecommandcanbeusedtoerase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the Erase operation w ill abort, the data in the block will not be changed and the Status Register will output the error.

Two Bus Write cycles are required to issue the command.

■ Th e first bus cycle sets up the Erase com mand.

■ Th e second latches the block addres s in the

internal state machine and starts the P ro gram/ Erase Co ntroller.

If the second bus cycle is not Write Erase Co nfirm (D0h), S ta tus Register bits b4 and b5 are s et and the command aborts.

Erase aborts if Reset turns to V cannot beguaranteed when t he Erase operation is aborted, the block must be erased agai n.

During Erase operations the mem ory will accept the Read S tatus Register command and the Program/Erase Suspend command, all other commands will be ignored. Typical Erase times are given in Table 7, Program , Erase Times and Program/Erase End uranc e Cycles.

See Appendix C, Figure 21, Erase Flowchart and Pseudo Code, for a suggested flowchart for using the Erase command.

Program Command

The memory array can be programmed word-byword. Two bus write cycles are required to issue the Program Command.

■ Th e first bus cycle s ets up the Program

command.

■ Th e second latchesthe Address and the Datato

be written and starts the Program/Erase Controller.

During Program operations the memory will accept the Read Status Register command and the Program/Erase S uspend com mand. Typical Program times are given in Table 7, Program, Erase Times and Program/Erase Endurance Cycles.

Programming aborts if Reset goes to V integrity cannot be guaranteed when the program operation is aborted, the block containing the

. As data integrity

. A s data

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M28W640CT, M28W640CB

memory location must be erased and reprogrammed.

See Appendix C, Figure 17 , Program Flowchart and Pseudo Code, for the flowchart for using the Program command.

Double Word Program Command

Thisfeat ure is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two words must di ffer on ly for t he address A0. P r ogramming should not be attempted when V executed if V

isnot at V

is below V

PPH

. The command can be

but the result is not

PPH

guaranteed. Three bus write cycles are necessary to issue the

Double Word Program command.

■ Th e first bus cycle sets up t he Double Word

Program Command.

■ The second bus cycle l atches the Address and

theDataofthefirstwordtobewritten.

■ The third bus cycle latches the Address and the

Data ofthe second word to be written and starts the Program/Erase Controller.

Read operations output the Status Register content after the programm ing has started. Programming aborts if Reset goes to V

. As data integrity

cannot be guaranteed when the program operation is aborted, the block containing the memory location mu st be erased and repro gramm ed.

See Appendix C, Figure 18, Double Word Program Flowchart and Pseudo Code, for the f lowchart for using the Double Word Program command.

Quadruple Word Program Command

Thisfeat ure is offered to improve the programming throughput, writing a page of four adjacent words in parallel.The four words must differ only for the addresses A0 andA1. Program ming s hould not be attempted when V

can be executed if V

isnotatV

is below V

.The command

PPH

but theresult

PPH

is not guaranteed. Five bus write c ycles are necessary to issue the

Quadruple Word Program command.

■ Th e first bus cycle sets up t he Double Word

Program Command.

■ The second bus cycle l atches the Address and

theDataofthefirstwordtobewritten.

■ The third bus cycle latches the Address and the

Data of the second word to be writte n.

■ The fourth bus cycle latches the Address and

theDataofthethirdwordtobewritten.

■ The fifth bus cycle latches the Address and the

Data of the fourth wo rd tob e written and starts the Program/Erase Controller.

Read operations output the Status Re gister content after the programm ing has started. Programming aborts if Reset goes to V

. As data integrity

cannot be guaranteed when the program operation is aborted, the block containing the memory location mu st be erased and repro gramm ed.

See Appendix C, Figure 19, Quadruple Word Program Flowchart and Pseudo Code, for the f lowchart for usin g the Quadruple Word Program command.

Clear Status R egister Command

The Clear Status Register command can be us ed to reset bits 1, 3, 4 and 5 in the Status Register t o ‘0’. One bus write cycle is required t o issue the Clear Status Register command.

The bits in the StatusRegiste r donot automatically return to ‘0’ when a n ew Program or E r as e command is issued. The error bits in the Status Register should be cleared before attempting a new Prog ram or Erase command.

Program/Erase Suspend Command

The Program/Erase Sus pend command is used to pause a Pr ogram or Erase operation. One bus write cycle is required to iss ue the Program/Erase command and pause the Program/Erase controller.

During Program/Erase Suspend the Co mmand Interface will accept the Program/E ras e Resu me, Read A rray , Read Status Register, Read E lectronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Program, Double Word Program, Quadruple Word Program, Block Lock, B lock Lock-Down or Protection Program commands will also be accepted. Th e block being erased may be pro tected by issuing the Block Protect, Block Lock or Protection Program commands. When the Program/ Erase Resume command is issued the operation will complete. Only the blocks not being erased may be read or prog ramm ed correctly.

During a Program/Erase Su sp end, the device can be placed in a pseudo-standby mode by taking Chip Enable to V Reset t urns to V

. Program/Erase i s aborted if

See Appendix C, Figure 20, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 22, Erase Sus pend & Resume Flowchart and Pseudo Codefor flowcharts for using the Program/ Erase Suspend command.

Program/Erase Resume Command

The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus W rite cycle is required to issue the command. Once the command is issued subse-

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M28W640CT, M28W640CB

quent Bus Read operations read t he Status Register.

Protection Register Program Command

The Protection R egister Program command is used to Program the 128 bit user One-Time-Programmable (OTP) segment of the Protection Register. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to ‘1’. The user can onlyprogram the bits to ‘0’.

Two write cycles are required to issue the Protection Register Program command.

■ Th e first bus cycle s ets up the Protection

■ Th e second latchesthe Address and the Datato

be written to the Protection Register and starts the Program/Erase Controller.

Read operations output the Status Register content after the programming has started.

The segment can be prot ec ted by programming bit 1 of t he Protection Lock Register. Bit 1 of the Protection Lock Register protects bit 2 of the Protection Lock Register. Programming bit 2 of the Protection Lock Register will result in a permanent protection of the Security Block (see Figure 6, Security Block Memory Map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection Register and/or the Security Block is not reversible.

The Protection Register Program ca nnot be suspended.

Block Lock Command

The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are lock ed at power-up or reset.

Two Bus Write cycles are required to issue the Block Lock command.

■ Th e first bus cycle s ets up the Block Loc k

command.

■ The second Bus W rite cycle latches the block

address.

The lock status can be monitored for each block using the Read Electronic Signature command. Table. 9 shows the protection status after issuing a Block Lock command.

The Block Lock bits are volatile, onc e set they remain set until a hardware reset or power-down/ power-up. They are cleared by a Blo cks Unlock command. Refer to the section, Block Locking, for a detailed explanation.

Block Unlock Command

The Blocks Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Blocks Unlock command.

■ Th e first bus cycle s ets up the Block Unlock

command.

■ The second Bus W rite cycle latches the block

address.

The lock status can be monitored for each block using the Read Electronic Signature command. Table. 9 shows the protection status after issuing a Block Unlock command. Refer to t he section, Block Locking, for a detailed explanati on.

Block Lock-Down Command

A locked block cannot be Programmed or Erased, or have its protection status changed when WP low, V

.WhenWPis high, V

the Lock-Down

IH,

function is disabled and the lock ed blocks can be individually unlocked by the Block Unlock command.

Two Bus Write cycles are required to issue the Block Lock-Down command.

■ Th e first bus cycle s ets up the Block Loc k

command.

■ The second Bus W rite cycle latches the block

address.

The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table. 9 shows the protection status after issuing a Block Lock-Down command. Refer to the section, Block Lockin g, for a detailed explanation.

13/54

M28W640CT, M28W640CB

Table 3. Commands

Bus Write Operations

Commands

Read Memory Array

Read Status Register

Read Electronic Signature

Read CFI Query 1+ Write X 98h Read QA QD Erase 2 Write X 20h Write BA D0h

Program 2 Write X

Double Word Program

QuadrupleWord Program

Clear Status Register

Program/Erase Suspend

Program/Erase Resume

Block Lock 2 Write X 60h Write Block Unlock 2 Write X 60h Write Block Lock-Down 2 Write X 60h Write Protection Register

Program

Note: 1. X = Don't Care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ID=Identifier (Manufacture and Device Code),

(3)

(4)

QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection Register Data.

2. The signature addresses are listed in Tables 4, 5 and 6.

3. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0.

4. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.

1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle

Cycles

Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data

1+ Write X FFh

1+ Write X 70h Read X SRD

1+ Write X 90h Read

40h

10h

3 Write X 30h Write PA1 PD1 Write PA2 PD2

5 Write X 55h Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4

1Write X 50h

1Write X B0h

1Write X D0h

RA RD

Read

(2)

IDh

Write PA PD

01h

BA BA D0h

2Fh

2 Write X C0h Write

PRA PRD

Table 4. Read Electronic Signature

Code Device E G W A0 A1 A2-A7 A8-A21 DQ0-DQ7 DQ8-DQ15

Manufacture. Code

M28W640CT

Device Code

M28W640CB

Note: RP =VIH.

14/54

IHVIL

0 Don't Care 20h 00h

0 Don't Care 48h 88h 0 Don't Care 49h 88h

M28W640CT, M28W640CB

Table 5. Read Block Lock Signature

Block Status E G W A0 A1 A2-A7 A8-A11 A12-A21 DQ0 DQ1 DQ2-DQ15

Locked Block Unlocked Block Locked-Down

Block

Note: 1. A Locked-Down Block can be locked "DQ0 = 1" or unlocked "DQ0 = 0"; see Block Locking section.

ILVILVIHVILVIH

VILVILVIHVILV

ILVILVIHVILVIH

0 Don't Care Block Address 1 0 00h 0 Don't Care Block Address 0 0 00h

0 Don't Care Block Address

Table 6. Read Protection Register and Lock Register

Word E

Lock

Unique ID 0 Unique ID 1 Unique ID 2 Unique ID 3 OTP 0 OTP 1 OTP 2 OTP 3 OTP 4 OTP 5 OTP 6 OTP 7

G W A0-A7 A8-A21 DQ0 DQ1 DQ2 DQ3-DQ7 DQ8-DQ15

ILVILVIH

VILVILV V

ILVILVIH

VILVILV V

ILVILVIH

80h Don'tCare 0

OTP Prot.

data 81h Don't Care ID data ID data ID data ID data ID data 82h Don't Care ID data ID data ID data ID data ID data

83h Don't Care ID data ID data ID data ID data ID data 84h Don't Care ID data ID data ID data ID data ID data 85h Don't Care OTP data OTP data OTP data OTP data OTP data 86h Don't Care OTP data OTP data OTP data OTP data OTP data 87h Don't Care OTP data OTP data OTP data OTP data OTP data 88h Don't Care OTP data OTP data OTP data OTP data OTP data 89h Don't Care OTP data OTP data OTP data OTP data OTP data

8Ah Don't Care OTP data OTP data OTP data OTP data OTP data

8Bh Don't Care OTP data OTP data OTP data OTP data OTP data 8Ch Don't Care OTP data OTP data OTP data OTP data OTP data

Security

prot. data

(1)

00h 00h

1 00h

15/54

M28W640CT, M28W640CB

Table 7. Program, Erase Times and Program/Erase Endurance Cycles

Parameter Test Conditions

Word Program Double Word Program Quadruple Word Program

Main Block Program

Parameter Block Program

Main Block Erase

Parameter Block Erase

Program/Erase Cycles (per Block) 100,000 cycles

Note: 1. Typicaltime to programa Main or Parameter Blockusing the Double WordProgram andtheQuadrupleWord Program commands

respectively.

PP=VDD

= 12V ±5%

PP=VDD

= 12V ±5%

PP=VDD

= 12V ±5%

PP=VDD

= 12V ±5%

PP=VDD

Min Typ Max

M28W640C

10 200 µs 10 200 µs 10 200 µs

0.16/0.08

0.02/0.01

(1)

0.32 5 s

(1)

0.04 4 s 110s 110s

0.8 10 s

Unit

BLOCK LOCKING

The M28W640C features an instant, individual block locking scheme that allows any block to be lockedorunlockedwithnolatency.Thislocking scheme has three levels of protection.

■ Lock/Unlock - this first level allows software-

only contro l of block locking.

■ Lock-Down - this second level requires

hardware interaction before locking can be changed.

■ V

≤ V

- the third level of fers a complete

PPLK

hardware prot ection against program anderase on all blocks.

Theprotectionstatusofeachblockcanbesetto Locked, Unlocked, and Lock-Down. Table 9, defines all of the possible protection states (WP DQ1, DQ0), and Appendix C, F igure 23, shows a flowchart for the locking operations.

ReadingaBlock’sLockStatus

The lock s ta tus of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subsequent reads at the address spe cified in Table 5, will output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Loc k command and cleared by the Unlock

command. It is also automatically set when enteringLo ck-Down . DQ1 indicates the Lock-Down status and is set by the Lock-Down c ommand. It cannot be cleared by software, only by a hardware reset or power-down.

The following sections explain theoperation ofthe locking system.

Locked State

The defau lt status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). L oc ked block s are fully protec te d from any program or erase. Any program or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software com-

mands.An Unlocked block can be Locked by issuing the Lock command.

Unlocked State

Unlocked b lock s (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a h ardware reset or when the device is powered-down. The status of an unlocked bloc k can be changed to Locked or Locked-Down using the appropriate software commands. A lo cked block can be unlocked by issuing the Unlock command.

16/54

M28W640CT, M28W640CB

Lock-Down State

Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Loc k ed blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. LockedDown blocks revert to the Locked state when the device is reset or powered-down.

The Lock-Down fu nction is dependent on the WP input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When WP

=1 (VIH) the Lock-Down function is disabled (1,1,1) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by iss uing the software comm and, where they can be erasedand programmed. These blocks c an then be relocked (1,1,1) and unlocked (1,1,0) as desired while WP remains high. When WP is low , blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WP

was high. Device reset or power-down resets all blocks , including those in Lock-Down, to the Locked state.

Locking Operations During Erase Suspend

Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress.

To change block locking d uring an erase operation, first write the Erase Suspend command, then check the status registe r until it indicates that the erase operation has been suspended. Next write the desired Lock com mand sequence to a block and the lock status will be changed. After completing any des ired lock, read, or program operations, resume the erase operation with the Erase Resume com mand.

If a block is locked or locked-down during an erase suspend of the same bl ock, the locking status bits will be changed immediately, but when the erase is resumed, the erase operat ion will complete.

Locking operations cannot be performed during a program su sp end. Refer to Appendix D, Command Interface and Program/Erase Controller State, for detailed information on which commands are valid during erase suspend.

Table 8. Block Lock Status

Item Address Data

Block Lock Configuration

Block is Unlocked DQ0=0

Block is Locked DQ0=1

Block is Locked-Down DQ1=1

LOCK

xx002

17/54

M28W640CT, M28W640CB

Table 9. Protection Status

Protection Status

(WP, DQ1, DQ0)

Current State

Current

Program/Erase

(1)

Allowed

After

Block Lock

Command

Next Protection Status

(WP, DQ1, DQ0)

After

Block Unlock

Command

1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0

1,0,1

(2)

no 1,0,1 1,0,0 1,1,1 0,0,1

1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0

0,0,1

(2)

no 0,0,1 0,0,0 0,1,1 1,0,1

0,1,1 no 0,1,1 0,1,1 0,1,1

Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read

in the Read Electronic Signature command with A1 = V

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP

3. A WP

transition to VIHon a locked block will restore the previous DQ0 value, giving a 111 or 110.

andA0=VIL.

(1)

After Block Lock-Down

Command

status.

After

transition

1,1,1 or 1,1,0

(3)

18/54

STATUS REGISTER

The Status Register provides information on t he current or previous Program or Erase operation. The various bits convey information and errors on the operation. To read the Status register the Read S t atusRegiste r command can be issued, refer to Read Status Regist er Command section. To output the contents, the S tatus Register is latched on the falling edge of the Chip Enable or Output Enable signals, and can be read untilChip Enable or Output Enable returns to V

. Either Chip En-

able or Output Ena ble must be toggled to update the latched data.

Bus R ead operations from any address always read the Status Register during P rogram and Erase operations.

The bits in the Status Register are summarized in Table 10, Status Register Bits. Refer to Table 10 in conjunction with the following text descriptions.

Program/Erase Controller Status (Bit 7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is Low (set to ‘0’), the Program/Erase Controller is active; when the bit is High (set to ‘1’), t he Program/Erase Controller is inactive, and the device is ready to process a new command.

The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High .

During Program, Erase, o perat ions t he Program/ EraseControllerStatusbitcanbepolledtofindthe end of t he operation. Other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High.

After the Program/Erase Controller completes its operation the Erase Status, Program S tatus, V

Status andBlock Lock Status bitsshould be tested for errors.

Erase Suspend Status (Bit 6). T he Erase Suspend Status bit indicates that an Erase operation has been sus pended or is going to be suspended. When the Erase Suspend Status bit is H igh (set to ‘1’), a Program/Erase S uspend c ommand has been issued and the memory is waiting for a Program/Erase Resu me command.

The Erase Suspend Status should only be considered valid when the Program/EraseC ontroller Status bit is High (Program/Erase Controller inactive). Bit 7 is set within 30µs of the Program/Erase Suspend command being issued the re fore thememory may still complete the operation rather t han entering the Suspend mode.

M28W640CT, M28W640CB

When a Program/Erase Resu me command is issued the Erase Suspend S tatus bit returns Low.

Erase Status (Bit 5). The Erase S tatus bit ca n be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase Status bit is High (set to ‘1’), the Program/ Erase Controller has appl ied the maximum number of pulses to the block and still failed to verify thatthe block has erased c orrectly. The Erase Status bit s hould be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive).

Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to f ail.

Program Status (Bit 4). The Program Status bit is used to identify a Program failure. When the Program Status bi t is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the byte and still fai led to verify that it has programmed correctly. The Program Status bit should be r ead once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive).

Once set High, t he Program Status bit can only be reset Low by a C lear Status Register command or a hardware reset. Ifset Highit shouldbe reset before a new command is iss ued, otherwise the new command will appear to fail.

Status (Bit 3). The VPPStatus bit can be

used to identify an invalid voltage on the V during Program and Eras e operations. The V pin is only sampled at the begi nning of a Program or Erase operation. Indeterminate results can occur if V

When the V age on the V when the V

becomes invalid during an operation.

Status bitis Low (set to ‘0’),the volt-

pin was sampled at avalid voltage;

Status bit is High (set to ‘1’), the V

pin has a voltage that is below the VPPLockout Voltage, V

, the mem ory is protected and Pro-

PPLK

gram and Erase operations cannot be performe d. Onceset High,the V

Status bitcan only be reset

Low by a Clear Status Register comman d or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to f ail.

Program Suspend Status (Bit 2). The Program Suspend Status bitindicates that a Program operation has been suspended. When the Program Suspend S tatus bit is High (set to ‘1’), a Program/ Erase Suspend command has been issued and the memory is waitin g f or a Program/Erase Resume command. The Program Suspend Status should only be considered valid when the Pro-

19/54

M28W640CT, M28W640CB

gram/Erase Controller Status bit i s High (Program/ Erase Controller inactive). Bit 2 is s et within 5µs of the Program/Erase Suspend command being issued therefo re the memory may still complete the operation rather than entering the Suspend mode.

When a Program/Erase Resu me command is issued the P rogram Susp end Status bit returns Low.

Block Protection Status (Bit 1). The Block ProtectionStatusbitcanbeusedtoidentifyifaProgram or Erase operation has tried to m odify the contents of a locked block.

When the Block Protection Status bit is High (set to ‘1’), a Program or Erase operation has been attemptedonalockedblock.

Once set Hi gh, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail.

Reserved (Bit 0). Bit 0 of th e Status Register is reserved. Its v alue must be masked.

Note: Refer to Appendix C, Flowcharts and Pseudo Codes, for using the Status Register.

Table 10. Status Register Bits

Bit Name Logic Level Definition

7 P/E.C. Status

6 Erase Suspend Status

5 Erase Status

4 Program Status

'1' Ready '0' Busy '1' Suspended '0' In progress or Completed '1' Erase Error '0' Erase Success '1' Program Error '0' Program Success

Status

2 Program Suspend Status

1 Block Protection Status

0 Reserved

Note: Logic level '1' is High, '0' is Low.

'1' '0' '1' Suspended '0' In Progress or Completed '1' Program/Erase on protected Block, Abort '0' No operation to protected blocks

VPPInvalid, Abort

20/54

MAXIMUM RATING

Stressingthedeviceabovetheratinglistedinthe Absolute Maximum R atings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above t hos e indicated in the Operating sections of this specification is not im-

Table 11. Absolute Maximum Ratings

Symbol Parameter

BIAS

STG

DD,VDDQ

Note: 1. Depends on range.

Ambient Operating Temperature Temperature Under Bias – 40 125 °C Storage Temperature – 55 155 °C Input or Output Voltage – 0.6 Supply Voltage – 0.6 4.1 V Program Voltage – 0.6 13 V

(1)

M28W640CT, M28W640CB

plied. Exposure to Absolute Maximum Rating conditions for extended periods may af fect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

Value

Min Max

–40 85 °C

+0.6

DDQ

Unit

21/54

M28W640CT, M28W640CB

DC AND AC PARAMETERS

This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests perform ed under the Meas ure-

Table 12. Operating and AC Measurement Conditions

ment Conditions summarized in Table 12, Operating and AC Measurement Conditions. Designers should check that theoperating conditions in their circuit match the measurement conditions when relying on the quote d parameters.

M28W640CT, M28W640CB

Parameter

80 90

Min Max Min Max

Supply Voltage

Supply Voltage (V

DDQ

≤ V

)

3.0 3.6 2.7 3.6 V

2.7 3.3 2.7 3.3 V

Ambient Operating Temperature – 40 85 – 40 85 °C Load Capacitance (C

)

50 50 pF Input Rise and Fall Times 5 5 ns Input Pulse Voltages Input and Output Timing Ref. Voltages

0toV

DDQ

/2 V

DDQ

0toV

DDQ

Figure 7. AC Measurement I/O Waveform Figu re 8. AC Measurement Load Circuit

DDQ

AI00610

DDQ

25kΩ

DEVICE

UNDER

TEST

Units

V V

0.1µF

CL includes JIG capacitance

Table 13. Capacitance

Symbol Parameter Test Condition Min Max Unit

OUT

=0V

6pF

12 pF

OUT

Note: Sampled only, not 100% tested.

Input Capacitance Output Capacitance

22/54

25kΩ

AI00609C

M28W640CT, M28W640CB

Table 14. DC Characteristics

Symbol Parameter Test Condition Min Typ Max Unit

DD1

DD2

DD3

DD4

DD5

PP1

PP2

PP3

PP4

PP1

PPH

PPLK

LKO

Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Stand-by or

Automatic Stand-by) Supply Current

(Reset)

Supply Current (Program)

Supply Current (Erase)

Supply Current (Program/Erase Suspend)

Program Current (Read or Stand-by)

Program Current (Reset)

Program Current (Program)

Program Current (Erase)

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage Program Voltage (Program or

Erase operations) Program Voltage

(Program or Erase operations)

Program Voltage (Program and Erase lock-out)

VDDSupply Voltage (Program and Erase lock-out)

0V≤ V

=VSS,G=VIH,f=5MHz

Program in progress

Erase in progress

Erase suspended

Program in progress

Erase in progress

= 100µA, VDD=VDDmin,

DDQ=VDDQ

= –100µA, VDD=VDDmin,

DDQ=VDDQ

≤ V

DDQ

≤ V

OUT≤VDDQ

DDQ

±0.2V,

± 0.2V

=VSS± 0.2V

=12V±5%

PP=VDD

=12V±5%

PP=VDD

DDQ

PP>VDD

≤ V

±0.2V,

=VSS± 0.2V

=12V±5%

PP=VDD

=12V±5%

PP=VDD

≥ 2.7V

DDQ

≥ 2.7V 0.7 V

DDQ

min

±1 µA

±10 µA

10 20 mA 15 50 µA

15 50 µA

10 20 mA

520mA

50 µA

400 µA

5µA 5µA

10 mA

5µA

10 mA

5µA

–0.5 0.4 V –0.5 0.8 V

–0.4 V

DDQ

DDQ DDQ

+0.4 +0.4

0.1 V

–0.1

DDQ

1.65 3.6 V

11.4 12.6 V

V V

23/54

M28W640CT, M28W640CB

Figure 9. Read AC Waveforms

tAVAV

A0-A21

tAVQV

tELQX

tGLQX

DQ0-DQ15

ADDR. VALID

CHIP ENABLE

Table 15. Read AC Characteristics

Symbol Alt Parameter

AVAV

AVQV

AXQX

EHQX

EHQZ

ELQV

ELQX

GHQX

GHQZ

GLQV

GLQX

Note: 1. Sampled only, not 100% tested.

2. G

Address Valid to Next Address Valid Min 80 90 ns

Address Valid to Output Valid Max 80 90 ns

ACC

(1)

Address Transition to Output Transition Min 0 0 ns

(1)

Chip Enable High to Output Transition Min 0 0 ns

(1)

Chip Enable High to Output Hi-Z Max 20 25 ns

(2)

Chip Enable Low to Output Valid Max 80 90 ns

(1)

Chip Enable Low to Output Transition Min 0 0 ns

(1)

Output Enable High to Output Transition Min 0 0 ns

(1)

Output Enable High to Output Hi-Z Max 20 25 ns

(2)

Output Enable Low to Output Valid Max 20 30 ns

(1)

Output Enable Low to Output Transition Min 0 0 ns

OLZ

maybe delayedby up to t

ELQV-tGLQV

after the falling edge of E without increasingt

tELQV

tGLQV

OUTPUTS ENABLED

VALID

tEHQX

tEHQZ

tGHQX

tGHQZ

VALID

DATA VALID STANDBY

M28W640C

80 90

ELQV

tAXQX

AI04387

Unit

24/54

Figure 10. Write AC Waveforms, Write Enable Controlled

M28W640CT, M28W640CB

AI04388

tWHAX

PROGRAM OR ERASE

tAVAV

VALIDA0-A21

tAVWH

tWHGL

tELQV

tWHEL

tQVWPL

STATUS REGISTER

tQVVPL

READ

1st POLLING

STATUS REGISTER

OR DATA INPUT

tELWL tWHEH

tVPHWH

SET-UP COMMAND CONFIRM COMMAND

tWPHWH

tWHWL

tWHDX

tWLWH

tDVWH

DQ0-DQ15 COMMAND CMD or DATA

25/54

M28W640CT, M28W640CB

Table 16. Write AC Characteristics, Write Enable Controlled

Symbol Alt Parameter

AVAV

AVWH

DVWH

ELWL

ELQV

QVVPL

QVWPL

VPHWH

WHAX

WHDX

WHEH

WHEL

WHGL

WHWL

WLWH

WPHWH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V

(1,2)

(1)

Write Cycle Time Min 80 90 ns

Address Valid to Write Enable High Min 45 50 ns

Data Valid to Write Enable High Min 45 50 ns

Chip Enable Low to Write Enable Low Min 0 0 ns

Chip Enable Low to Output Valid Min 80 90 ns Output Valid to VPPLow

Min 0 0 ns

Output Valid to Write Protect Low Min 0 0 ns

VPSVPP

High to Write Enable High

Min 200 200 ns

Write Enable High to Address Transition Min 0 0 ns Write Enable High to Data Transition Min 0 0 ns Write Enable High to Chip Enable High Min 0 0 ns Write Enable High to Chip Enable Low Min 25 30 ns Write Enable High to Output Enable Low Min 20 30 ns

Write Enable High to Write Enable Low Min 25 30 ns

WPH

Write Enable Low to Write Enable High Min 45 50 ns

Write Protect High to Write Enable High Min 45 50 ns

is seen as a logic input (VPP<3.6V).

M28W640C

Unit

80 90

26/54

Figure 11. Write AC Waveforms, Chip Enable Controlled

M28W640CT, M28W640CB

AI04389

tEHAX

PROGRAM OR ERASE

tAVAV

VALIDA0-A21

tAVEH

tEHGL

tELQV

tQVWPL

CMD or DATA STATUS REGISTER

tQVVPL

READ

1st POLLING

STATUS REGISTER

OR DATA INPUT

CONFIRM COMMAND

tWLEL tEHWH

tVPHEH

POWER-UP AND

SET-UP COMMAND

tWPHEH

tEHEL

tEHDX

tELEH

tDVEH

DQ0-DQ15 COMMAND

27/54

M28W640CT, M28W640CB

Table 17. Write AC Characteristics, Chip Enable Controlled

Symbol Alt Parameter

AVAV

AVEH

DVEH

EHAX

EHDX

EHEL

EHGL

EHWH

ELEH

ELQV

QVVPL

QVWPL

VPHEH

WLEL

WPHEH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V

(1,2)

(1)

Write Cycle Time Min 80 90 ns

Address Valid to Chip Enable High Min 45 50 ns

Data Valid to Chip Enable High Min 45 50 ns

Chip Enable High to Address

Transition

Chip Enable High to Data Transition Min 0 0 ns

Chip Enable High to Chip Enable Low Min 25 30 ns

CPH

Chip Enable High to Output Enable Low

Chip Enable High to Write Enable High Min 0 0 ns

Chip Enable Low to Chip Enable High Min 45 50 ns

Min 0 0 ns

Min 25 30 ns

Chip Enable Low to Output Valid Min 80 90 ns Output Valid to VPPLow

Min 0 0 ns

Data Valid to Write Protect Low Min 0 0 ns

VPSVPP

High to Chip Enable High

Min 200 200 ns

Write Enable Low to Chip Enable Low Min 0 0 ns Write Protect High to Chip Enable High Min 45 50 ns

is seen as a logic input (VPP<3.6V).

M28W640C

Unit

80 90

28/54

Figure 12. Power-Up and Reset AC Waveforms

E, G

tPHWL

tPHEL

tPHGL

M28W640CT, M28W640CB

tPHWL

tPHEL

tPHGL

tVDHPH

VDD, VDDQ

Power-Up Reset

Table 18. Power-Up and Reset AC Characteristics

Symbol Parameter Test Condition

PHWL

PHEL

PHGL

PLPH

VDHPH

Note: 1. The device Reset is possible but not guaranteed if t

Reset High to Write Enable Low, Chip Enable Low, Output Enable Low

(1,2)

Reset Low to Reset High Min 100 100 ns

(3)

Supply Voltages High to Reset High Min 50 50 µs

2. Sampled only, not 100% tested.

3. It is important to assert RP

in o rder to allow proper CPU initialization during power up or reset.

During Program

< 100ns.

PLPH

and Erase

others Min 30 30 ns

tPLPH

AI03537b

M28W640C

Unit

80 90

Min 50 50 µs

29/54

M28W640CT, M28W640CB

PACKAGE MECHANICAL

Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Out line

1 N

N/2

DIE

TSOP-a

Note: Drawing is not to scale.

LA1 α

Table 19. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm , Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 1.20 0.0472 A1 0.05 0.15 0.0020 0.0059 A2 0.95 1.05 0.0374 0.0413

B 0.17 0.27 0.0067 0.0106

C 0.10 0.21 0.0039 0.0083 D 19.80 20.20 0.7795 0.7953

millimeters inches

D1 18.30 18.50 0.7205 0.7283

E 11.90 12.10 0.4685 0.4764

e 0.50 – – 0.0197 – –

L 0.50 0.70 0.0197 0.0279

α 0° 5° 0° 5°

N48 48

CP 0.10 0.0039

30/54

M28W640CT, M28W640CB

Figure 14. TFBGA48 - 8 x 6 ball array, 0. 75 mm pitch, Bottom View Package Outline

E1E

BALL "A1"

Note: Drawing is not to scale.

BGA-Z34

Table 20. TFBGA48 - 8 x 6 b all array, 0.75 mm pitch, Packag e Mechanical Data

Symbol

Typ Min Max Typ Min Max

millimeters inches

ddd

A 1.200 0.0472 A1 0.260 0.0102 A2 1.000 0.0394

b 0.400 0.350 0.450 0.0157 0.0138 0.0177

D 6.390 6.290 6.490 0.2516 0.2476 0.2555

D1 5.250 – – 0.2067 – –

ddd 0.100 0.0039

E 10.500 10.400 10.600 0.4134 0.4094 0.4173 E1 3.750 – – 0.1476 – –

e 0.750 – – 0.0295 – –

FD 0.570 – – 0.0224 – – FE 3.375 – – 0.1329 – – SD 0.375 – – 0.0148 – – SE 0.375 – – 0.0148 – –

31/54

M28W640CT, M28W640CB

Figure 15. TFBGA48 Daisy Chain - Package Connections (Top view through package)

87654321

AI04390

Figure 16. TFBGA48 Daisy Chain - PC B Connections proposal (Top view through package)

87654321

START POINT

END

POINT

32/54

AI04391

M28W640CT, M28W640CB

PART NUMBERING Table 21. Ordering Information Scheme

Example: M28W640CT 90 N 6 T

Device Type

M28

Operating Voltage

W=V

Device Function

640C = 64 Mbit (4 Mb x16), Boot Block

Array Matrix

T=TopBoot B = Bottom Boot

Speed

80 = 80 ns 90 = 90 ns

= 2.7V to 3.6V; V

= 1.65V or 2.7V

DDQ

Package

N = TSOP48: 12 x 20 mm ZB = TFBGA48: 0.75 mm pitch

Temperature Range

1 = 0 to 70 °C 6 = –40 to 85 °C

Option

T = Tape & Reel Packing

Table 22. Daisy Chain Ordering Scheme

Example: M28W640C -ZB T

Device Type

M28W640C

Daisy Chain

-ZB = TFBGA48: 0.75 mm pitch

Option

T = Tape & Reel Packing

Note:Devices are shipped from t he factory with the memory content bits erased to ’1’. For a list of available

options (Speed, Package, etc...) or forfurther information on any aspect of this dev ice, ple as e contact the ST Sales Office nearest to you.

33/54

M28W640CT, M28W640CB

REVISION HISTORY

Table 23. Document Revision History

Date Version Revision Details

20-Apr-2001 -01 First Issue (Brief Data)

18-Jun-2001 -02

02-Jul-2001 -03 Corrections to Table 3. Commands (Lock, Unlock, Lock-Down)

31-Oct-2001 -06

Document expanded to full Product Preview, TFBGA48 Package Mechanical Data changed

Document status changed from Product Preview to Preliminary Data

maximum changed to 3.3V

DDQ

Commands Table, Read CFI Query Address on 1st cycle changed to ‘X’ (Table 3)

description clarified (Table 16)

WHEL

34/54

APPENDIX A. BLOCK ADDRESS TABLES

M28W640CT, M28W640CB

Table 24. Top Boot Block Addresses, M28W640CT

0 4 3FF000-3FFFFF 1 4 3FE000-3FEFFF 2 4 3FD000-3FDFFF 3 4 3FC000-3FCFFF 4 4 3FB000-3FBFFF 5 4 3FA000-3FAFFF 6 4 3F9000-3F9FFF 7 4 3F8000-3F8FFF 8 32 3F0000-3F7FFF

9 32 3E8000-3EFFFF 10 32 3E0000-3E7FFF 11 32 3D8000-3DFFFF 12 32 3D0000-3D7FFF 13 32 3C8000-3CFFFF 14 32 3C0000-3C7FFF 15 32 3B8000-3BFFFF 16 32 3B0000-3B7FFF 17 32 3A8000-3AFFFF 18 32 3A0000-3A7FFF 19 32 398000-39FFFF 20 32 390000-397FFF 21 32 388000-38FFFF 22 32 380000-387FFF 23 32 378000-37FFFF 24 32 370000-377FFF 25 32 368000-36FFFF 26 32 360000-367FFF 27 32 358000-35FFFF 28 32 350000-357FFF 29 32 348000-34FFFF 30 32 340000-347FFF 31 32 338000-33FFFF 32 32 330000-337FFF 33 32 328000-32FFFF 34 32 320000-327FFF 35 32 318000-31FFFF 36 32 310000-317FFF 37 32 308000-30FFFF 38 32 300000-307FFF 39 32 2F8000-2FFFFF

Size

(KWord)

Address Range

40 32 2F0000-2F7FFF 41 32 2E8000-2EFFFF 42 32 2E0000-2E7FFF 43 32 2D8000-2DFFFF 44 32 2D0000-2D7FFF 45 32 2C8000-2CFFFF 46 32 2C0000-2C7FFF 47 32 2B8000-2BFFFF 48 32 2B0000-2B7FFF 49 32 2A8000-2AFFFF 50 32 2A0000-2A7FFF 51 32 298000-29FFFF 52 32 290000-297FFF 53 32 288000-28FFFF 54 32 280000-287FFF 55 32 278000-27FFFF 56 32 270000-277FFF 57 32 268000-26FFFF 58 32 260000-267FFF 59 32 258000-25FFFF 60 32 250000-257FFF 61 32 248000-24FFFF 62 32 240000-247FFF 63 32 238000-23FFFF 64 32 230000-237FFF 65 32 228000-22FFFF 66 32 220000-227FFF 67 32 218000-21FFFF 68 32 210000-217FFF 69 32 208000-20FFFF 70 32 200000-207FFF 71 32 1F8000-1FFFFF 72 32 1F0000-1F7FFF 73 32 1E8000-1EFFFF 74 32 1E0000-1E7FFF 75 32 1D8000-1DFFFF 76 32 1D0000-1D7FFF 77 32 1C8000-1CFFFF 78 32 1C0000-1C7FFF 79 32 1B8000-1BFFFF 80 32 1B0000-1B7FFF 81 32 1A8000-1AFFFF 82 32 1A0000-1A7FFF 83 32 198000-19FFFF

35/54

M28W640CT, M28W640CB

84 32 190000-197FFF 85 32 188000-18FFFF 86 32 180000-187FFF 87 32 178000-17FFFF 88 32 170000-177FFF 89 32 168000-16FFFF 90 32 160000-167FFF 91 32 158000-15FFFF 92 32 150000-157FFF 93 32 148000-14FFFF 94 32 140000-147FFF 95 32 138000-13FFFF 96 32 130000-137FFF 97 32 128000-12FFFF 98 32 120000-127FFF 99 32 118000-11FFFF

100 32 110000-117FFF 101 32 108000-10FFFF 102 32 100000-107FFF 103 32 0F8000-0FFFFF 104 32 0F0000-0F7FFF 105 32 0E8000-0EFFFF 106 32 0E0000-0E7FFF 107 32 0D8000-0DFFFF 108 32 0D0000-0D7FFF 109 32 0C8000-0CFFFF 110 32 0C0000-0C7FFF 111 32 0B8000-0BFFFF 112 32 0B0000-0B7FFF 113 32 0A8000-0AFFFF 114 32 0A0000-0A7FFF 115 32 098000-09FFFF 116 32 090000-097FFF 117 32 088000-08FFFF 118 32 080000-087FFF 119 32 078000-07FFFF 120 32 070000-077FFF 121 32 068000-06FFFF 122 32 060000-067FFF 123 32 058000-05FFFF 124 32 050000-057FFF 125 32 048000-04FFFF 126 32 040000-047FFF 127 32 038000-03FFFF 128 32 030000-037FFF 129 32 028000-02FFFF

130 32 020000-027FFF 131 32 018000-01FFFF 132 32 010000-017FFF 133 32 008000-00FFFF 134 32 000000-007FFF

36/54

M28W640CT, M28W640CB

Table 25. Bottom Boot Block Addres ses, M28W640CB

134 32 3F8000-3FFFFF 133 32 3F0000-3F7FFF 132 32 3E8000-3EFFFF 131 32 3E0000-3E7FFF 130 32 3D8000-3DFFFF 129 32 3D0000-3D7FFF 128 32 3C8000-3CFFFF 127 32 3C0000-3C7FFF 126 32 3B8000-3BFFFF 125 32 3B0000-3B7FFF 124 32 3A8000-3AFFFF 123 32 3A0000-3A7FFF 122 32 398000-39FFFF 121 32 390000-397FFF 120 32 388000-38FFFF 119 32 380000-387FFF 118 32 378000-37FFFF 117 32 370000-377FFF 116 32 368000-36FFFF 115 32 360000-367FFF 114 32 358000-35FFFF 113 32 350000-357FFF 112 32 348000-34FFFF 111 32 340000-347FFF 110 32 338000-33FFFF 109 32 330000-337FFF 108 32 328000-32FFFF 107 32 320000-327FFF 106 32 318000-31FFFF 105 32 310000-317FFF 104 32 308000-30FFFF 103 32 300000-307FFF 102 32 2F8000-2FFFFF 101 32 2F0000-2F7FFF 100 32 2E8000-2EFFFF

99 32 2E0000-2E7FFF 98 32 2D8000-2DFFFF 97 32 2D0000-2D7FFF 96 32 2C8000-2CFFFF 95 32 2C0000-2C7FFF 94 32 2B8000-2BFFFF 93 32 2B0000-2B7FFF

Size

(KWord)

Address Range

92 32 2A8000-2AFFFF 91 32 2A0000-2A7FFF 90 32 298000-29FFFF 89 32 290000-297FFF 88 32 288000-28FFFF 87 32 280000-287FFF 86 32 278000-27FFFF 85 32 270000-277FFF 84 32 268000-26FFFF 83 32 260000-267FFF 82 32 258000-25FFFF 81 32 250000-257FFF 80 32 248000-24FFFF 79 32 240000-247FFF 78 32 238000-23FFFF 77 32 230000-237FFF 76 32 228000-22FFFF 75 32 220000-227FFF 74 32 218000-21FFFF 73 32 210000-217FFF 72 32 208000-20FFFF 71 32 200000-207FFF 70 32 1F8000-1FFFFF 69 32 1F0000-1F7FFF 68 32 1E8000-1EFFFF 67 32 1E0000-1E7FFF 66 32 1D8000-1DFFFF 65 32 1D0000-1D7FFF 64 32 1C8000-1CFFFF 63 32 1C0000-1C7FFF 62 32 1B8000-1BFFFF 61 32 1B0000-1B7FFF 60 32 1A8000-1AFFFF 59 32 1A0000-1A7FFF 58 32 198000-19FFFF 57 32 190000-197FFF 56 32 188000-18FFFF 55 32 180000-187FFF 54 32 178000-17FFFF 53 32 170000-177FFF 52 32 168000-16FFFF 51 32 160000-167FFF 50 32 158000-15FFFF 49 32 150000-157FFF 48 32 148000-14FFFF 47 32 140000-147FFF

37/54

M28W640CT, M28W640CB

46 32 138000-13FFFF 45 32 130000-137FFF 44 32 128000-12FFFF 43 32 120000-127FFF 42 32 118000-11FFFF 41 32 110000-117FFF 40 32 108000-10FFFF 39 32 100000-107FFF 38 32 0F8000-0FFFFF 37 32 0F0000-0F7FFF 36 32 0E8000-0EFFFF 35 32 0E0000-0E7FFF 34 32 0D8000-0DFFFF 33 32 0D0000-0D7FFF 32 32 0C8000-0CFFFF 31 32 0C0000-0C7FFF 30 32 0B8000-0BFFFF 29 32 0B0000-0B7FFF 28 32 0A8000-0AFFFF 27 32 0A0000-0A7FFF 26 32 098000-09FFFF 25 32 090000-097FFF 24 32 088000-08FFFF 23 32 080000-087FFF 22 32 078000-07FFFF 21 32 070000-077FFF 20 32 068000-06FFFF 19 32 060000-067FFF 18 32 058000-05FFFF 17 32 050000-057FFF 16 32 048000-04FFFF 15 32 040000-047FFF 14 32 038000-03FFFF 13 32 030000-037FFF 12 32 028000-02FFFF 11 32 020000-027FFF 10 32 018000-01FFFF

9 32 010000-017FFF

8 32 008000-00FFFF

7 4 007000-007FFF

6 4 006000-006FFF

5 4 005000-005FFF

4 4 004000-004FFF

3 4 003000-003FFF

2 4 002000-002FFF

1 4 001000-001FFF

0 4 000000-000FFF

38/54

M28W640CT, M28W640CB

APPENDIX B. COMMO N FLASH INTERFACE (CFI)

TheCommonFlashInterfaceisaJEDECapproved, standardized data structure that can be read from the Flash memory device. It allows a system s oftware t o query the device to determi ne various electrical and timi ng parameters, density information and function s supported by t he memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary.

When the CFI Query Command (RCFI) is issued the device ent ers CFI Query mode and the data

Table 26. Query Structure Overview

Offset Sub-section Name Description

00h Reserved Reserved for algorithm-specific information 10h CFI Query Identification String Command set ID and algorithm data offset

1Bh System Interface Information Device timing & voltage information

27h Device Geometry Definition Flash device layout

P Primary Algorithm-specific Extended Query table

A Alternate Algorithm-specific Extended Query table

Note: Querydata are always presented on the lowest order data outputs.

structure is read from the memory . Tables 26, 27, 28, 29, 30 and 31 show the addresses used to retrieve the data.

The CFI data structu re also contains a security area where a 64 bit unique security number is written (see Table 31, Security Code area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Issue a Read command t o return to Read mode.

Additional information specific to the Primary Algorithm (optional)

Additional information specific to the Alternate Algorithm (optional)

Table 27. CFI Query Identification String

Offset Data Description Value

00h 0020h Manufacturer Code ST

01h

02h-0Fh reserved Reserved

10h 0051h "Q"

11h 0052h Query Unique ASCII String "QRY" "R" 12h 0059h "Y" 13h 0003h 14h 0000h 15h 0035h 16h 0000h 17h 0000h 18h 0000h 19h 0000h

1Ah 0000h

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

8848h 8849h

Device Code

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm

Address for Primary Algorithm extended Query table (see Table 29) P = 35h

Alternate Vendor Command Set and Control Interface ID Code second vendor specified algorithm supported (0000h means none exists)

Address for Alternate Algorithm extended Query table (0000h means none exists)

compatible

Top

Bottom

Intel

39/54

M28W640CT, M28W640CB

Table 28. CFI Query System Interface Information

Offset Data Description Value

Logic Supply Minimum Program/Erase or Write voltage

1Bh 0027h

1Ch 0036h

1Dh 00B4h

1Eh 00C6h

1Fh 0004h 20h 0004h 21h 000Ah 22h 0000h 23h 0005h 24h 0005h 25h 0003h 26h 0000h

bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV

Logic Supply Maximum Program/Erase or Write voltage

bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV

Typical time-out per single word program = 2 Typical time-out for Double Word Program = 2 Typical time-out per individual block erase = 2 Typical time-out for full chip erase = 2

Maximum time-out for word program = 2

µs

times typical

µs

Maximum time-out for Double/Quadruple Word Program = 2 Maximum time-out per individual block erase = 2

Maximum time-out for chip erase = 2

times typical

2.7V

3.6V

11.4V

12.6V

16µs 16µs

NA 512µs 512µs

40/54

Table 29. Device Geometry Definition

Offset Word

Mode

27h 0032h 28h

29h

2Ah 2Bh

2Ch 0002h

2Dh 2Eh

2Fh 30h

31h 32h

M28W640CT

33h 34h

2Dh 2Eh

2Fh 30h

31h 32h

M28W640CB

33h 34h

Data Description Value

Device Size = 2

0001h 0000h

0002h 0000h

007Eh 0000h

0000h 0001h

0007h 0000h

0020h 0000h

0007h 0000h

0020h 0000h

007Eh 0000h

0000h 0001h

Flash Device Interface Code description

Maximum number of bytes in multi-byte program or page = 2 Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing contiguous Erase Blocks of the same size.

Region 1 Information Number of identical-size erase block = 007Eh+1

Region 1 Information Block size in Region 1 = 0100h * 256 byte

Region 2 Information Number of identical-size erase block = 0007h+1

Region 2 Information Block size in Region 2 = 0020h * 256 byte

Region 1 Information Number of identical-size erase block = 0007h+1

Region 1 Information Block size in Region 1 = 0020h * 256 byte

Region 2 Information Number of identical-size erase block = 007Eh=1

Region 2 Information Block size in Region 2 = 0100h * 256 byte

in number of bytes

M28W640CT, M28W640CB

8 MByte

x16

Async.

127

64 KByte

8 KByte

127

64 KByte

41/54

M28W640CT, M28W640CB

Table 30. Primary Algorithm -Sp ecific Extended Query Table

Offset

P = 35h

(1)

(P+0)h = 35h 0050h (P+1)h = 36h 0052h "R" (P+2)h = 37h 0049h "I" (P+3)h = 38h 0031h Major version number, ASCII "1" (P+4)h = 39h 0030h Minor version number, ASCII "0"

Data Description Value

Primary Algorithm extended Query table unique ASCII string “PRI”

"P"

(P+5)h = 3Ah 0066h Extended Query table contents for Primary Algorithm. Address (P+5)h (P+6)h = 3Bh 0000h (P+7)h = 3Ch 0000h (P+8)h = 3Dh 0000h

contains less significant byte.

bit 0 Chip Erase supported (1 = Yes, 0 = No) bit 1 Suspend Erase supported (1 = Yes, 0 = No) bit 2 Suspend Program supported (1 = Yes, 0 = No) bit 3 Legacy Lock/Unlock supported (1 = Yes, 0 = No) bit 4 Queued Erase supported (1 = Yes, 0 = No) bit 5 Instant individual block locking supported (1 = Yes, 0 = No) bit 6 Protection bits supported (1 = Yes, 0 = No) bit 7 Page mode read supported (1 = Yes, 0 = No) bit 8 Synchronous read supported (1 = Yes, 0 = No) bit 31 to 9 Reserved; undefined bits are ‘0’

No Yes Yes

(P+9)h = 3Eh 0001h Supported Functions after Suspend

Read Array, Read Status Register and CFI Query are always supported during Erase or Program operation

bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No)

bit 7 to 1 Reserved; undefined bits are ‘0’ Yes (P+A)h = 3Fh 0003h Block Lock Status (P+B)h = 40h 0000h

Defines which bits in the Block Status Register section of the Query are implemented. Address (P+A)h contains less significant byte

bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No)

bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

Yes Yes

bit 15 to 2 Reserved for future use; undefined bits are ‘0’ (P+C)h = 41h 0030h V

Logic Supply Optimum Program/Erase voltage (highest performance)

3V bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV

(P+D)h = 42h 00C0h V

Supply Optimum Program/Erase voltage

12V bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV

(P+E)h = 43h 0001h Number of Protection register fields in JEDEC ID space.

"00h," indicates that 256 protection bytes are available

(P+F)h = 44h 0080h Protection Field 1: Protection Description

(P+10)h = 45h 0000h 00h

(P+11)h = 46h 0003h 8 Byte

(P+12)h = 47h 0004h 16 Byte

This field describes user-available One Time Programmable (OTP) Protection register bytes. Some are pre-programmed with device unique serial numbers. Others are user programmable. Bits 0–15 point to the Protection register Lock byte, the section’s first byte. The following bytes are factory pre-programmed and user-programmable.

80h

bit 0 to 7 Lock/bytes JEDEC-plane physical low address bit 8 to 15 Lock/bytes JEDEC-plane physical high address

bit 16 to 23 "n" such that 2 bit 24 to 31 "n" such that 2

= factory pre-programmed bytes

= user programmable bytes

(P+13)h = 48h Reserved

Note: 1. See Table 27, offset 15 for P pointer definition.

42/54

Table 31. Security Code Area

Offset Data Description

80h 00XX Protection Register Lock 81h XXXX 82h XXXX 83h XXXX 84h XXXX 85h XXXX 86h XXXX 87h XXXX 88h XXXX

89h XXXX 8Ah XXXX 8Bh XXXX 8Ch XXXX

64 bits: unique device number

128 bits: User Programmable OTP

M28W640CT, M28W640CB

43/54

M28W640CT, M28W640CB

APPENDIX C. FLO WCHART S AND PSEUDO CO DE S

Figure 17. Program Flowchart and Pseudo Code

Start

Write 40h or 10h

Write Address

& Data

Read Status

b7 = 1

YES

b3 = 0

YES

b4 = 0

YES

b1 = 0

YES

End

VPP Invalid Error (1, 2)

Error (1, 2)

Program to Protected

Block Error (1, 2)

Program

program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0x40) ; /*or writeToFlash (any_address, 0x10) ; */

writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;

if (status_register.b4==1) /*program error */ error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;

}

AI03538b

Note: 1. Status check of b1 (Protected Block), b3 (VPPInvalid) and b4 (Program Error) can be made after each program operation or after

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

44/54

Figure 18. Double Word Program Flowchart and Pseudo Code

Start

M28W640CT, M28W640CB

Write 30h

Write Address 1

& Data 1 (3)

Write Address 2

& Data 2 (3)

Read Status

b7 = 1

YES

b3 = 0

YES

b4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

double_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2) { writeToFlash (any_address, 0x30) ;

writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ /*Memory enters read status state after the Program command*/

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;

if (status_register.b4==1) /*program error */ error_handler ( ) ;

YES

b1 = 0

YES

End

Note: 1. Status check of b1 (Protected Block), b3 (VPPInvalid) and b4 (Program Error) can be made after each program operation or after

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;

}

AI03539b

45/54

M28W640CT, M28W640CB

Figure 19. Quadruple Word Program Flowchart and Pseudo Code

Start

Write 55h

Write Address 1

& Data 1 (3)

Write Address 2

& Data 2 (3)

Write Address 3

& Data 3 (3)

Write Address 4

& Data 4 (3)

Read Status

b7 = 1

YES

quadruple_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2, addressToProgram3, dataToProgram3, addressToProgram4, dataToProgram4) { writeToFlash (any_address, 0x55) ;

writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */

writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */

writeToFlash (addressToProgram3, dataToProgram3) ; /*see note (3) */

writeToFlash (addressToProgram4, dataToProgram4) ; /*see note (3) */

/*Memory enters read status state after the Program command*/

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

b3 = 0

b4 = 0

b1 = 0

End

Note: 1. Status check of b1 (Protected Block), b3 (VPPInvalid) and b4 (Program Error) can be made after each program operation or after

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.

YES

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;

if (status_register.b4==1) /*program error */ error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;

}

AI04398

46/54

Figure 20. Program Suspend & Resume Flowchart and Pseudo Code

Start

program_suspend_command ( ) {

Write B0h

Write 70h

Read Status

writeToFlash (any_address, 0xB0) ; writeToFlash (any_address, 0x70) ;

/* read status register to check if program has already completed */

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

M28W640CT, M28W640CB

b7 = 1

YES

b2 = 1

YES

Write FFh

Read data from

another address

Write D0h

Program Continues

Program Complete

Write FFh

Read Data

} while (status_register.b7== 0) ;

if (status_register.b2==0) /*program completed */ { writeToFlash (any_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/

} else { writeToFlash (any_address, 0xFF) ; read_data ( ); /*read data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ } }

AI03540b

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M28W640CT, M28W640CB

Figure 21. Erase Flowchart and Pseudo Code

Start

Write 20h

Write Block

Address & D0h

erase_command ( blockToErase ) { writeToFlash (any_address, 0x20) ;

writeToFlash (blockToErase, 0xD0) ; /* only A12-A20 are significannt */ /* Memory enters read status state after

the Erase Command */

Read Status

YES

VPP Invalid

Error (1)

Command

Sequence Error (1)

Erase to Protected

Block Error (1)

b7 = 1

b3 = 0

b4, b5 = 1

b5 = 0 Erase Error (1)

b1 = 0

End

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;

if ( (status_register.b4==1) && (status_register.b5==1) ) /* command sequence error */ error_handler ( ) ;

if ( (status_register.b5==1) ) /* erase error */ error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;

}

AI03541b

Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.

48/54

Figure 22. Erase Suspend & Resume Flowchart and Pseudo Code

Start

M28W640CT, M28W640CB

Write B0h

Write 70h

Read Status

b7 = 1

b6 = 1

Write FFh

Read data from

another block

Program/Protection Program

Block Protect/Unprotect/Lock

or or

Write D0h

Erase Continues

YES

Erase Complete

Write FFh

Read Data

erase_suspend_command ( ) { writeToFlash (any_address, 0xB0) ;

writeToFlash (any_address, 0x70) ; /* read status register to check if erase has already completed */

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b6==0) /*erase completed */ { writeToFlash (any_address, 0xFF) ;

read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/

} else { writeToFlash (any_address, 0xFF) ; read_program_data ( ); /*read or program data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume erase*/ } }

AI03542b

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M28W640CT, M28W640CB

Figure 23. Locking Operations Flowchart and Pseudo Code

Start

Write 60h

Write

01h, D0h or 2Fh

Write 90h

Read Block Lock States

Locking change

confirmed?

YES

Write FFh

End

locking_operation_command (address, lock_operation) { writeToFlash (any_address, 0x60) ; /*configuration setup*/

if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ;

writeToFlash (any_address, 0x90) ;

if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/

writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/ }

AI04364

50/54

Figure 24. Protection Register Program Flowchart and Pseudo Code

Start

M28W640CT, M28W640CB

Write C0h

Write Address

& Data

Read Status

b7 = 1

YES

b3 = 0

YES

b4 = 0

YES

b1 = 0

YES

End

VPP Invalid

Error (1, 2)

Program to Protected

Block Error (1, 2)

Program

protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0xC0) ;

writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/

do { status_register=readFlash (any_address) ; /* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ;

if (status_register.b4==1) /*program error */ error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ;

}

AI04381

Note: 1. Status check of b1 (Protected Block), b3 (VPPInvalid) and b4 (Program Error) can be made after each program operation or after

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

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M28W640CT, M28W640CB

APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE

Table 32. Write State Machine Current/Next, sheet 1 of 2.

Current

StateSRbit 7

Read Array “1” Array Read Array Prog.Setup Ers. Setup Read Array Read Sts. Read Array

Read

Status

Read

Elect.Sg.

Read CFI

Query

Lock Setup “1” Status Lock Command Error

Lock Cmd

Error

Lock

(complete) Prot. Prog.

Setup

Prot. Prog.

(continue)

Prot. Prog. (complete)

Prog.Setup “1” Status Program

Program

(continue) Prog.Sus

Status

Prog.Sus

Read Array

Prog.Sus

Read

Elect.Sg.

Prog.Sus

Read CFI

Program

(complete)

Erase Setup

Erase

Cmd.Error

Erase

(continue) Erase Sus

Read Sts

Erase Sus

Read Array

Erase Sus

Read

Elect.Sg.

Erase Sus

Read CFI

Erase

(complete)

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.

Data

When

Read

“1” Status Read Array

Electronic

“1”

Signature

“1” CFI Read Array

“1” Status Read Array

“1” Status Protection Register Program

“0” Status Protection Register Program continue

“1” Status Read Array

“0” Status Program (continue)

“1” Status

“1” Array

Electronic

“1”

Signature

“1” CFI

“1” Status Read Array

“1” Status Erase Command Error

“1” Status Read Array

“0” Status Erase (continue)

“1” Status

“1” Array

Electronic

“1”

Signature

“1” CFI

“1” Status Read Array

Read Array (FFh)

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Program

Setup

(10/40h)

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program Suspend to

Read Array

Program Suspend to

Read Array

Program Suspend to

Read Array

Program Suspend to

Read Array

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Command Input (and Next State)

Erase Setup

(10/40h)

Erase Setup

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Setup

Erase

Confirm

(D0h)

Lock

(complete)

Program

(continue)

Program

(continue)

Program

(continue)

Program

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Prog/Ers Suspend

(B0h)

Read Array

Lock Cmd

Error

Read Array

Prog. Sus

Read Sts

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array Read Array

Erase

CmdError

Read Array

Erase Sus

Read Sts

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array Read Array

Prog/Ers

Resume

(D0h)

Lock

(complete)

Program

(continue)

Program

(continue)

Program

(continue)

Program

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Read

Status

(70h)

Read

Status

Read

Status

Read

Status

LockCommand Error

Read

Status

Read

Status

Read

Status

Program (continue)

Prog. Sus

Read Sts

Prog. Sus

Read Sts

Prog. Sus

Read Sts

Prog. Sus

Read Sts

Read

Status

Erase Command Error

Read

Status

Erase (continue)

Erase Sus

Read Sts

Erase Sus

Read Sts

Erase Sus

Read Sts

Erase Sus

Read Sts

Read

Status

Read Array Read Array

Clear

Status

(50h)

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array

Prog. Sus

Read Array Read Array

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Erase Sus

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M28W640CT, M28W640CB

Table 33. Write State Machine Current/Next, sheet 2 of 2.

Command Input (and Next State)

Current State

Read Array ReadElect.Sg. Read CFI Query Lock Setup

Read Status Read Elect.Sg. Read CFI Query Lock Setup

Read Elect.Sg. Read Elect.Sg. Read CFI Query Lock Setup

Read CFI Query Read Elect.Sg. Read CFI Query Lock Setup

Lock Setup Lock Command Error Lock (complete)

Lock Cmd Error Read Elect.Sg. Read CFI Query Lock Setup

Lock (complete) Read Elect.Sg. Read CFI Query Lock Setup

Prot. Prog.

Setup

Prot. Prog.

(continue)

Prot. Prog. (complete)

Prog. Setup Program

Program

(continue)

Prog.Suspend

Read Status

Prog.Suspend

Read Array

Prog.Suspend

ReadElect.Sg.

Prog.Suspend

Read CFI

Program

(complete)

EraseSetup Erase Command Error

Erase

Cmd.Error

Erase (continue) Erase (continue)

Erase Suspend

Read Ststus

Erase Suspend

Read Array

Erase Suspend ReadElect.Sg.

Erase Suspend

Read CFI Query

Erase

(complete)

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.

Read Elect.Sg.

(90h)

Read Elect.Sg. Read CFI Query Lock Setup

Prog. Suspend Read Elect.Sg.

Read Elect.Sg. Read CFIQuery Lock Setup

Read Elect.Sg. Read CFI Query Lock Setup

Erase Suspend

Read Elect.Sg.

Erase Suspend

Read Elect.Sg.

Erase Suspend

Read Elect.Sg.

Erase Suspend

Read Elect.Sg. Read Elect.Sg. Read CFI Query Lock Setup

Read CFI

Query

(98h)

Prog. Suspend

Read CFI Query

Prog. Suspend

Read CFI Query

Prog. Suspend

Read CFI Query

Prog. Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Erase Suspend

Read CFI Query

Lock Setup

(60h)

Protection Register Program

Protection Register Program (continue)

LockSetup Erase Suspend Read Array

Prot. Prog.

Setup (C0h)

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Program (continue)

Program Suspend Read Array

Prot. Prog.

Setup

Prot. Prog.

Setup

Prot. Prog.

Setup

Lock Confirm

(01h)

Confirm (2Fh)

Lock Down

Read Array

Unlock

Confirm

(D0h)

Program

(continue)

Program

(continue)

Program

(continue)

Program

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

Erase

(continue)

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M28W640CT, M28W640CB

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

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SGS Thomson Microelectronics M28W640CT, M28W640CB Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual