SGS Thomson Microelectronics M27W801 Datasheet

M27W801

8 Mbit (1Mb x8) Low Voltage UV EPROM and OTP EPROM

■ 2.7V to 3.6V SUPPLY VOLTAGE in READ

OPERATION

■ ACCESS TIME:

–80nsatVCC= 3.0V to 3.6V – 100ns at VCC= 2.7V to 3.6V

■ PIN COMPATIBLE with M27C801

■ LOW POWER CONSUMPTION:

–15µA max Standby Current – 15mA max Active Current at 5MHz

■ PROGRAMMING TIME 50µs/byte

■ HIGH RELIABILITY CMOS TECHNOLOGY

– 2,000V ESD Protection – 200mA Latchup Protection Immunity

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Device Code: 42h

FDIP32W (F)

PLCC32 (K)

Figure 1. Logic Diagram

PDIP32 (B)

TSOP32 (N)

8 x 20 mm

DESCRIPTION

The M27W801 is a low voltage 8 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large data or program storage and is organized as1,048,576by 8 bits.

The M27W801 operates in the read mode with a supply voltage as low as 2.7V at –40 to 85°C temperature range. The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery recharges.

The FDIP32W (window ceramic frit-seal package) has a transparent lids which allow the user to expose the chip to ultraviolet light to erase thebitpattern. A new pattern can then be written to the device by following the programming procedure.

For applications wherethe content is programmed only one time and erasure is not required, the M27W801 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages.

A0-A19 Q0-Q7

M27W801

AI02363

1/16April 2000

M27W801

Figure 2A. DIP Connections

A19 V

1 2

A15

A12

8 A3 A2 A1 A0

Q2 SS

M27W801

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

AI02671

A18A16 A17 A14 A13 A8 A9 A11 GV A10 E Q7 Q6 Q5Q1 Q4 Q3V

Figure 2B. PLCC Connections

A16

A7 A6 A5 A4 A3 A2 A1 A0

A12

A19

A15

M27W801

A18

A17

A14 A13 A8 A9 A11 GV A10 E Q7

AI02365

Figure 2C. TSOP Connections

A11 GV

A8 A13 A14 A17 A18

A19 A16 A15 A12

A4 A3

M27W801

(Normal)

16 17

25 24

AI02366

A10 E Q7 Q6 Q5 Q4 Q3 V

Q2 Q1 Q0 A0 A1 A2

Table 1. Signal Names

A0-A19 Address Inputs

Q0-Q7 Data Outputs

E Chip Enable

Output Enable / Program Supply

Supply Voltage

Ground

2/16

M27W801

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

BIAS

STG

(2)

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of thedevice at theseor anyother conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extendedperiods may affect device reliability. Refer alsoto the STMicroelectronics SUREProgram andotherrelevant quality documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is V

3. Depends on range.

Ambient Operating Temperature Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage (except A9) –2 to 7 V Supply Voltage –2 to 7 V A9 Voltage –2 to 13.5 V Program Supply Voltage –2 to 14 V

+0.5V with possible overshoot to VCC+2V for a period less than 20ns.

(3)

–40 to 125 °C

Table 3. Operating Modes

Mode E

Read Output Disable V Program

V Program Inhibit V Standby Electronic Signature

Note: X = VIHor VIL,VID= 12V ± 0.5V.

Pulse V

A9 Q7-Q0

X Data Out X Hi-Z X Data In X Hi-Z

X X Hi-Z

Codes

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code Device Code

00100000 20h 01000010 42h

3/16

M27W801

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns (10% to 90%) Input Pulse Voltages 0 to 3V 0.4V to 2.4V Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform

High Speed

1.5V

Standard

2.4V

0.4V

Table 6. Capacitance

Symbol Parameter Test Condition Min Max Unit

OUT

Note: 1. Sampled only, not 100% tested.

(1)

(TA=25°C, f = 1 MHz)

Input Capacitance Output Capacitance

2.0V

0.8V

AI01822

Figure 4. AC Testing Load Circuit

1.3V

DEVICE

UNDER

TEST

CL= 30pFfor HighSpeed CL= 100pF for Standard CLincludes JIG capacitance

=0V

OUT

1N914

3.3kΩ

6pF

12 pF

OUT

AI01823B

DEVICE OPERATION

The operating modes of the M27W801 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for GVPPand 12V on A9 for Electronic Signature and Margin Mode Set or Reset.

Read Mode

The M27W801 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable(G)is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time

4/16

) is equal to the delay from E to output

AVQV

). Data is available attheoutputafteradelay

ELQV

of t

from the falling edge of G, assuming that

GLQV

E has been low and the addresses have been stable for at least t

AVQV-tGLQV

Standby Mode

The M27W801 has a standby mode which reduces the supply current from 15mA to 20µA with low voltage operation VCC≤ 3.6V, see ReadMode DC Characteristics table for details. The M27W801 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the GVPPinput.

M27W801

Table 7. Read Mode DC Characteristics

(1)

(TA= –40 to 85 °C; VCC= 2.7V to 3.6V; VPP=VCC)

Symbol Parameter Test Condition Min Max Unit

CC1

CC2

I V

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

Two Line Output Control

Because EPROMs are usually used in larger memory arrays, the product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:

a. the lowest possible memory power dissipation, b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control lines, Eshould be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system controlbus. This ensures that all deselected memory devices are intheir low power standby mode and that the output pins are only active when data is required from a particular memory device.

Input Leakage Current

Output Leakage Current

Supply Current

Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current

Input Low Voltage –0.6

(2)

Input High Voltage Output Low Voltage

Output High VoltageTTL

2. Maximum DC voltage on Output is V

+0.5V.

E=V

0V ≤ V

,GVPP=VIL,I

f = 5MHz, V

E>V

≤ V

OUT

E=V

–0.2V,VCC≤ 3.6V

PP=VCC

= 2.1mA

= –1mA

OUT

≤ 3.6V

System Considerations

The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associatedtransient voltagepeaks can be suppressed by complying with the two line outputcontrol and byproperly selected decoupling capacitors.It is recommended that a 0.1µFceramic capacitor be used on every device between V and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between VCCand VSSfor every eight devic-

= 0mA,

±10 µA ±10 µA

15 mA

1mA 15 µA 10 µA

0.2 V

0.7 V

CCVCC

3.6 V

+ 0.5

0.4 V

es. The bulk capacitor should be located near the power supply connection point. The purposeof the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.

V V

5/16

+ 11 hidden pages