SGS Thomson Microelectronics M27W800 Datasheet

Low Voltage UV EPROM and OTP EPROM

■ 2.7V to 3.6V LOW VOLTAGE in READ

OPERATION

■ ACCESS TIME:

–90ns at V – 100ns at V

■ BYTE-WIDE or WORD-WIDE

CONFIGURABLE

■ 8 Mbit MASK ROM REPLACEMENT

■ LOW POWER CONSUMPTION

– Active Current 30mA at 8MHz – Standby Current 15µA

■ PROGRAMMI N G VOLT AG E: 1 2.5V ± 0.25V

■ PROGRAMMING TIME: 50µs/word

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Device Code: B2h

DESCRIPTION

The M27W800 is a low voltage 8 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmab le). It is ideally suited for microprocessor systems requiring large data or program storage. It is orga nised as either 1 M bit words of 8 bit or 512 Kbit words of 16 bit. The pinout is compatible with a 8 Mbit Mask ROM.

The M27W800 operates in the read mode with a supply voltage as low as 2.7V. The decrease in operating power allows either a red uction of the size of the battery or an increase i n the time between battery recharges.

The FDIP42W (window ceramic frit-seal package) has a transparent lid which all ows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written rapidly to the device by following the programming procedure.

For applications where the content is programmed only one time and erasure is not required, the M27W800 is offered in PDIP42 and PLCC44 package.

= 3.0V to 3.6V

= 2.7V to 3.6V

M27W800

8 Mbit (1Mb x 8 or 512Kb x 16)

FDIP42W (F) PDIP42 (B)

Figure 1. Logic Diagram

A0-A18

BYTEV

PLCC44 (K)

M27W800

Q15A–1

Q0-Q14

AI03601

1/15March 2000

M27W800

Figure 2A. DIP Connections

A18 NC

1 2

3 4

A5 A4

6 7

A3 A2

8 9

Q0 Q8 Q1 Q9

Q10

Q11

M27W800

11 12 13 14 15 16 17 18 19 20 21

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

AI03602

A8A17 A9 A10 A11 A12 A13 A14 A15 A16 BYTEV V

Q15A-1 Q7 Q14 Q6 Q13 Q5Q2 Q12 Q4 V

Figure 2B. LCC Connections

A4 A3 A2 A1 A15 A0

Q0 Q8 Q1

Q10

A18

A17

M27W800

Q11

Q12

A10

A11

Q13

A12 A13 A14

A16 BYTEV V

Q15A–1G Q7 Q14 Q6

AI03603

Table 1. Signal Names

A0-A18 Address Inputs Q0-Q7 Data Outputs Q8-Q14 Data Outputs

Q15A–1 Data Output / Address Input E G

BYTE

NC Not Connected Internally

Chip Enable Output Enable Byte Mode / Program Supply Supply Voltage Ground

DEVICE OPERATION

The operating modes of the M27W800 are listed in the Operating Modes Table. A single power supply is required in the read mode. All inputs are TTL compatib le exce pt for V

and 12V on A9 for the

Electronic Signature.

Read Mode

The M27W800 has two organ isations, Word-w ide and Byte-wide. The organisation is selected by the signal level on the BYTE

VPP pin. When BYTEV

is at VIH the Word-wide organisation is selected

and the Q15A–1 pin is used for Q15 Data Output. When the BYTE

VPP pin is at VIL the Byte-wide organisation is selected and the Q15A–1 pin is used for the Address Input A–1. When the memory is logically regarded as 16 bit wid e, but read in the Byte-wide organisation, then with A–1 at V

the lower 8 bits of the 16 bit data are selected and with A–1 at V

the upper 8 bits of the 16 bit dat a are

sele cte d. The M27W800 has two cont rol functions, both of

which must be logically ac tive in order to obtain data at the outputs. In addition the Word-wide or Byte-wide organisation must be selected.

Chip Enable (E used for device selection. Output Enable (G

) is the power control and should be

) is the output control and should be used to gate data to the output pins i ndependent of device selection. Assuming that the addresses are s table, the address access time (t from E

to output (t

ELQV

output after a delay of t of G

, assuming that E has been low and the ad-

dresses have been stable for at least t

) is equal to the delay

AVQV

). Data is available at the

from the falling e dge

GLQV

AVQV-tGLQV

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M27W800

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

BIAS

STG

(2)

Note: 1. Except for the ratin g " Operati ng Temperat ure Range" , stresses above th ose liste d i n t he Table " A bsolute M aximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indi cated in the Operating sections of this s pecification is not impli ed. Exposure to A bsolute M aximum Rating conditions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ity docum en ts .

2. Min imum DC volta ge on In put or O utput is –0.5V with po ssible under shoot t o –2.0V f or a period less th an 20ns. Maximu m DC

voltage on Output is V

3. Depends on range.

Ambient Operating Temperature

Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage (except A9) –2 to 7 V Supply Voltage –2 to 7 V A9 Voltage –2 to 13.5 V Program Supply Voltage –2 to 14 V

+0.5V with possible overshoot to VCC +2V for a period l ess than 20n s.

(3)

–40 to 125 °C

Table 3. Operating Modes

Mode E

Read Word-wide Read Byte-wide Upper Read Byte-wide Lower Output Disable Program

Verify Program Inhibit Standby Electronic Signature

Note: X = VIH or VIL, VID = 12V ± 0.5V.

Pulse V V

V V V V

V V

BYTEV

X X Hi-Z Hi-Z Hi-Z

A9 Q15A–1 Q14-Q8 Q7-Q0

X Data Out Data Out Data Out X X

Hi-Z Data Out Hi-Z Data Out

X Data In Data In Data In X Data Out Data Out Data Out X Hi-Z Hi-Z Hi-Z

X X X Hi-Z Hi-Z Hi-Z

Code Codes Codes

Table 4. Electronic Signature

Identifier A0

Manufacturer’s Code Device Code

Q15 and

Q14

and

Q13 and

Q12 and

Q11 and

Q10 and

and

and Q0Hex Data

00100000 20h 10110010 B2h

3/15

M27W800

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform

High Speed

1.5V

Standard

2.4V

0.4V

Table 6. Capacitance

(1)

(TA = 25 °C, f = 1 MHz)

2.0V

0.8V

AI01822

Figure 4. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE UNDER

TEST

CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance

OUT

AI01823B

Symbol Parameter Test Condition Min Max Unit

Input Capacitance (except BYTEVPP)V

OUT

Note: 1. Sampled only, not 100% tested.

Input Capacitance (BYTE Output Capacitance

VPP)V

OUT

= 0V = 0V

= 0V

10 pF

120 pF

12 pF

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M27W800

Table 7. Read Mode DC Characteristics

(1)

(TA = –40 to 85 °C; VCC = 2.7 to 3.6V; VPP = VCC)

Symbol Parameter Test Condition Min Max Unit

CC1

CC2

I V

Note: 1. VCC must be ap pl i e d simultaneously wi th or before VPP and removed simultaneously or after VPP.

Input Leakage Current

Output Leakage Curren t

Supply Current

Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current

Input Low Voltage –0.6

(2)

Input High Voltage Output Low Voltage

Output High Voltage TTL

2. Max imum DC volt age on Output i s V

+0.5 V.

0V ≤ V

= VIL, G = VIL, I

f = 8MHz, V

= VIL, G = VIL, I

f = 5MHz, V

> VCC – 0.2V, VCC ≤ 3.6V

OUT

= V

= 2.1mA

= –400µA

= V

≤ V

OUT

≤ 3.6V

OUT

≤ 3.6V

= 0mA,

±1 µA

±10 µA

30 mA

20 mA

1mA 15 µA 10 µA

0.2V

0.7V

2.4 V

VCC + 0.5

0.4 V

V V

Standby Mode

The M27W800 has a standby m ode which reduc-

es the supply current from 20mA to 20µA with low voltage operation V

≤ 3.6V, see Read Mode DC

Characteristics table for details.The M27W800 is placed in the standby mode b y applying a CMOS high signal to the E

input. When in the standby mode, the outputs are in a h igh impedanc e state, independent of the G

input.

Two Line Outp ut C ontrol

Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:

a. the lowest possible memory power dissipation, b. complete assurance tha t output bus contention

will not occur.

For the most efficient use of these two control lines, E ry device selecting function, while G

should be decoded and used as the prima-

should be made a common connectio n to all devices in the array and connected to the READ

line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.

System Considerations

The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the supplies to the devices. The supply current ICC has three segments of importance to the system designer: the standby current, the active current and the transient peaks that are produced by the falling and rising edges of E

. The magnitude of the transient current peaks is dependent on the capacitive and inductive loadi ng of the device outputs. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor is used on every device between V

and VSS. This should be a high frequency type of low inherent inductance and should be placed as close as possible to the device. In addition, a

4.7µF electrolytic capacitor should be used between V

and VSS for every eight devices. This

capacitor should be mounted near the power supply connection point. The purpose of this capacitor is to overcome the voltage d r op caus ed by the inductiv e effects of PCB traces.

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