SGS Thomson Microelectronics M27W401 Datasheet

M27W401

4 Mbit (512Kb x 8) Low Voltage UV EPROM and OTP EPROM

■ 2.7V to 3.6V LOW VOLTAGE in READ

OPERATION

■ ACCESS TIME:

–70nsatVCC= 3.0V to 3.6V –80nsatVCC= 2.7V to 3.6V

■ PIN COMPATIBLE with M27C4001

■ LOW POWER CONSUMPTION:

–15µA max Standby Current – 15mA max Active Current at 5MHz

■ PROGRAMMING TIME 100µs/byte

■ HIGH RELIABILITY CMOS TECHNOLOGY

– 2,000V ESD Protection – 200mA Latchup Protection Immunity

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Device Code: 41h

32

1

FDIP32W (F)

PLCC32 (K)

Figure 1. Logic Diagram

32

1

PDIP32 (B)

TSOP32 (N)

8 x 20 mm

DESCRIPTION

The M27W401 is a low voltage 4 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large data or program storage and is organisedas 524,288 by 8 bits.

The M27W401 operates in the read mode with a supply voltageas low as 2.7V at –40 to 85°C temperature range. The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery recharges.

The FDIP32W (window ceramic frit-seal package) has a transparent lid which allows the user to expose the chip to ultraviolet lightto erase thebitpattern. A new pattern can then be written to the device by following the programming procedure.

For application where thecontent is programmed only one time and erasure is not required, the M27W401 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages.

V

19

A0-A18 Q0-Q7

E

G

V

CC

M27W401

V

SS

PP

8

AI01590

1/15March 2000

M27W401

Figure 2A. DIP Connections

V

1

PP

2

A15

3

A12

4

A7

5

A6

6

A5

7

A4

8 A3 A2 A1 A0

Q0

Q2 SS

M27W401

9

10

11

12

13

14

15

16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

AI02676

V

CC

A18A16 A17 A14 A13 A8 A9 A11 G A10 E Q7 Q6 Q5Q1 Q4 Q3V

Figure 2B. LCC Connections

A16

A7 A6 A5 A4 A3 A2 A1 A0

Q0

A12

9

Q1

VPPV

A15

1

32

M27W401

17

Q2

Q3

SS

V

Q4

CC

A18

Q5

A17

25

Q6

A14 A13 A8 A9 A11 G A10 E Q7

AI01591

Figure 2C. TSOP Connections

A11 G

A9

A8 A13 A14 A17 A18

V

CC

V

PP

A16 A15 A12

A7

A6

A5

A4 A3

1

M27W401

8

(Normal)

9

16 17

32

25 24

AI01592

A10 E Q7 Q6 Q5 Q4 Q3 V

SS

Q2 Q1 Q0 A0 A1 A2

Table 1. Signal Names

A0-A18 Address Inputs Q0-Q7 Data Outputs E Chip Enable G Output Enable V

PP

V

CC

V

SS

Program Supply Supply Voltage Ground

2/15

M27W401

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

T

A

T

BIAS

T

STG

(2)

V

IO

V

CC

(2)

V

A9

V

PP

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extendedperiods may affect device reliability. Refer alsoto the STMicroelectronics SUREProgram andother relevant quality documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is V

3. Depends on range.

Ambient Operating Temperature Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage (except A9) –2 to 7 V Supply Voltage –2 to 7 V A9 Voltage –2 to 13.5 V Program Supply Voltage –2 to 14 V

+0.5V with possible overshoot to VCC+2V for a period less than 20ns.

CC

(3)

–40 to 85 °C

Table 3. Operating Modes

Mode E G A9

Read Output Disable V Program

V Verify V Program Inhibit Standby Electronic Signature

Note: X = VIHor VIL,VID= 12V ± 0.5V.

V

IL

Pulse V

IL

IH

V

IH

V

IH

V

IL

V

IL

V

IH

V

IL

V

IH

X XV X XVPPData Out X

XX

V

IL

V

ID

V

PP

V

or V

CC

SS

or V

CC

SS

V

PP

V

PP

V

or V

CC

SS

V

CC

Q7-Q0

Data Out

Hi-Z

Data In

Hi-Z Hi-Z

Codes

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code Device Code

V

IL

V

IH

00100000 20h 01000001 41h

3/15

M27W401

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform

High Speed

3V

1.5V

0V

Standard

2.4V

0.4V

Table 6. Capacitance

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note: 1. Sampled only, not 100% tested.

Input Capacitance Output Capacitance

(1)

(TA=25°C, f = 1 MHz)

2.0V

0.8V

AI01822

Figure 4. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE UNDER

TEST

C

L

CL= 30pFfor HighSpeed CL= 100pF for Standard CLincludes JIG capacitance

V

IN

OUT

=0V

6pF

12 pF

OUT

AI01823B

DEVICE OPERATION

The operating modes of theM27W401 are listed in the Operating Modes table.A single power supply is required in the read mode. All inputs are TTL levels exceptfor VPPand 12V on A9 for Electronic Signature.

Read Mode

The M27W401 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable(G)is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time

4/15

(t

) is equal to the delay from E to output

AVQV

(t

). Data is available attheoutputafteradelay

ELQV

of t

from the falling edge of G, assuming that

GLQV

E has been low and the addresses have been stable for at least t

AVQV-tGLQV

.

Standby Mode

The M27W401 has a standby mode which reduces the supply current from 15mA to 15µA with low voltage operation VCC≤ 3.6V, see Read Mode DC Characteristics table for details. The M27W401 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input.

M27W401

Table 7. Read Mode DC Characteristics

(1)

(TA= –40 to 85°C; VCC= 2.7V to 3.6V; VPP=VCC)

Symbol Parameter Test Condition Min Max Unit

I

CC

I

CC1

I

CC2

I V

V

IH

V

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

Two Line Output Control

Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:

a. the lowest possible memory power dissipation, b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control lines, Eshould be decodedand usedas theprimary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system controlbus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.

Input Leakage Current

LI

Output Leakage Current

LO

Supply Current

Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current

PP

Input Low Voltage –0.6

IL

(2)

Input High Voltage Output Low Voltage

OL

Output High Voltage TTL

OH

2. Maximum DC voltage on Output is V

CC

+0.5V.

E=V

IL

f = 5MHz, V

E>V

0V ≤ V

,G=VIL,I

CC

I

OH

≤ V

IN

CC

≤ V

OUT

E=V

–0.2V,VCC≤ 3.6V

V

PP=VCC

I

= 2.1mA

OL

= –400µA

CC

IH

CC

OUT

≤ 3.6V

= 0mA,

System Considerations

The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output.

The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between V and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be

±10 µA ±10 µA

15 mA

1mA 15 µA 10 µA

0.2 V

CC

0.7 V

CCVCC

2.4 V

+ 0.5

0.4 V

used between VCCand VSSfor every eight devices. The bulkcapacitor should be located near the power supply connection point.The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.

V V

CC

5/15