The M27W064 is a 64 Mbit (4Mb x16) non-volatile,
One Time Programmable (OT P), FlexibleROM™
Memory. Read operations can be performed using
a single low voltage (2.7 to 3.6V) supply. Program
operations require an additional V
(11.4 to
PP
12.6V) power supply. On power-up the memory
defaults to Read mode where it can be read in the
same way as a ROM or EPROM.
Program commands are written to t he Command
Interface of the memory. An on-chip Program Controller (PC) simplifies the process of programming
the memory by taking care of all of the special operations that are required to update the memory
conte nts.
The M27W064 features an in novative command,
Multiple Word Program, used to program large
streams of data. It greatly reduces the total pro-
Figure 2. Logic DiagramTable 1. Signal Names
gramming time when a large number of Words are
written to the memory at any one time. Using this
command the entire memory can be program m ed
in 8s, compared to 36s us ing the standard Word
Progra m.
The end of a program operation can be de tected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
Chip Enable and Output Enable signals control the
bus operation of the memory. They allo w simple
connection to most microprocessors, often without
additional logic.
The memory is offered in SO44 a nd TS OP48 (12
x 20mm) packages. T he mem ory is supplied with
all the bits set to ’1’.
A0-A21Address Inputs
V
V
22
A0-A21DQ0-DQ15
E
G
M27W064
V
CC
SS
PP
16
AI05960
DQ0-DQ15Data Inputs/Outputs
E
G
V
CC
V
PP
V
SS
NCNot Connected Internally
Chip Enable
Output Enable
Supply Voltage read
Supply Voltage program
Ground
4/23
Figure 3. SO Connecti onsFigure 4. TSOP Con nections
See Figure 2, Logic Diagram, and Table 1, Sign al
Names, for a brief overview of the signals connected to this de vice.
Address Inputs (A0-A21). The Address Inputs
select the cell s in th e memory array to a ccess during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the Program Controller.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the command
sent to the Command Interface of the Program
Controller. When reading the Status Register they
report the status of the ongoing algorithm.
Data Inputs/Outputs (DQ8-DQ15). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations the Command Interface does not
use these bits. When reading t he Status Register
these bits should be ignored.
Chip Enable (E
the memory, allowing Bus Read operat ions to be
performed. It also controls the B us Write operations, when V
Output Enable (G
trols the Bus Read operations of the memory. It
). The Chip Enable, E, activates
is in the VHH range.
PP
). The Ou tput Enable, G, con-
also allows Bus Write operations, when V
the V
V
range.
HH
Supply Voltage. The VCC Supply Voltage
CC
PP
is in
supplies the power for Read operations.
A 0.1µF capacitor should be connec ted between
the V
Supply Voltage pin and the VSS Ground
CC
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program operations, I
V
PP
.
CC3
Program Supply Voltage. VPP is both a
power supply and Write Protect pin. The two functions are selected by t he voltage range applie d t o
the pin.
When the V
is in the VHH range (see Table 10,
PP
DC Characteristic, for the relevant values) the Program operation is enabled. During such operations the V
If the V
must be stable in the VHH range.
PP
is kept under the VHH range, particularly
PP
in the voltage range 0 to 3.6V, any Program operation is disabled or stopped.
Note that V
must not be left floating o r uncon-
PP
nected as the device may become unreliable.
Vss Ground. The V
Ground is the reference
SS
for all voltage measurements.
6/23
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Wri te, Output Disable, Standby, Automatic Standby and
Electronic Signature. See Tables 2, Bus Operations, for a summary. Typically glitches of less
than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs and applying a Low signal, V
, to Chip En-
IL
able and Output Enable. The Data Inputs/Outpu ts
will output the value, see Figure 10, Read AC
Waveforms, and Table 11, Read AC Ch aracteristics, for details of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. Bus Write is enabled only
when V
is set to VHH. A valid Bus W rite opera-
PP
tion begins by setting the desired addres s on the
Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable. The Data I nputs/Outputs are latched by
the Command Interface on the rising edge of Chip
Enable. Output Enable must remain High, V
IH
during the whole Bus W rite operat ion . See Figure
11, Write AC Waveforms, and Table 12, Write AC
Characteristics, for details of the timing requirements.
Output Disa bl e . The Data Inputs/Outputs are in
the high impedance s tate when Output Enable is
High, V
.
IH
Standby. When Chip Enable is High, V
memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the S upply Current to the
Standby Supply Current, I
be held within V
± 0.2V. For the Standby current
CC
, Chip Enable should
CC2
level see Table 10, DC Characteristics.
During program operation the memory will cont in-
ue to use the Program Supply Current, I
Program operation until the operation completes.
Automatic Standby. If CMOS levels (V
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is reduced to the Standby Supply Current, I
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying t he signals
listed in Tables 2, Bus Operat ions, once the A uto
,
Select Command is executed. To exit Electronic
Signature mode, the Read/Reset command must
be issued.
M27W064
, the
IH
, for
CC3
± 0.2V)
CC
. The
CC2
Table 2. Bus Operations
OperationEG
HH
V
IL
V
IL
V
IH
V
IL
V
IL
Bus Read
Bus Write
Output DisableX
Standby
Read Manufacturer
Code
Read Device Code
Note: 1. X = VIL or VIH.
2. XX = V
3. When readin g Status Register during Program algorithm execution VPP must be kept at VHH.
, VIHor V
IL
V
IL
V
IH
V
IH
XXXHi-Z
V
IL
V
IL
V
PP
(3)
XX
V
HH
XXHi-Z
V
HH
V
HH
Address Inputs
A0-A21
Cell AddressData Output
Command AddressData Input
A0 = VIL, A1 = VIL,
Others VIL or V
A0 = VIH, A1 = VIL,
Others VIL or V
IH
IH
Data Inputs/Outputs
DQ15-DQ0
0020h
888Ah
7/23
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