SGS Thomson Microelectronics M27V402 Datasheet

M27V402
4 Mbit (256Kb x 16) Low Voltage UV EPROM and OTP EPROM
LOW VOLTAGEREAD OPERATION:
3V to 3.6V
FAST ACCESS TIME: 120ns
LOW POWERCONSUMPTION:
– Active Current15mA at 5MHz – Standby Current 20µA
PROGRAMMING VOLTAGE: 12.75V ± 0.25V
PROGRAMMING TIME: 100µs/byte (typical)
ELECTRONIC SIGNATURE
– Manufacturer Code:20h – Device Code: 8Dh
DESCRIPTION
The M27V402 is a low voltage, low power 4 Mbit UV erasable and electrically programmable EPROM, ideally suited for handheld and portable microprocessor systems requiring large programs. It is organized as 262,144 by16 bits.
The M27V402 operates in the read mode with a supply voltage as low as 3V. The decrease in op­erating power allowseither a reduction of the size of the battery or an increase in the time between battery recharges.
The FDIP40W (window ceramic frit-seal package) has a transparent lid which allows the user to ex­pose thechip to ultraviolet light to erase the bit pat­tern. A new pattern can then be written to the device by followingthe programming procedure.
40
1
FDIP40W (F) PDIP40 (B)
PLCC44 (K) TSOP40 (N)
Figure 1. Logic Diagram
V
18
A0-A17 Q0-Q15
CC
40
V
PP
1
10 x 20 mm
16
Table 1. Signal Names
A0-A17 Address Inputs Q0-Q15 Data Outputs E Chip Enable G Output Enable V
PP
V
CC
V
SS
Program Supply Supply Voltage Ground
E
G
M27V402
V
SS
AI01819
1/15May 1998
M27V402
Figure 2A. DIP Pin Connections
V
PP
Q15 Q14 Q13 Q12 Q11 Q10
Q9 Q8
V
SS Q7
Q6 Q5 Q4 Q3 Q2
Q0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
M27V402
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 2120
AI01862
V
CC
A17E A16 A15 A14 A13 A12 A11 A10 A9 V
SS
A8 A7 A6 A5 A4 A3 A2Q1 A1 A0G
Figure 2B. LCC Pin Connections
CC
VPPE
Q15
Q13
Q14
Q12 Q11 Q10
Q9 A10 Q8
V
SS
NC
Q6 Q5 Q4
12
Q3
Q2
Q1
Q0
M27V402
23
G
A17
V
NC
1
NC
44
A0
A1
A16
A2
A15
A3
A14
34
A4
A13 A12 A11
A9 V
SS
NC A8Q7 A7 A6 A5
AI01820
Figure 2C. TSOP Pin Connections
A9 A10 A11 A12 A6 A13 A14 A15 A16 A17
V
CC
V
PP
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
DQ9 DQ8
1
M27V402
10
(Normal)
11
E
20 21
40
31 30
AI01821
V
SS
A8 A7
A5 A4 A3 A2 A1 A0 G DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 V
SS
Warning: NC = Not Connected.
For applications wherethe content isprogrammed only one time and erasure is not required, the M27V256 is offered in PDIP40, PLCC44 and TSOP40 (10 x 20 mm) packages.
DEVICE OPERATION
The operating modes of the M27V402 arelisted in the OperatingModes table. A single power supply is required in the read mode. All inputs are TTL levels except for VPPand 12V on A9 forElectronic Signature.
Read Mode
The M27V402 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output controland should be used to gate data to the output pins, independent of device selection. Assuming that the addresses arestable, the address accesstime (t
) is equal to the delay from E to output
AVQV
(t
). Data is availableattheoutput after a delay
ELQV
of t
from the falling edge of G, assuming that
GLQV
E has been low and the addresses have been stable for at least t
AVQV-tGLQV
.
2/15
M27V402
Table 2. Absolute Maximum Ratings
(1)
Symbol Parameter Value Unit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
(2)
V
A9
V
PP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings onlyand operation of the device atthese or anyother conditions above those indicated in the Operating sections of this specification is not implied. Exposure toAbsolute Maximum Rating condi­tions for extended periods may affect device reliability. Referalso to the STMicroelectronics SUREProgram andotherrelevant qual­ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is V
3. Depends on range.
Ambient Operating Temperature Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C
Input or Output Voltage (except A9) –2 to 7 V Supply Voltage –2 to 7 V A9 Voltage –2 to 13.5 V Program Supply Voltage –2 to 14 V
+0.5V with possible overshoot to VCC+2V for a period less than20ns.
CC
(3)
–40 to 125 °C
Table 3. Operating Modes
Mode E G A9
Read Output Disable V Program
V Verify V Program Inhibit Standby Electronic Signature
Note: X = VIHor VIL,VID= 12V ± 0.5V.
V
IL
IL
Pulse V
IL
IH
V
IH
V
IH
V
IL
V
IL
V
IH
IH
V
IL
V
IH
X XV X XVPPData Out X
XX
V
IL
V
ID
V
PP
V
or V
CC
SS
or V
CC
SS
V
PP
V
PP
V
or V
CC
SS
V
CC
Q0-Q15
Data Out
Hi-Z
Data In
Hi-Z Hi-Z
Codes
Table 4. Electronic Signature
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code Device Code
V
IL
V
IH
Standby Mode
The M27V402 has a standbymode which reduces the supply current from 20mA to 20µA with low voltage operationVCC≤ 3.6V, see Read Mode DC
00100000 20h 10001101 8Dh
Characteristics table for details. The M27V402 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input.
3/15
M27V402
Table 5. AC Measurement Conditions
High Speed Standard
Input Rise and Fall Times 10ns 20ns Input Pulse Voltages 0 to3V 0.4V to 2.4V Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V
Figure 3. AC Testing Input OutputWaveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
Table 6. Capacitance
(1)
(TA=25°C, f = 1 MHz)
2.0V
0.8V
AI01822
Figure 4. AC Testing Load Circuit
1.3V
1N914
3.3k
DEVICE UNDER
TEST
C
L
CL= 30pF for HighSpeed CL= 100pF for Standard CLincludes JIG capacitance
OUT
AI01823B
Symbol Parameter Test Condition Min Max Unit
V
C
IN
C
OUT
Note: Sampled only, not 100% tested.
Input Capacitance Output Capacitance V
=0V
IN
=0V 12 pF
OUT
6pF
Two Line Output Control
Because EPROMs are usually used in larger memory arrays, the product features a 2 line con­trol function whichaccommodates the use of mul­tiple memory connection. The two line control function allows:
a. the lowest possible memory power dissipation, b. complete assurance that output bus contention
will not occur.
4/15
For the most efficient use of these two control lines, E should bedecodedand used asthe prima­ry device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselect­ed memory devicesare intheir lowpower standby mode and that the output pins are only active when data is required from a particular memory device.
M27V402
Table 7. Read Mode DC Characteristics
(1)
(TA = 0to 70°C, –20 to 70°C, –20 to 85°C or –40 to 85°C; VCC= 3.3V ± 10%; VPP=VCC)
Symbol Parameter TestCondition Min Max Unit
I
I
I
CC
I
CC1
I
CC2
I V
V
IH
V
V
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Input Leakage Current
LI
Output Leakage Current
LO
Supply Current
Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current
PP
Input Low Voltage –0.3 0.8 V
IL
(2)
Input High Voltage 2 Output Low Voltage
OL
Output High Voltage TTL
OH
Output High Voltage CMOS
2. Maximum DC voltage on Output is V
CC
+0.5V.
E=V
IL
f = 5MHz, V
E>V
0V V
0V V
,G=VIL,I
CC
I
OH
I
OH
V
IN
CC
V
OUT
CC
= 0mA,
OUT
= 3.6V
CC
E=V
IH
– 0.2V, VCC= 3.6V
V
PP=VCC
I
= 2.1mA
OL
= –400µA = –100µAV
2.4 V –0.7V
CC
±10 µA ±10 µA
20 mA
1mA 20 µA 10 µA
V
+1
CC
0.4 V
V
V
System Considerations
The power switching characteristics of Advanced CMOS EPROMs requirecareful decoupling of the devices. The supply current, ICC, has three seg­ments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the fallingand rising edgesof E. The magnitudeof the transient current peaks is dependent on the output capacitive and inductive loading of the de­vice.
The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling ca­pacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between V
CC
and VSS. This should be a high frequency capaci­tor of low inherent inductance and should be placed as close to the device as possible. In addi­tion, a 4.7µF bulk electrolytic capacitor should be
used between VCCand VSSfor every eight devic­es. The bulk capacitor should be located near the power supply connection point.Thepurpose of the bulk capacitor is to overcome the voltage drop caused bythe inductive effects of PCB traces.
Programming
When delivered (and after each erasure for UV EPROM), all bits of the M27V402 are in the ’1’ state. Data is introduced by selectively program­ming ’0’s into the desired bit locations. Although only ’0’s will beprogrammed, both ’1’s and ’0’s can be present in the data word. The only way to change a ’0’ to a’1’is by die exposure to ultraviolet light (UV EPROM). The M27V402 is in the pro­gramming modewhen VPPinput is at12.75V, Gia at VIHand E is pulsed to VIL. The data to be pro­grammedis applied to16 bitsin paralleltothe data output pins.
The levels required for the address and data in­puts are TTL. VCCis specified to be 6.25V ±
0.25V.
5/15
Loading...
+ 10 hidden pages