SGS Thomson Microelectronics M27V160 Datasheet

Low Voltage UV EPROM and OTP EPROM

■ 3V to 3.6V LOW VOLTAGE in READ

OPERATION

■ ACCESS TIME: 100ns

■ BYTE-WIDE or WORD-WIDE

CONFIGURABLE

■ 16 Mbit MASK ROM REPLACEMENT

■ LOW POWER CONSUMPTION

– Active Current 30mA at 8MHz
– Standby Current 60µA

■ PROGRAMMING VOLTAGE: 12.5V ± 0.25V

■ PROGRAMMING TIME: 50µs/word

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h
– Device Code: B1h

DESCRIPTION

The M27V160 is a low voltage 16 Mbit EPROM of­fered in the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiringlarge data or
program storage. It is organised as either 2 Mbit
words of 8 bit or 1 Mbit words of 16 bit. The pin-out
is compatible with a 16 Mbit Mask ROM.

The M27V160 operates in the read mode with a
supply voltage as low as 3V. The decrease in op­erating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.

The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex­pose the chiptoultraviolet light to erase thebitpat­tern. A new pattern can then be written rapidly to
the device by following the programming proce­dure.

For applications where the content is programmed
only one time and erasure is not required, the
M27V160 is offered in PDIP42 and SO44 packag­es.

M27V160

16 Mbit (2Mb x8 or 1Mb x16)

42

1

FDIP42W (F) SO44 (M)

42

1

PDIP42 (B)

Figure 1. Logic Diagram

V

CC

20

A0-A19

BYTEV

E

G

PP

M27V160

V

SS

44

1

Q15A–1

15

Q0-Q14

AI01898

1/15March 2000

M27V160

Figure 2A. DIP Connections

A18 A19

1
2

A7

3
4

A6

5

A5
A4

6

A3

7

A2

8

A1

9

A0

10

M27V160

V

SS

Q0
Q8
Q1
Q9

Q10

Q3

Q11

E

11
12

G

13
14
15
16
17
18
19
20
21

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

AI01899

A8A17
A9
A10
A11
A12
A13
A14
A15
A16
BYTEV
V

SS

Q15A-1
Q7
Q14
Q6
Q13
Q5Q2
Q12
Q4
V

CC

PP

Figure 2B. SO Connections

NC NC

A17 A8

A7
A6
A5
A4
A3
A2
A1
A0

V

SS

Q0
Q8

Q9

Q10

Q3

Q11

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17Q1
18
19
20
21

M27V160

E

G

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
2322

AI01900

A19A18

A9
A10
A11
A12
A13
A14
A15
A16
BYTEV
V

SS

Q15A-1
Q7
Q14
Q6
Q13
Q5Q2
Q12
Q4
V

CC

PP

Table 1. Signal Names

A0-A19 Address Inputs
Q0-Q7 Data Outputs
Q8-Q14 Data Outputs
Q15A–1 Data Output / Address Input
E Chip Enable
G
BYTEV

PP

V

CC

V

SS

NC Not Connected Internally

2/15

Output Enable
Byte Mode / Program Supply
Supply Voltage
Ground

DEVICE OPERATION

The operating modes of the M27V160 are listed in
the OperatingModes Table.A single power supply
is required in the read mode. All inputs are TTL
compatible except for VPPand 12V on A9 for the
Electronic Signature.

Read Mode

The M27V160 has two organisations, Word-wide
and Byte-wide.The organisation is selected bythe
signal level on the BYTEVPPpin. When BYTEV

PP

is at VIHthe Word-wide organisation is selected
and the Q15A–1 pin is used for Q15 Data Output.
When the BYTEVPPpinis at VILthe Byte-wide or­ganisation is selected and theQ15A–1 pin isused
for the Address Input A–1. When the memory is
logically regarded as 16 bit wide, but read in the
Byte-wide organisation, then with A–1 at VILthe
lower 8bits of the 16bit data are selected and with
A–1 at VIHthe upper 8 bits of the 16 bit data are
selected.

M27V160

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

T

A

T

BIAS

T

STG

(2)

V

IO

V

CC

(2)

V

A9

V

PP

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi­tions for extended periods may affect device reliability. Refer also tothe STMicroelectronics SURE Program andotherrelevant qual­ity documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V

3. Depends on range.

Ambient Operating Temperature
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C

Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V

+0.5V with possible overshoot to VCC+2V for a period less than 20ns.

CC

(3)

–40 to 125 °C

Table 3. Operating Modes

Mode E G

Read Word-wide
Read Byte-wide Upper V
Read Byte-wide Lower
Output Disable V
Program

V
Verify
Program Inhibit
Standby
Electronic Signature

Note: X = VIHor VIL,VID= 12V ± 0.5V.

V

IL

IL

V

IL

IL

Pulse V

IL

V

IH

V

IH

V

IH

V

IL

V
V
V

V

V

V

X X X Hi-Z Hi-Z Hi-Z

V

BYTEV

PP

IL

IL

IL

IH

IH

IL

IH

IL

V

IH

V

IL

V

IL

X X Hi-Z Hi-Z Hi-Z

V

PP

V

PP

V

PP

V

IH

A9 Q15A–1 Q14-Q8 Q7-Q0

X Data Out Data Out Data Out
XVIHHi-Z Data Out
X

V

IL

Hi-Z Data Out

X Data In Data In Data In
X Data Out Data Out Data Out
X Hi-Z Hi-Z Hi-Z

V

ID

Code Codes Codes

Table 4. Electronic Signature

Identifier A0

Manufacturer’s Code
Device Code

Q15

and

Q7

V

IL

V

IH

Q14

and

Q6

Q13
and

Q5

00100000 20h
10110001 B1h

The M27V160 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte- wide organisation must be selected.

Chip Enable (E) isthe power control andshould be
used fordevice selection. Output Enable (G) is the
output control and should be used to gate data to

Q12

and

Q4

Q11
and

Q3

Q10
and

Q2

Q9

and

Q1

Q8

andQ0Hex Data

the output pins independent of device selection.
Assuming that the addresses are stable, the ad­dress access time (t
from E to output (t

ELQV

output after a delay of t

) is equal to the delay

AVQV

). Data is available at the

from the falling edge

GLQV

of G, assuming that E has been low and the ad­dresseshavebeen stable forat least t

AVQV-tGLQV

3/15

.

M27V160

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform

High Speed

3V

1.5V

0V

Standard

2.4V

0.4V

Table 6. Capacitance

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note: 1. Sampled only, not 100% tested.

(1)

(TA=25°C, f = 1 MHz)

Input Capacitance (except BYTEVPP)V
Input Capacitance (BYTEV
Output Capacitance

2.0V

0.8V

AI01822

)V

PP

Figure 4. AC Testing Load Circuit

1.3V

1N914

Ω

3.3k

DEVICE
UNDER

TEST

C

L

CL= 30pFfor High Speed
CL= 100pFfor Standard
CLincludes JIG capacitance

V

IN

IN

OUT

=0V
=0V

=0V

10 pF

120 pF

12 pF

OUT

AI01823B

Standby Mode

The M27V160 hasa standby mode which reduces
the active currentfrom 20mAto 20µA with low volt-
age operation VCC≤ 3.6V, see Read Mode DC
Characteristics table for details.The M27V160 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.

Two Line Output Control

Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con­trol function which accommodates the use of mul­tiple memory connection. The two line control
function allows:

4/15

a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control
lines, Eshould be decoded and used asthe prima­ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect­ed memory devices are intheir low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.

M27V160

Table 7. Read Mode DC Characteristics

(1)

(TA= 0 to 70°C or –40 to 85°C; VCC= 3.3V ± 10%; VPP=VCC)

Symbol Parameter Test Condition Min Max Unit

I

I

I

CC

I

CC1

I

CC2

I
V

V

IH

V

V

Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.

Input Leakage Current

LI

Output Leakage Current

LO

E=V

0V ≤ V

0V ≤ V

,G=VIL,I

IL

f = 8MHz, V

Supply Current

E=V

,G=VIL,I

IL

f = 5MHz, V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current

PP

Input Low Voltage –0.3

IL

(2)

Input High Voltage
Output Low Voltage

OL

Output High Voltage TTL

OH

2. Maximum DC voltage on Output is V

CC

+0.5V.

E>V

CC

I

OH

≤ V

IN

CC

≤ V

OUT

E=V

CC

CC

IH

CC

OUT

≤ 3.6V

OUT

≤ 3.6V

= 0mA,

= 0mA,

–0.2V,VCC≤ 3.6V

V

PP=VCC

I

= 2.1mA

OL

= –400µA

±1 µA

±10 µA

30 mA

20 mA

1mA
60 µA
10 µA

0.2V

CC

0.7V

CC

VCC+1

0.4 V

2.4 V

V
V

System Considerations

The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current I

CC

has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E. The magnitude of the
transient current peaks is dependent on the ca­pacitive and inductive loading of the device out­puts. The associated transient voltage peaks can
be suppressed by complying with the two line out-

put control and by properly selected decoupling
capacitors.It is recommended thata 0.1µF ceram­ic capacitor is used on every device between V

CC

and VSS. This should be a high frequency type of
low inherent inductance and should be placed as
close as possible to the device. In addition, a

4.7µF electrolytic capacitor should be used be­tween VCCand VSSfor every eight devices. This
capacitor should be mounted near the power sup­ply connection point. The purposeof this capacitor
is to overcome the voltage drop caused by the in­ductive effects of PCB traces.

5/15