SGS Thomson Microelectronics M27C512 Datasheet

512 Kbit (64Kb x8) UV EPROM and OTP EPROM

5V ± 10% SUPPLY VOLTAGE in READ OPERATION

FAST A CCES S TIME : 45ns LOW POWER “CMOS” CONSUMPTION: – Active Current 30mA – Standby Current 100µA PROGRAMMING VOLTAGE : 12.75V ± 0.25V PROGRAMMING TIMES of AROU ND 6s ec.

(PRESTO IIB ALGORITHM) ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: 3Dh

DESCRIPTION

The M27C512 is a 512 Kbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for applications where fast turn-around and pattern experimentation are important requirements and is organized as 65,536 by 8 bits.

The FDIP28W (window ceramic frit-seal package) has transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure.

For applications where the content is programmed only one time and erasure is not required, the M27C512 is offered in PDIP28, PLCC32 and TSOP28 (8 x 13.4 mm) packages.

28

1

FDIP28W (F)

PLCC32 (C)

Figure 1. Logic Diagram

V

CC

16

A0-A15

M27C512

28

1

PDIP28 (B)

TSOP28 (N)

8 x 13.4mm

8

Q0-Q7

E

T ab le 1. Signal Names

GV

A0-A15 Address Inputs Q0-Q7 Data Outputs E Chip Enable GV

PP

V

CC

V

SS

November 1998 1/15

Output Enable / Program Supply Supply Voltage Ground

PP

M27C512

V

SS

AI00761B

M27C512

Figure 2A. DIP Pin Connections

A15 V

1

A12

2 3

A7

4

A6

5

A5

6

A4

7

A3 A2 A1 A0

Q0

Q2 SS

8 9 10 11 12 13 14

M27C512

28 27 26 25 24 23 22 21 20 19 18 17 16 15

AI00762

CC

A14 A13 A8 A9 A11 GV A10 E Q7 Q6 Q5Q1 Q4 Q3V

PP

Figure 2B. LCC Pin Connections

CC

DU

32

DU

V

Q3

A14

Q4

Warning

A15

A7

A12

A6 A5 A4 A3 A2

9 A1 A0

NC

Q0

Q1

: NC = Not Connected, DU = Don’t Use

1

M27C512

17

Q2

SS

V

A13

25

Q5

A8 A9 A11 NC GV A10 E Q7 Q6

AI00763

PP

Figure 2C. TSOP Pin Connections

GV

A11

A13 A14

V

A15 A12

PP

A9 A8

CC

A7 A6 A5 A4 A3

22

28

M27C512

1

78

21

15 14

AI00764B

A10 E Q7 Q6 Q5 Q4 Q3 V

SS

Q2 Q1 Q0 A0 A1 A2

DEVICE OPERATION

The modes of operations of the M27C512 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for

GVPP and 12V on A9 for

Electronic Signature.

Read Mode

The M27C512 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (

E) is the power control and should be used for device selection. Output Enable (

G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time

) is equal to the delay from E to output (t

(t

AV QV

Data is available at the output after a delay of t

ELQV

GLQV

from the falling edge of G, assuming that E has been low and the addresses have been stable for at least t

AVQV-tGLQV

.

Standby Mode

The M27C512 has a standby mode which reduces the active current from 30mA to 100µA The M27C512 is placed in the standby mode by applying a CMOS high signal to the

E input. When in the standby mode, the outputs are in a high impedance state, independent of the

GVPP input.

).

2/15

(1)

T ab le 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

BIAS

T

STG

(2)

V

IO

V

CC

(2)

V

A9

V

PP

Notes:

1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC

3. Depends on range.

Ambient Operating Temperature Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C Input or Output Voltages (except A9) –2 to 7 V Supply Voltage –2 to 7 V A9 Voltage –2 to 13.5 V Program Supply Voltage –2 to 14 V

may cause permanent damage to the device. These are stress rating s only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

voltage on Output is V

+0.5V with possible overshoot to VCC +2V for a period less than 20ns.

CC

(3)

–40 to 125 °C

T ab le 3. Operating Modes

M27C512

Mode E GV

Read V Output Disable V Program V Program Inhibit V Standby V Electronic Signature V

Note

: X = V

or VIL, VID = 12V ± 0.5V

IH

IL

Pulse V

IL

IH

IL

PP

V

IL

V

IH

PP

V

PP

X X Hi-Z

V

IL

A9 Q0 - Q7

X Data Out X Hi-Z X Data In X Hi-Z

V

ID

T able 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code V Device Code V

IL

IH

T wo Line Output Control

Because EPROMs are usually used in larger memory arrays, the product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:

a. the lowest possible memor y powe r dissipatio n, b. complete assurance that output bus contention

00100000 20h 00111101 3Dh

For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while

G should be made a common connection to all devices in the array and connected to the

READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.

will not occur.

Codes

3/15

M27C512

T able 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input O utput Waveform

High Speed

3V

1.5V

0V

Standard

2.4V

0.4V

Table 6. Capacitance

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note.

1. Sampled only, not 100% tested.

(1)

(TA = 25 °C, f = 1 MHz )

Input Capacitance VIN = 0V 6 pF Output Capacitance V

2.0V

0.8V

AI01822

Figure 4. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE UNDER

TEST

CL

CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance

= 0V 12 pF

OUT

AI01823B

System Considerations

The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, I

, has three seg-

CC

ments that are of interest t o the s ystem designer: the standby current level, t he active current level, and transient current peaks that are produced by the falling and rising edges of

E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output.

4/15

The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between V

CC

and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a

4.7µF bulk electrolytic capacitor should be used between V

and VSS for every eight devices. The

CC

bulk capacitor should be located near the power supplyconnection point.The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.

M27C512

T ab le 7. Read Mode DC Characteristics

(1)

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

Symbol Parameter Test Condition Min Max Unit

V

Notes:

I

LO

I

CC

I

CC1

I

CC2

I

PP

V

IH

V

Input Leakage Current 0V ≤ VIN ≤ V

LI

Output Leakage Current 0V ≤ V

Supply Current

E = VIL, G = VIL,

= 0mA, f = 5MHz

I

OUT

Supply Current (Standby) TTL E = V

OUT

≤ V

IH

CC

Supply Current (Standby) CMOS E > VCC – 0.2V 100 µA Program Current VPP = V Input Low Voltage –0.3 0.8 V

IL

(2)

Input High Voltage 2 VCC + 1 V Output Low Voltage IOL = 2.1mA 0.4 V

OL

Output High Voltage TTL IOH = –1mA 3.6 V

OH

Output High Voltage CMOS I

1. V

must be applied simultaneousl y with or before VPP and removed simultaneously or after VPP.

CC

2. Maximum DC voltage on Output is V

+0.5V.

CC

OH

CC

= –100µAV

±10 µA ±10 µA

30 mA

1mA

10 µA

–0.7V V

CC

T ab le 8A. Read Mode AC Characteristics

(1)

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

M27C512

Symbol Alt Parameter Test Condition

t

AVQVtACC

Address Valid to Output Valid

E = VIL, G = V

IL

Chip Enable

t

ELQV

t

CE

Low to Output

G = V

IL

Valid Output Enable

t

GLQV

t

OE

E = V

IL

Low to Output Valid

t

EHQZ

(2)

Chip Enable

t

High to Output

DF

G = V

IL

Hi-Z

t

GHQZ

(2)

Output Enable High to Output

t

DF

E = V

IL

Hi-Z Address

t

AXQX

t

OH

Transition to

E = VIL, G = V

IL

Output Transition

Notes.

1. V

must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

CC

2. Sampled only, not 100% tested.

3. In case of 45ns speed see High Speed AC measurement conditions.

-45

(3)

-60 -70 -80

Min Max Min Max Min Max Min Max

45 60 70 80 ns

25 30 35 40 ns

0 25 0 25 0 30 0 30 ns

0000ns

Unit

5/15