SGS Thomson Microelectronics M24C64-WMW6T, M24C64-WMW6, M24C64-WMN6T, M24C64-WMN6, M24C64-W Datasheet

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1/19December 1999

M24C64 M24C32

64/32 Kbit Serial I²C Bus EEPROM

■ Compat ible with I

C Extended Addressing

■ Two Wire I

C Serial Interface

Supports 400 kHz Protocol

■ Single Supply Voltage:

– 4.5V to 5.5V for M24Cxx – 2.5V to 5.5V for M24Cxx-W – 1.8V to 3.6V for M24Cxx-R

■ Hardware Write Control

■ BYTE and PAGE WRITE (up to 32 Bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Tim ed P ro g ra m ming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behavior

■ 1 Million Erase/Write Cycles (minimum)

■ 40 Year Data Retention (minimum)

DESCRIPTION

These I

C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 8192x8 bits (M24C64) and 4096x8 bits (M24C32), and operate down to 2.5 V (for the -W version of each device), and down to 1.8 V (for the

-R version of each device). The M24C64 and M24C32 are available in Plastic

Dual-in-Line, Plastic Small Outline and Thin Shrink Small Outline packages.

Figure 1. Logic Diagram

AI01844B

E0-E2 SDA

M24C64 M24C32

SCL

Table 1. Signal Names

E0, E1, E2 Chip Enable Inputs SDA Serial Data/Address Input/

Output SCL Serial Clock WC

Write Control V

Supply Voltage V

Ground

PSDIP8 (BN)

0.25 mm frame

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

SO8 (MW)

200 mil width

M24C64, M24C32

2/19

These memory devices are compatible with the I

C extended memory standard. This is a two wire serial interface that uses a bi-directiona l data bus and serial clock. The memory carries a built-in 4bit unique Device Type Identifier code (1010) in accordance with the I

C bus definition.

The memory behaves as a slave device in the I

C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, gene rated by the bus master. The START condition is followed by a Device Select Code and RW

bit (as described in

Table 3), terminated by an acknowledge bit. When writing data to the memory, the mem ory in-

serts an acknowledge bit during the 9

bit time,

following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by

a STOP condition after an Ack for WRITE, and after a NoAck for READ.

Power On Reset: V

Lock-Out Write Protect

In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The internal reset is held active until the V

voltage has reached the POR threshold value, and all operations are disabled – the device will not respond to any command. In the same way, when V

drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any com ma nd. A s table a nd v alid V

must be applied before applying any logic signal.

SIGNAL DESCRIPTION Serial Clock (SCL)

The SCL input pin is used to strobe all data in and out of the memory. In applications where this line is used by slaves to synchronize the bus to a slow-

Figure 2A. DIP Connections

SDAV

SCL

WCE1

E0 V

AI01845B

M24C64 M24C32

1 2 3 4

8 7 6 5

Figure 2B. SO and TSSOP Connections

AI01846B

2 3 4

8 7 6 5

SDAV

SCL

WCE1

E0 V

M24C64 M24C32

Table 2. Absolute Maximum Ratings

Note: 1. Exc ept for the rating “Operating Temperature Range”, stresses above those l i sted in the Table “Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indica te d i n the Operating secti ons of this specification is not im plied. Exposure to Absolute Ma xim um Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL -STD-883C, 3015.7 (100 pF, 1500 Ω)

Symbol Parameter Value Unit

Ambient Operating Temperature -40 to 125 °C

STG

Storage Temperature -65 to 150 °C

LEAD

Lead Temperature during Soldering

PSDIP8: 10 seconds SO8: 40 seconds TSSOP8: 40 second s

260 215 215

°C

Input or Output range -0.6 to 6.5 V

Supply Voltage -0.3 to 6.5 V

ESD Electrostatic Discharge Voltage (Human Body model)

4000 V

3/19

M24C64, M24C32

er clock, the master must have an open drain output, and a pull-up resistor must be connected from the SCL line to V

. (Figure 3 indicates how the value of the pull-up res istor c an be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the master has a push-pull (rather than open drain) output.

Serial Data (SDA)

The SDA pin is bi-directional, and is used to transfer data in or out of the memory. It is an open drain

output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from the SDA bus to V

. (Figure 3 indicates how the value of the

pull-up resistor can be calculated).

Chip Enable (E2, E1, E0)

These chip enable inputs are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. These inputs may be driven dynamically or tied to V

or VSS to establish the device select code (but

note that the V

and VIH levels for the inputs are

CMOS compatible, not TTL compatible).

Write Control (WC

)

The hardware Write Control pin (WC

) is useful for protecting the entire contents of the memory from inadvertent erase/write. The Write Control signal is used to enable (WC

=VIL) or disable (WC=VIH) write instructions to the entire memory area. When unconnected, the WC

input is internally read as

, and write operations are allowed.

When WC

=1, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged.

Please see the Application Note

AN404

for a more

detailed description of the Write Control feature.

DEVICE OPERATION

The memory device supports the I

C protocol. This is summarized in Figure 4, and is compared with other serial bus protocols in Application Note

AN1001

. Any device that sends data on to the bus is defined to be a transm itter, and any device that reads the data to be a receiver. The device that controls the data transfer is k nown as the master, and the other as the slave. A data transfer can only be initiated by the mas ter, which wi ll also provide the serial clock for synchronization. The memory device is always a slave device in all comm unication.

Start Condition

START is identified by a high t o low transition of the SDA line while the clock, SCL, is stable i n the high state. A START condition must precede any data transfer comman d. Th e m em ory devi ce continuously monitors (except during a program ming cycle) the SDA and SCL lines for a START condition, and will not respond unless one is given.

Stop Condition

STOP is identified by a low to high transition of the SDA line wh ile th e clock S CL is sta ble in the h igh state. A STO P condition terminates c ommunication between the memory device and the bus master. A STOP condition at the end of a Read command, after (and only after) a NoAck, forces the memory device into its standby state. A STOP condition at the end of a Write command triggers the interna l EEPRO M write cycle.

Figure 3. Maximum R

Value versus Bus Capacitance (C

BUS

) for an I2C Bus

AI01665

BUS

SDA

MASTER

SCL

BUS

100

BUS

(pF)

Maximum RP value (kΩ)

10 1000

fc = 400kHz

fc = 100kHz

M24C64, M24C32

4/19

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a successful byte transfer. The bus transmitter, whether it be master or slave, releases the SDA bus after sending eight bits of data. During the 9

clock pulse period, the receiver pulls the SDA bus low to acknowledge the receipt of the eight data bits.

Data Input

During data input, the memory device samples the SDA bus signal on the rising edge of the clock, SCL. For correct device operation, the SDA signal must be stable during the clock low-to-high transition, and the data must change

only

when the SCL

line is low.

Memory Addressing

To start communication betwee n the bus master and the slave memory, the master must initiate a START condition. Following this, the master sends the 8-bit byte, shown in Table 3, on the SDA bus

line (most significant bit first). This consists of the 7-bit Device Select Code, and the 1-bit Read/Write Designator (RW). The Device Select Code i s further su bdi v i d ed i n to : a 4 -b i t D e vi c e T y pe Iden t if i er,

and a 3-bit Chip Enable “Address” (E2, E1, E0). To address the memory array, the 4-bit Device

Type Identifier is 1010b. Up to eight memory devices can be connected on

a single I

C bus. Each one is given a uniq ue 3-bit code on its Chip Enable inputs. When the Dev ice Select Code is received on the SDA bus, the memory only responds if the Chip Select Code is the same as the pattern applied to its Chip Enable pins.

The 8

bit is th e RW bit. This is set to ‘1’ for read and ‘0’ for write operations. If a match occurs on the Device Select Cod e, th e corresponding memory gives an acknowledgment on the SDA bus during the 9

bit time. If the memo ry does n ot ma tch

Figure 4. I

C Bus Protocol

SCL

SDA

SCL

SDA

START

CONDITION

SDA

INPUT

SDA

CHANGE

AI00792

STOP

CONDITION

1 23 789

MSB

ACK

START

CONDITION

SCL

1 23 789

MSB ACK

STOP

CONDITION

5/19

M24C64, M24C32

the Device Select Code, it deselects itself from the bus, and goes into stand-by mode.

There are two modes both for read and write. These are summarized in Table 6 and described later. A communication between the m aster and the slave is ended with a STOP condition.

Each data byte in the m emory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 4) is sent first, f ollowed by the Least significant Byte (Table 5). Bits b15 to b0 form t he addre ss of the byte in memory. Bits b15 to b13 are treated as

a Don’t Care bit on the M24C64 memory. Bits b15 to b12 are treated as Don’t Care bits on the M24C32 me m o r y .

Write Operations

Following a START con dition the ma ster sends a Device Select Code with the RW

bit set to ’0’, as shown in Table 6. The memory acknowledges this, and waits for two address bytes. The memory responds to each address byte with an acknowledge bit, and then waits for the data byte.

Writing to the memory may be inhibited if the WC input pin is taken high. Any write command with WC

=1 (during a period of time from the START condition until the end of the two address bytes) will not modify the me mory c ontents, and t he accompanying data bytes will

not

be acknowledged

(as shown in Figure 5).

Byte Write

In the Byte Write mode, after the Device Select Code and the address bytes, the master sends one data byte. If the addressed lo cation is write

protected by the WC

pin, the memory replies with a NoAck, and the location is not modified. If, instead, the WC

pin has been held at 0, as shown in Figure 6, the memory replies with an Ack. The master terminates the transfer by generating a STOP condition.

Page Write

The Page Write mode allows u p to 32 by tes to be written in a single write cycle, provided that they are all located in the same ’row’ in the memory: that is the most significant memory add ress bits (b12-b5 for the M24C64 and b11-b5 for the M24C32) are the same. If more bytes are sent than will fit up to the end of t he row, a condit ion known as ‘roll-over’ occurs. Data starts to become overwritten (in a way not formally specified in this data sheet).

The master sends from one up to 32 bytes of data, each of which is acknow ledged by the memory if the W C

pin is low. If the WC pin is high, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte i s tran sferred, the i nte rnal

Table 3. Device Select Code

Note: 1. The most significant bit, b7, is sent first.

Device Type Identifier Chip Enable RW

b7 b6 b5 b4 b3 b2 b1 b0

Device Select Code 1 0 1 0 E2 E1 E 0 RW

Table 4. Most Significant Byte

Note: 1. b15 to b13 are Don’t Care on the M24C6 4 series.

b15 to b12 are Don’t Care on the M 24C32 serie s.

Table 5. Least Significant Byte

b15 b14 b13 b12 b11 b10 b9 b8

b7 b6 b5 b4 b3 b2 b1 b0

Table 6. Operating Modes

Note: 1. X = V

or V

Mode RW bit

Bytes Initial Sequence

Current Address Read 1 X 1 START, Device Select, RW

= ‘1’

Random Address Read

START, Device Select, RW

= ‘0’, Address

1 X reSTART, Device Select, RW

= ‘1’ Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read Byte Write 0 V

1 START, Device Select, RW = ‘0’

Page Write 0 V

≤ 32 START, Device Select, RW = ‘0’

M24C64, M24C32

6/19

Figure 5. Wri te Mo de S e qu e nces with WC=1 (data write inhib i ted)

STOP

START

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

START

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

DATA IN 2

AI01120B

PAGE WRITE (cont'd)

WC (cont'd)

STOP

DATA IN N

ACK ACK ACK NO ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK NO ACK

byte address counter (the 5 least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition.

When the master generates a STOP condition im-

mediately after the Ack bit (in the “10

bit” time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered. A STOP condition at any other time does not t rigger the internal write cycle.

During the internal write cycle, the SDA input is disabled internally, and the device does not respond to any requests.

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