SGS Thomson Microelectronics M24512-W, M24512-R, M24512 Datasheet

M24512

512 Kbit Serial I²C Bus EEPROM

PRODUCT PREVIEW

■ Compat ible with I

■ Two Wire I

2

C Extended Addressing

2

C Serial Interface

Supports 400 kHz Protocol

■ Single Supply Voltage:

– 4.5V to 5.5V for M24512
– 2.5V to 5.5V for M24512-W
– 1.8V to 3.6V for M24512-R

■ Hardware Write Control

■ BYTE and PAGE WRITE (up to 128 Bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Tim ed P ro g ra m ming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behaviour

■ 100000 Erase/Write Cycles (minimum)

■ 40 Year Data Retention (minimum)

DESCRIPTION

These I

2

C-compatible electrically erasable pro­grammable memory (EEPROM) devices are or­ganised as 64Kx8 bits, and operate down to 2.5 V
(for the -W version), and down to 1.8 V (for the -R
version).

The and M24512 are available in Plastic Dual-in­Line, Plastic Small Out line and T hin Shrink Small
Outline packages.

These memory devices are compatible with the

2

C extended memory standard. This is a two wire

I

Table 1. Signal Names

E0, E1, E2 Chip Enable Inputs

8

PSDIP8 (BN)

0.25 mm frame

16

SO16 (MJ)

300 mil width

Figure 1. Logic Diagram

V

CC

3

E0-E2

SCL

M24512

1

1

SDA

SDA Serial Data/Address Input/

Output
SCL Serial Clock
WC
V

CC

V

SS

September 1999

This is preliminary information on a new product now in development. Details are subject to change without notice.

Write Control

Supply Voltage

Ground

WC

V

SS

AI02275

1/16

M24512

Figure 2A. DIP Connections

M24512

1

E0 V

2
3

E2

4

SS

8
7
6
5

AI02276

CC

WCE1
SCL
SDAV

serial interface that uses a bi-directiona l data bus
and serial clock. The memory carries a built-in 4­bit unique Device Type Identifier code (1010) in
accordance with the I

The memory behaves as a slave device in the I

2

C bus definition.

2

protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, gene rated by the
bus master. The START condition is followed by a
Device Select Code and RW

bit (as described in

Table 3), terminated by an acknowledge bit.
When writing data to the memory, the mem ory in-

serts an acknowledge bit during the 9

th

bit time,

following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by

Figure 2B. SO C on ne ct i on s

M24512

NC
NC

E0
E1
E2

V

SS

NC

Note: 1. NC = Not Connected

16

1
2
3
4
5
6
7
8

AI02286

15
14
13
12
11
10

NC
NC
V

CC

WC
SCL
SDA
NC

9

NCNC

a STOP condition after an Ack for WRITE, and af­ter a NoAck for READ.

Power On Reset: V

In order to prevent data corruption and inadvertent

C

write operations during power up, a Power On Re-

Lock-Out Write Protect

CC

set (POR) circuit is included. The internal reset is
held active until the V

voltage has reached the

CC

POR threshold value, and all operations are dis­abled – the device will not respond to any com­mand. In the same way, when V

drops from the

CC

operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any com ma nd. A s table a nd v alid V
must be applied before applying any logic signal.

CC

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

STG

T

LEAD

V

IO

V

CC

V

ESD

Note: 1. Exc ept for the rating “Operating Temperature Ra nge”, stres ses above those listed in the Table “Absolute Maximum Ratings” may

2/16

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indi cated in t he Operating sect i ons of thi s specifi cation i s not impl i ed. Exposure to Absolute M aximum Rating c ondi­tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL -STD-883C, 3015.7 (1 00 pF, 1500 Ω)

3. EIA J I C-121 (Condition C) (200 pF, 0 Ω)

Ambient Operating Temperature -40 to 125 °C
Storage Temperature -65 to 150 °C

Lead Temperature during Soldering

Input or Output range -0.6 to 6.5 V
Supply Voltage -0.3 to 6.5 V

Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)

1

PSDIP8: 10 sec
SO8: 40 sec

2

3

260
215

4000 V

500 V

°C

M24512

SIGNAL DESCRIPTION
Serial Clock (SCL)

The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slow­er clock, the master must have an open drain out­put, and a pull-up resistor must be connected from
the SCL line to V

. (Figure 3 indicates how the

CC

value of the pull-up res istor c an be calculated). In
most applications, though, this method of synchro­nization is not employed, and so the pull-up resis­tor is not necessary, provided that the master has
a push-pull (rather than open drain) output.

Serial Data (SDA)

The SDA pin is bi-directional, and is used to trans­fer data in or out of the memory. It is an open drain

output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to V

. (Figure 3 indicates how the value of the

CC

pull-up resistor can be calculated).

Chip Enable (E2, E1, E0)

These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code.
These inputs may be driven dynamically or tied to
V

or VSS to establish the device select code (but

CC

note that the V

and VIH levels for the inputs are

IL

CMOS compatible, not TTL compatible). When
unconnected, the E2, E 1 and E0 inp uts are in ter­nally read as V

Write Control (WC

The hardware Write Control pin (WC

(see Table 7 and Table 8)

IL

)

) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC

=VIL) or disable (WC=VIH)

write instructions to the entire memory area. When
unconnected, the WC
V

, and write operations are allowed.

IL

When WC

=1, Device Select and Address bytes

input is internally read as

are acknowledged, Data bytes are not acknowl­edged.

Please see the Application Note

AN404

for a more

detailed description of the Write Control feature.

DEVICE OPERATION

2

The memory device supports the I

C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note

AN1001

. Any device that sends data on to the bus
is defined to be a transm itter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is k nown as the master,
and the other as the slave. A data transfer can only
be initiated by the mas ter, which wi ll also provide
the serial clock for synchronization. The memory
device is always a slave device in all comm unica­tion.

Start Condition

START is identified by a high t o low transition of
the SDA line while the clock, SCL, is s table i n t he
high state. A START condition must precede any
data transfer comman d. Th e m em ory devi ce con­tinuously monitors (except during a program ming
cycle) the SDA and SCL lines for a START condi­tion, and will not respond unless one is given.

Stop Condition

STOP is identified by a low to high transition of the
SDA line wh ile th e clock S CL is sta ble in the h igh
state. A STO P condition terminates c ommunica­tion between the memory device and the bus mas­ter. A STOP condition at the end of a Read

Figure 3. Maximum R

20

16

12

8

Maximum RP value (kΩ)

4

0

10 1000

Value versus Bus Capacitance (C

L

fc = 100kHz

fc = 400kHz

100

C

(pF)

BUS

) for an I2C Bus

BUS

MASTER

V

CC

R

SDA

SCL

R

C

BUS

L

C

BUS

AI01665

3/16

L

M24512

Figure 4. I

2

C Bus Protocol

SCL

SDA

SCL

SDA

SCL

SDA

START

CONDITION

START

CONDITION

SDA

INPUT

1 23 789

MSB

1 23 789

MSB ACK

SDA

CHANGE

CONDITION

ACK

STOP

STOP

CONDITION

command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the interna l EEPRO M write cycle.

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a suc­cessful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9

th

clock
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.

Data Input

During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transi-

only

tion, and the data must change

when the SCL

line is low.

4/16

AI00792

Memory Addressing

To start communication betwee n the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code i s fur­ther su bdi v i de d i n to : a 4 -b i t D e vi c e Type I d en t if i er ,

and a 3-bit Chip Enable “Address” (E2, E1, E0).
To address the memory array, the 4-bit Device

Type Identifier is 1010b.
Up to eight memory devices can be connected on

a single I

2

C bus. Each one is given a uniq ue 3-bit
code on its Chip Enable inputs. When the Device
Select Code is received on the SDA bus, the mem­ory only responds if the Chip Select Code is the
same as the pattern applied to its Chip Enable
pins.

M24512

Table 3. Device Select Code

b7 b6 b5 b4 b3 b2 b1 b0

Device Select Code 1 0 1 0 E2 E1 E0 RW

Note: 1. The most significant bit, b7, is sent firs t.

The 8th bit is th e RW bit. This is set to ‘1’ for read

and ‘0’ for write operations. If a match occurs on
the Device Select Cod e, th e corresponding mem­ory gives an acknowledgment on the SDA bus dur­ing the 9

th

bit time. If the memo ry does n ot match
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.

1

Device Type Identifier Chip Enable RW

Table 4. Most Significant Byte

b15 b14 b13 b12 b11 b10 b9 b8

Table 5. Least Significant Byte

b7 b6 b5 b4 b3 b2 b1 b0

There are two modes both for read and write.
These are summarized in Table 6 and described
later. A communication between the m aster and
the slave is ended with a STOP condition.

Each data byte in the m emory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta­ble 4) is sent first, f ollowed by the Least significant
Byte (Table 5). Bits b15 to b0 form t he addre ss of
the byte in memory.

Byte Write

In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed lo cation is write
protected by the WC

pin, the memory replies with
a NoAck, and the location is not modified. If, in­stead, the WC

pin has been held at 0, as shown in
Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a

Write Operations

Following a START con dition the ma ster sends a
Device Select Code with the RW

bit set to ’0’, as
shown in Table 6. The memory acknowledges this,
and waits for two address bytes. The memory re­sponds to each address byte with an acknowledge
bit, and then waits for the data byte.

Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC

=1 (during a period of time from the START
condition until the end of the two address bytes)
will not modify the me mory c ontents, and t he ac-

not

companying data bytes will

be acknowledged,

as shown in Figure 5.

STOP condition.

Page Write

The Page Write mode allows up to 128 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory add ress bits
(b15-b7) are the same. If more bytes are sent than
will fit up to t he en d of t he row, a condition known
as ‘roll-over’ occurs. Data starts to become over­written (in a way not formally specified in this data
sheet).

The master sends from one up to 128 bytes of da­ta, each of which is acknowledged by the memory
if the WC

pin is low. If the WC pin is high, the con­tents of the addressed memory location are not
modified, and each data byte is followed by a

Table 6. Operating Modes

Mode RW bit

Current Address Read 1 X 1 START, Device Select, RW

Random Address Read

Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read
Byte Write 0 V
Page Write 0 V

Note: 1. X = V

IH

or V

.

IL

0X
1 X reSTART, Device Select, RW

WC

1

IL

IL

Bytes Initial Sequence

= ‘1’

1

START, Device Select, RW

1 START, Device Select, RW = ‘0’

≤ 128 START, Device Select, RW = ‘0’

= ‘0’, Address

= ‘1’

5/16