SGS Thomson Microelectronics M24256B-W, M24256B, M24128B-W, M24128B Datasheet

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PRELIMINARY DATA

February 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M24256-B M24128-B

256/128 Kbit SerialI C Bus EEPROM

With Three Chip Enable Lines

■ Compatible with I

C Extended Addressing

■ Two Wire I

C Serial Interface

Supports 400 kHz Protocol

■ Single Supply Voltage:

– 4.5V to 5.5V for M24xxx-B – 2.5V to 5.5V for M24xxx-BW – 1.8V to 3.6V for M24xxx-BR

■ Hardware Write Control

■ BYTE and PAGE WRITE (up to 64 Bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Timed Programming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behavior

■ 100000 Erase/Write Cycles (minimum)

■ 40 Year Data Retention (minimum)

DESCRIPTION

These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 32Kx8 bits (M24256-B) and 16Kx8 bits (M24128-B).

These memory devices are compatible with the I2C extended memory standard. Thisis a two wire serial interface that uses a bi-directional data bus and serial clock. The memory carries a built-in 4bit unique Device Type Identifier code (1010) in accordance with the I2C bus definition.

Figure 1. Logic Diagram

AI02809

SDA

M24256-B M24128-B

SCL

E0-E2

Table 1. Signal Names

E0, E1, E2 Chip Enable Inputs SDA Serial Data/Address Input/

Output SCL Serial Clock WC Write Control V

Supply Voltage V

Ground

PSDIP8 (BN)

0.25 mm frame

SO8 (MN)

150 mil width

TSSOP8(DW)

169 mil width

TSSOP14 (DL)

169 mil width

M24256-B, M24128-B

2/19

The memory behaves as a slave device in the I2C protocol, with all memory operations synchronized by theserial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition isfollowed by a Device Select Code and RW bit (as described in Table 3), terminated by an acknowledge bit.

When writing data to the memory, the memory inserts an acknowledge bit during the 9thbit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ.

Power On Reset: VCCLock-Out Write Protect

In order to preventdata corruptionand inadvertent write operationsduring power up, a Power On Re-

Figure 2A. PSDIP8 Connections

Figure 2B. SO8 and TSSOP8 Connections

SDAV

SCL

WCE1

E0 V

AI02810

M24256-B M24128-B

1 2 3 4

8 7 6 5

AI02811

2 3 4

8 7 6 5 SDAV

SCL

WCE1

E0 V

M24256-B M24128-B

Figure 2C. TSSOP14 Connections

Note: 1. NC = Not Connected

AI02812

2 3 4

8 SDAV

E2 SCL

M24256-B M24128-B

NC NC

5 6 7

Table 2. Absolute Maximum Ratings

Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may

cause permanent damage tothe device.These are stress ratings only, and operation of thedevice at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions forextended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)

Symbol Parameter Value Unit

Ambient Operating Temperature -40 to 125 °C

STG

Storage Temperature -65 to 150 °C

LEAD

Lead Temperature during Soldering

PSDIP8: 10 seconds SO8: 40 seconds TSSOP8: 40 seconds TSSOP14: 40 seconds

260 215 215 215

°C

Input or Output range -0.6 to 6.5 V

Supply Voltage -0.3 to 6.5 V

ESD Electrostatic Discharge Voltage (Human Body model)

4000 V

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M24256-B, M24128-B

set (POR) circuit is included. The internal reset is held active until the VCCvoltage has reached the POR threshold value, and all operations are disabled – the device will not respond to any command. In the same way,when VCCdrops from the operating voltage, below thePOR thresholdvalue, all operations are disabled and the device will not respond to any command. A stable and valid V

must be applied before applying any logic signal.

SIGNAL DESCRIPTION Serial Clock (SCL)

The SCL input pin is used to strobeall data in and out of the memory. In applications where this line is used by slaves to synchronize thebus to a slower clock, the master must have an open drain output, and apull-up resistor mustbe connected from the SCL line to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications,though, thismethod ofsynchronization is not employed, and so thepull-up resistor is not necessary, provided that the master has a push-pull (rather than open drain) output.

Serial Data (SDA)

The SDA pin is bi-directional, and isused to transfer datain or out of the memory. It is anopen drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from the SDA bus to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated).

Chip Enable (E2, E1, E0)

These chip enable inputs areused toset the value that isto be looked for on the three leastsignificant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied directly to VCCor VSSto

establish the device select code. When unconnected, the E2, E1 and E0 inputs are internally read as VIL(see Table 7 and Table 8)

Write Control (WC)

The hardware Write Control pin (WC) is useful for protecting the entire contents of the memory from inadvertenterase/write. TheWrite Control signalis used to enable (WC=VIL) or disable (WC=VIH) write instructions to the entire memoryarea. When unconnected, the WC input is internally read as VIL, and write operations are allowed.

When WC=1, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged.

Please seethe Application Note

AN404

for amore

detailed description of the Write Control feature.

DEVICE OPERATION

The memory device supports the I2C protocol. This is summarized in Figure 4, and is compared with other serial bus protocols in Application Note

AN1001

. Any device thatsends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the master, andthe otheras the slave.A datatransfer canonly be initiated by the master, which will also provide the serial clock for synchronization. The memory device is always a slave device in all communication.

Start Condition

START is identified by a high to low transition of the SDA line while the clock, SCL, is stable in the high state. A START condition must precede any data transfer command. The memory device continuously monitors (except during a programming

Figure 3. Maximum RLValue versus Bus Capacitance (C

BUS

) for an I2C Bus

AI01665

BUS

SDA

MASTER

SCL

BUS

100

BUS

(pF)

Maximum RP value (kΩ)

10 1000

fc = 400kHz

fc =100kHz

M24256-B, M24128-B

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cycle) the SDA and SCL lines for a START condition, and will not respond unless one is given.

Stop Condition

STOP isidentified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the memory device and the bus master. A STOP condition at the end of a Read command, after (and only after) a NoAck, forces the memory device into its standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a successful byte transfer. The bus transmitter, whether it be master or slave, releases the SDA bus after sending eight bits of data. During the 9thclock pulse period, the receiver pulls the SDA bus low to acknowledge the receipt of the eight data bits.

Data Input

During data input, thememory device samples the SDA bus signal on the rising edge of the clock, SCL. For correct device operation, theSDA signal must be stable during the clock low-to-high transition, and the data must change

only

whenthe SCL

line is low.

Memory Addressing

To start communication between the bus master and the slave memory, the master must initiate a START condition. Following this,the master sends the 8-bit byte, shown in Table 3, on the SDA bus line (most significant bit first). This consists of the 7-bit DeviceSelect Code, andthe 1-bit Read/Write Designator (RW). The Device Select Code is further subdivided into:a 4-bitDevice Type Identifier, and a 3-bit Chip Enable “Address” (E2, E1, E0).

To address the memory array, the 4-bit Device Type Identifier is 1010b.

Figure 4. I2C Bus Protocol

SCL

SDA

SCL

SDA

START

CONDITION

SDA

INPUT

SDA

CHANGE

AI00792

STOP

CONDITION

123 789

MSB

ACK

START

CONDITION

SCL

123 789

MSB ACK

STOP

CONDITION

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M24256-B, M24128-B

Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on its Chip Enable inputs. When the Device Select Codeis received onthe SDA bus, the memory only responds if the Chip Select Code is the same as the pattern applied to its Chip Enable pins.

The 8thbit is the RW bit. This is set to ‘1’ for read and ‘0’ for write operations. If a match occurs on the Device Select Code, the corresponding memory gives an acknowledgment onthe SDA bus during the 9thbit time. If the memory does not match the Device SelectCode, itdeselects itself fromthe bus, and goes into stand-by mode.

There are two modes both for read and write. These are summarized in Table 6 and described later. A communication between the master and the slave is ended with a STOP condition.

Each data byte in the memory has a 16-bit (two byte wide)address. The MostSignificantByte (Table 4) issent first, followed by the Least significant Byte (Table 5). Bits b15 to b0 form the address of the byte in memory. Bit b15 is treated as a Don’t Care bit on the M24256-B memory. Bits b15 and b14 aretreated as Don’t Carebits on the M24128B memory.

Write Operations

Following a START condition the master sends a Device Select Code with the RW bit set to ’0’, as shown inTable 6.The memoryacknowledges this, and waits for two address bytes. The memory re-

sponds to each address bytewith an acknowledge bit, and then waits for the data byte.

Writing to the memory may be inhibited if the WC input pin is taken high. Any write command with WC=1 (during a period of time from the START condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes will

not

be acknowledged,

as shown in Figure 5.

Byte Write

In the Byte Write mode, after the Device Select Code and the address bytes, the master sends one data byte. If the addressed location is write protected by the WC pin, the memory replies with a NoAck, and the location is not modified. If, instead, the WC pinhas been held at0, asshown in Figure 6, the memory replies with an Ack. The master terminates the transfer by generating a STOP condition.

Page Write

The Page Write mode allows up to 64 bytes to be written in a single write cycle, provided that they are all located in the same ’row’ in the memory:

Table 3. Device Select Code

Note: 1. The most significant bit, b7, is sent first.

Device Type Identifier Chip Enable RW

b7 b6 b5 b4 b3 b2 b1 b0

Device Select Code 1 0 1 0 E2 E1 E0 RW

Table 4. Most Significant Byte

Note: 1. b15 is treated as Don’t Care on the M24256-B series.

b15 and b14 are Don’t Care on the M24128-B series.

Table 5. Least Significant Byte

b15 b14 b13 b12 b11 b10 b9 b8

b7 b6 b5 b4 b3 b2 b1 b0

Table 6. Operating Modes

Note: 1. X = V

or V

Mode RW bit

Data Bytes Initial Sequence

Current Address Read 1 X 1 START, Device Select, RW = ‘1’

Random Address Read

START, Device Select, RW = ‘0’, Address

1 X reSTART, Device Select, RW = ‘1’ Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read Byte Write 0 V

1 START,Device Select, RW = ‘0’

Page Write 0 V

≤ 64 START, Device Select, RW = ‘0’

M24256-B, M24128-B

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Figure 5. Write Mode Sequences with WC=1 (data write inhibited)

STOP

START

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

START

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

DATA IN 2

AI01120B

PAGE WRITE (cont’d)

WC (cont’d)

STOP

DATA IN N

ACK ACK ACK NO ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK NO ACK

that is the most significant memory address bits (b14-b6 for the M24256-B and b13-b6 for the M24128-B) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. Data starts to become overwritten (in a way not formally specified in this data sheet).

The mastersends from one up to 64 bytes ofdata, each of which is acknowledged by the memory if the WC pin is low. If the WC pin is high, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (the 6 least significant bits only) is incremented.The transfer is terminated by the master generating a STOP condition.

When the master generates a STOP condition immediately after the Ack bit (in the “10thbit” time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered.

A STOP condition at any other time does not trigger the internal write cycle.

During the internal write cycle, the SDA input is disabled internally, and the device does not respond to any requests.

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