SGS Thomson Microelectronics M24256-WBN6, M24256-W, M24256-MW6, M24256-BN6, M24256 Datasheet

1/16

PRELIMINARY DATA

November 1999

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M24256
M24128

256/128 Kbit Serial I²C Bus EEPROM

Without Chip Enable Lines

■ Compat ible with I

2

C Extended Addressing

■ Two Wire I

2

C Serial Interface

Supports 400 kHz Protocol

■ Single Supply Voltage:

– 4.5V to 5.5V for M24xxx
– 2.5V to 5.5V for M24xxx-W

■ Hardware Write Control

■ BYTE and PAGE WRITE (up to 64 Bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Tim e d P ro g r amming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behavior

■ 100,000 Erase/Write Cycles (minimum)

■ 40 Year Data Retention (minimum)

DESCRIPTION

These I

2

C-compatible electrically erasable pro­grammable memory (EEPROM) devices are orga­nized as 32Kx8 bits (M24256) and 16Kx8 bits
(M24128), and operate down to 2.5 V (for the -W
version of each device).

The M24256 and M 24128 are available in Plastic
Dual-in-Line and Plastic Small Outline packages.

These memory devices are compatible with the
I

2

C extended memory standard. This is a two wire
serial interface that uses a bi-directiona l data bus
and serial clock. The memory carries a built-in 4­bit unique Device Type Identifier code (1010) in
accordance with the I

2

C bus definition.

Figure 1. Logic Diagram

AI01882

SDA

V

CC

M24256
M24128

WC

SCL

V

SS

Table 1. Signal Names

SDA Serial Data/Address Input/

Output
SCL Serial Clock
WC

Write Control
V

CC

Supply Voltage
V

SS

Ground

PSDIP8 (BN)

0.25 mm frame

SO8 (MN)

150 mil width

8

1

8

1

SO8 (MW)

200 mil width

8

1

M24256, M24128

2/16

The memory behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, gene rated by the
bus master. The START condition is followed by a
Device Select Code and RW

bit (as described in

Table 3), terminated by an acknowledge bit.
When writing data to the memory, the mem ory in-

serts an acknowledge bit during the 9

th

bit time,

following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af­ter a NoAck for READ.

Power On Reset: V

CC

Lock-Out Write Protect

In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re­set (POR) circuit is included. The internal reset is

held active until the V

CC

voltage has reached the
POR threshold value, and all operations are dis­abled – the device will not respond to any com­mand. In the same way, when V

CC

drops from the
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any com ma nd. A s table a nd v alid V

CC

must be applied before applying any logic signal.

SIGNAL DESCRIPTION
Serial Clock (SCL)

The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slow­er clock, the master must have an open drain out­put, and a pull-up resistor must be connected from
the SCL line to V

CC

. (Figure 3 indicates how the
value of the pull-up res istor c an be calculated). In
most applications, though, this method of synchro­nization is not employed, and so the pull-up resis-

Figure 2A. DIP Connections

Note: 1. NC = Not Connected

SDAV

SS

SCL

WCNC

NC V

CC

NC

AI01883

M24256
M24128

1
2
3
4

8
7
6
5

Figure 2B. SO C on ne ct i on s

Note: 1. NC = Not Connected

1

AI01884

2

3

4

8
7
6
5

SDAV

SS

SCL

WCNC

NC V

CC

NC

M24256
M24128

Table 2. Absolute Maximum Ratings

1

Note: 1. Exc ept for the rating “Operating Temperature Ra nge”, stres ses above those listed in the Table “Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indi cated in t he Operating sect i ons of thi s specifi cation i s not impl i ed. Exposure to Absolute M aximum Rating c ondi­tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL -STD-883C, 3015.7 (1 00 pF, 1500 Ω)

Symbol Parameter Value Unit

T

A

Ambient Operating Temperature –40 to 125 °C

T

STG

Storage Temperature –65 to 150 °C

T

LEAD

Lead Temperature during Soldering

PSDIP8: 10 sec
SO8: 40 sec

260
215

°C

V

IO

Input or Output range –0.6 to 6.5 V

V

CC

Supply Voltage –0.3 to 6.5 V

V

ESD

Electrostatic Discharge Voltage (Human Body model)

2

4000 V

3/16

M24256, M24128

tor is not necessary, provided that the master has
a push-pull (rather than open drain) output.

Serial Data (SDA)

The SDA pin is bi-directional, and is used to trans­fer data in or out of the memory. It is an open drain

output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to V

CC

. (Figure 3 indicates how the value of the

pull-up resistor can be calculated).

Write Control (WC

)

The hardware Write Control pin (WC

) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC

=VIL) or disable (WC=VIH)
write instructions to the entire memory area. When
unconnected, the WC

input is internally read as

V

IL

, and write operations are allowed.

When WC

=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowl­edged.

Please see the Application Note

AN404

for a more

detailed description of the Write Control feature.

DEVICE OPERATION

The memory device supports the I

2

C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note

AN1001

. Any device that sends data on to the bus
is defined to be a transm itter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is k nown as the master,
and the other as the slave. A data transfer can only
be initiated by the mas ter, which wi ll also provide
the serial clock for synchronization. The memory

device is always a slave device in all comm unica­tion.

Start Condition

START is identified by a high t o low transition of
the SDA line while the clock, SCL, is s table i n t he
high state. A START condition must precede any
data transfer comman d. Th e m em ory devi ce con­tinuously monitors (except during a program ming
cycle) the SDA and SCL lines for a START condi­tion, and will not respond unless one is given.

Stop Condition

STOP is identified by a low to high transition of the
SDA line wh ile th e clock S CL is sta ble in the h igh
state. A STO P condition terminates c ommunica­tion between the memory device and the bus mas­ter. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the interna l EEPRO M write cycle.

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a suc­cessful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9

th

clock
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.

Data Input

During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transi­tion, and the data must change

only

when the SCL

line is low.

Figure 3. Maximum R

L

Value versus Bus Capacitance (C

BUS

) for an I2C Bus

AI01665

V

CC

C

BUS

SDA

R

L

MASTER

R

L

SCL

C

BUS

100

0

4

8

12

16

20

C

BUS

(pF)

Maximum RP value (kΩ)

10 1000

fc = 400kHz

fc = 100kHz

M24256, M24128

4/16

Memory Addressing

To start communication betwee n the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code i s fur­ther su bdi v i de d i n to : a 4 -b i t D e vi c e Type I d en t if i er ,

and a 3-bit Chip Enable “Address” (0, 0, 0).

To address the memory array, the 4-bit Device
Type Identifier is 1010b.

The 8

th

bit is th e RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Cod e, th e corresponding mem­ory gives an acknowledgment on the SDA bus dur­ing the 9

th

bit time. If the memo ry does n ot ma tch
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.

There are two modes both for read and write.
These are summarized in Table 4 and described

Figure 4. I

2

C Bus Protocol

SCL

SDA

SCL

SDA

SDA

START

CONDITION

SDA

INPUT

SDA

CHANGE

AI00792

STOP

CONDITION

1 23 789

MSB

ACK

START

CONDITION

SCL

1 23 789

MSB ACK

STOP

CONDITION

Table 3. Device Select Code

1

Note: 1. The most significant bit, b7, is sent firs t.

Device Type Identifier Chip Enable RW

b7 b6 b5 b4 b3 b2 b1 b0

Device Select Code 1 0 1 0 0 0 0 RW

5/16

M24256, M24128

later. A communication between the m aster and
the slave is ended with a STOP condition.

Each data byte in the m emory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta­ble 5) is sent first, f ollowed by the Least significant
Byte (Table 6). Bits b15 to b0 form t he addre ss of

the byte in memory. Bit b15 is t reated as a Don’t
Care bit on the M24256 memory. Bits b15 and b14
are treated as Don’t Care bits on the M24128
memory.

Table 4. Operating Modes

Note: 1. X = V

IH

or V

IL

.

Mode RW bit

WC

1

Data Bytes Initial Sequence

Current Address Read 1 X 1 START, Device Select, RW

= ‘1’

Random Address Read

0X

1

START, Device Select, RW

= ‘0’, Address

1 X reSTART, Device Select, RW

= ‘1’
Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read
Byte Write 0

V

IL

1 START, Device Select, RW = ‘0’

Page Write 0

V

IL

≤ 64 START, Device Select, RW = ‘0’

Figure 5. Wri te Mo de S e qu e nces with WC =1 (data wri te inhibi ted)

STOP

START

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

WC

START

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

WC

DATA IN 2

AI01120B

PAGE WRITE
(cont'd)

WC (cont'd)

STOP

DATA IN N

ACK ACK ACK NO ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK NO ACK

M24256, M24128

6/16

Figure 6. Wri te Mo de S e qu e nces with WC =0 (data wri te enab led)

STOP

START

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

WC

START

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

WC

DATA IN 2

AI01106B

PAGE WRITE
(cont'd)

WC (cont'd)

STOP

DATA IN N

ACK

R/W

ACK ACK ACK

ACK ACK ACK ACK

R/W

ACKACK

Write Operations

Following a START con dition the ma ster sends a
Device Select Code with the RW

bit set to ’0’, as
shown in Table 4. The memory acknowledges this,
and waits for two address bytes. The memory re­sponds to each address byte with an acknowledge
bit, and then waits for the data byte.

Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC

=1 (during a period of time from the START

condition until the end of the two address bytes)
will not modify the me mory c ontents, and t he ac­companying data bytes will

not

be acknowledged,

as shown in Figure 5.

Byte Write

In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed lo cation is write
protected by the WC

pin, the memory replies with
a NoAck, and the location is not modified. If, in­stead, the WC

pin has been held at 0, as shown in
Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a
STOP condition.

Page Write

The Page Write mode allows u p to 64 by tes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory add ress bits
(b14-b6 for the M24256 and b13-b6 for the
M24128) are the same. If more bytes are sent than

Table 5. Most Significant Byte

Note: 1. b15 is tr eated as Don’t Care on the M24256 series.

b15 and b14 ar e Don’t Care on t he M 24128 seri es.

Table 6. Least Significant Byte

b15 b14 b13 b12 b11 b10 b9 b8

b7 b6 b5 b4 b3 b2 b1 b0

7/16

M24256, M24128

During the internal write cycle, the SDA input is
disabled internally, and the device does not re­spond to any requests.

Minimizing System Delays by Polling On ACK

During the internal write cycle, the memory discon­nects itself from the bus, and copies the data from
its internal latches to the memory cells. The maxi­mum writ e time (t

w

) is shown in Table 10, but the
typical time is shorter. To make use of this, an Ack
polling sequence can be used by the master.

The sequence, as shown in Figure 7, is:

– Initial condition: a Write is in progress.
– Step 1: the m aster issues a START condition

followed by a Device Select Code (the first byte
of the new instruction).

– Step 2: if the memory is bus y with the internal

write cycle, no Ack will be returned and the mas­ter goes back to Step 1. If the memory has ter-

will fit up to t he en d of t he row, a condition known
as ‘roll-over’ occurs. Data starts to become over­written (in a way not formally specified in this data
sheet).

The master sends from one up to 64 bytes of data,
each of which is acknow ledged by the memory if
the W C

pin is low. If the WC pin is high, the con­tents of the addressed memory location are not
modified, and each data byte is followed by a
NoAck. After each byte i s tran sferred, the i nte rnal
byte address counter (the 6 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.

When the master generates a STOP condition im­mediately after the Ack bit (in the “10

th

bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not t rig­ger the internal write cycle.

Figure 7. Wri te Cy cle Pol l in g Fl owchart usin g A C K

WRITE Cycle

in Progress

AI01847

Next

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

NO

YESNO

ReSTART

STOP

Proceed

WRITE Operation

Proceed

Random Address

READ Operation

Send

Byte Address

First byte of instruction
with RW = 0 already
decoded by M24xxx

M24256, M24128

8/16

the Device Select Code, with the RW bit set to ‘1’.

The memory acknowledge s this, and outputs the
contents of the addressed byte. The master m ust

not

acknowledge the by te output, and terminates

the transfer with a STOP condition.

Current Address Read

The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read m ode, following a START
condition, the master sends a Device Select Code
with the RW

bit set to ‘1’. The memory acknowl­edges this, and outputs the byte addressed by the
internal address counter. The counter is then in-

minated the internal write cycle, it responds with
an Ack, indicating that the m emory is ready to
receive the second part of the nex t instruction
(the first byte of this instruction having been sent
during Step 1).

Read Operations

Read operations are performed independently of
the state of the WC

pin.

Random Address Read

A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then,

without

sending a STOP condition, the mas-

ter sends another START condi tion, and repeats

Figure 8. Read Mode Sequences

Note: 1. The seven most significan t bits of the Dev i ce Select Co de of a Random Read (in the 1st and 4th bytes) must b e i d entical.

START

DEV SEL * BYTE ADDR BYTE ADDR

START

DEV SEL DATA OUT 1

AI01105C

DATA OUT N

STOP

START

CURRENT
ADDRESS
READ

DEV SEL DATA OUT

RANDOM
ADDRESS
READ

STOP

START

DEV SEL * DATA OUT

SEQUENTIAL
CURRENT
READ

STOP

DATA OUT N

START

DEV SEL * BYTE ADDR BYTE ADDR

SEQUENTIAL
RANDOM
READ

START

DEV SEL * DATA OUT 1

STOP

ACK

R/W

NO ACK

ACK

R/W

ACK ACK ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK

ACK ACK ACK

R/W

ACK ACK

R/W

ACK NO ACK

9/16

M24256, M24128

Table 7. DC Characteristics

(T

A

= –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.5 to 5.5 V)

Table 8. Input Parameters

1

(TA = 25 °C, f = 400 kHz)

Note: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min. Max. Unit

I

LI

Input Leakage Current
(SCL, SDA)

0V ≤ V

IN

≤ V

CC

± 2 µA

I

LO

Output Leakage Current 0 V ≤ V

OUT

≤ V

CC,

SDA in Hi-Z ± 2 µA

I

CC

Supply Current

V

CC

=5V, fc=400kHz (rise/fall time < 30ns)

2mA

-W series:

V

CC

=2.5V, fc=400kHz (rise/fall time < 30ns)

1mA

I

CC1

Supply Current
(Stand-by)

V

IN

= VSS or V

CC

, V

CC

= 5 V

10 µA

-W series: V

IN

= VSS or V

CC

, V

CC

= 2.5 V 2 µA

V

IL

Input Low Voltage
(SCL, SDA)

–0.3

0.3V

CC

V

V

IH

Input High Voltage
(SCL, SDA)

0.7V

CC

VCC+1

V

V

IL

Input Low Voltage (WC) –0.3 0.5 V

V

IH

Input High Voltage (WC) 0.7V

CC

VCC+1 V

V

OL

Output Low
Voltage

I

OL

= 3 mA, VCC = 5 V

0.4 V

-W series:

I

OL

= 2.1 mA, VCC = 2.5 V

0.4 V

Symbol Parameter Test Condition Min. Max. Unit

C

IN

Input Capacitance (SDA) 8 pF

C

IN

Input Capacitance (other pins) 6 pF

Z

L

Input Impedance (WC)

V

IN

≤ 0.5 V

5kΩ

Z

H

Input Impedance (WC)V

IN

≥ 0.7V

CC

500 kΩ

t

NS

Low Pass Filter Input Time
Constant (SCL and SDA)

100 ns

Table 9. AC Measurement Conditions

Input Rise and Fall Times ≤ 50 ns
Input Pulse Voltages

0.2V

CC

to 0.8V

CC

Input and Output Timing
Reference Voltages

0.3V

CC

to 0.7V

CC

Figure 9. AC Testing Input Output Waveforms

AI00825

0.8V

CC

0.2V

CC

0.7V

CC

0.3V

CC

M24256, M24128

10/16

Table 10. AC Characteristics

Note: 1. For a r eS T ART condi tion, or following a writ e cy cl e.

2. Samp l ed only, not 100% tes ted.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

Symbol Alt. Parameter

M24256 / M24128

Unit

V

CC

=4.5 to 5.5 V

T

A

=–40 to 85°C

V

CC

=2.5 to 5.5 V

T

A

=–40 to 85°C

MinMaxMinMax

t

CH1CH2

t

R

Clock Rise Time 300 300 ns

t

CL1CL2

t

F

Clock Fall Time 300 300 ns

t

DH1DH2

2

t

R

SDA Rise Time 20 300 20 300 ns

t

DL1DL2

2

t

F

SDA Fall Time 20 300 20 300 ns

t

CHDX

1

t

SU:STA

Clock High to Input Transition 600 600 ns

t

CHCL

t

HIGH

Clock Pulse Width High 600 600 ns

t

DLCL

t

HD:STA

Input Low to Clock Low (START) 600 600 ns

t

CLDX

t

HD:DAT

Clock Low to Input Transition 0 0 µs

t

CLCH

t

LOW

Clock Pulse Width Low 1.3 1.3 µs

t

DXCX

t

SU:DAT

Input Transition to Clock Transition 100 100 ns

t

CHDH

t

SU:STO

Clock High to Input High (STOP) 600 600 ns

t

DHDL

t

BUF

Input High to Input Low (Bus Free) 1.3 1.3 µs

t

CLQV

3

t

AA

Clock Low to Data Out Valid 200 900 200 900 ns

t

CLQX

t

DH

Data Out Hold Time After Clock Low 200 200 ns

f

C

f

SCL

Clock Frequency 400 400 kHz

t

W

t

WR

Write Time 10 10 ms

cremented. The master terminates the transfer
with a STOP condition, as shown in Figure 8,

with-

out

acknowledging the byte output.

Sequenti a l Rea d

This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master

does

acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must

not

acknowledge the last

byte output, and

must

generate a STOP condition.

The output data comes from consecutive address­es, with the internal address counter automatically
incremented after each byte output. After the last

memory address, the address coun ter ‘rolls-over’
and the memory continues to output data from
memory address 00h.

Acknowledge in Read Mode

In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9

th

bit time. If the master does n ot pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.

11/16

M24256, M24128

Figure 10. AC Waveforms

SCL

SDA IN

SCL

SDA OUT

SCL

SDA IN

tCHCL

tDLCL

tCHDX

START

CONDITION

tCLCH

tDXCX

tCLDX

SDA

INPUT

SDA

CHANGE

tCHDH

tDHDL

STOP &

BUS FREE

DATA VALID

tCLQV tCLQX

DATA OUTPUT

tCHDH

STOP

CONDITION

tCHDX

START

CONDITION

WRITE CYCLE

tW

AI00795B

M24256, M24128

12/16

Table 11. Ordering Information Scheme

Note: 1. Available only on request.

2. Avail able for M24 128 only.

3. Avail able for M24 256 only.

Example: M24256 – W MN 1 T

Memory Capacity Option

256 256 Kbit (32K x 8) T Tape and Reel Packing
128

128 Kbit (16K x 8)

Temperature Range

6 –40 °C to 85 °C
5 –20 °C to 85 °C

Operating Voltage

blank

1

4.5 V to 5.5 V Package

W 2.5 V to 5.5 V BN PSDIP8 (0.25 mm frame)

MN

2

SO8 (150 mil width)

MW

3

SO8 (200 mil width)

ORDERING INFORMATION

Devices are shipped from the factory with the

memory content set at all ‘1’s (FFh).
The notation used for the device number is as

shown in Table 11. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.

13/16

M24256, M24128

Figure 11. PSDIP8 (BN)

Note: 1. D rawing is not to scale.

PSDIP-a

A2

A1AL

e1

D

E1 E

N

1

C

eA
eB

B1

B

Table 12. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 3.90 5.90 0.154 0.232

A1 0.49 – 0.019 –

A2 3.30 5.30 0.130 0.209

B 0.36 0.56 0.014 0.022

B1 1.15 1.65 0.045 0.065

C 0.20 0.36 0.0 08 0.014
D 9.20 9.90 0.3 62 0.390
E 7.62 – – 0.300 – –

E1 6.00 6.70 0.236 0.264

e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB 10.00 0.394

L 3 .00 3.80 0.118 0.150

N8 8

M24256, M24128

14/16

Table 13. SO8 - 8 lead Plastic Small Outline, 150 mils body width

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.0 07 0.010
D 4.80 5.00 0.1 89 0.197
E 3.80 4.00 0.150 0.157

e 1.27 – – 0.050 – –

H 5.80 6.20 0.2 28 0.244

h 0 .25 0.50 0.010 0.020

L 0 .40 0.90 0.016 0.035
α 0° 8° 0° 8°
N8 8

CP 0.10 0.004

Figure 12. SO8 narrow (MN)

Note: 1. D rawing is not to scale.

SO-a

E

N

CP

B

e

A

D

C

LA1 α

1

H

h x 45˚

15/16

M24256, M24128

Table 14. SO8 - 8 lead Plastic Small Outline, 200 mils body width

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 2.03 0.080

A1 0.10 0.25 0.004 0.010
A2 1.78 0.070

B 0.35 0.45 0.014 0.018
C 0.20 – – 0.008 – –

D 5.15 5.35 0.2 03 0.211
E 5.20 5.40 0.205 0.213

e 1.27 – – 0.050 – –
H 7.70 8.10 0.3 03 0.319

L 0 .50 0.80 0.020 0.031
α 0° 10° 0° 10°
N8 8

CP 0.10 0.004

Figure 13. SO8 wide (MW)

Note: 1. D rawing is not to scale.

SO-b

E

N

CP

B

e

A2

D

C

LA1 α

H

A

1

M24256, M24128

16/16

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