SGS Thomson Microelectronics M24256-WBN6, M24256-W, M24256-MW6, M24256-BN6, M24256 Datasheet
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PRELIMINARY DATA
November 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M24256
M24128
256/128 Kbit Serial I²C Bus EEPROM
Without Chip Enable Lines
■ Compat ible with I
2
C Extended Addressing
■ Two Wire I
2
C Serial Interface
Supports 400 kHz Protocol
■ Single Supply Voltage:
– 4.5V to 5.5V for M24xxx
– 2.5V to 5.5V for M24xxx-W
■ Hardware Write Control
■ BYTE and PAGE WRITE (up to 64 Bytes)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Tim e d P ro g r amming Cycle
■ Automatic Address Incrementing
■ Enhanced ESD/Latch-Up Behavior
■ 100,000 Erase/Write Cycles (minimum)
■ 40 Year Data Retention (minimum)
DESCRIPTION
These I
2
C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 32Kx8 bits (M24256) and 16Kx8 bits
(M24128), and operate down to 2.5 V (for the -W
version of each device).
The M24256 and M 24128 are available in Plastic
Dual-in-Line and Plastic Small Outline packages.
These memory devices are compatible with the
I
2
C extended memory standard. This is a two wire
serial interface that uses a bi-directiona l data bus
and serial clock. The memory carries a built-in 4bit unique Device Type Identifier code (1010) in
accordance with the I
2
C bus definition.
Figure 1. Logic Diagram
AI01882
SDA
V
CC
M24256
M24128
WC
SCL
V
SS
Table 1. Signal Names
SDA Serial Data/Address Input/
Output
SCL Serial Clock
WC
Write Control
V
CC
Supply Voltage
V
SS
Ground
PSDIP8 (BN)
0.25 mm frame
SO8 (MN)
150 mil width
8
1
8
1
SO8 (MW)
200 mil width
8
1
M24256, M24128
2/16
The memory behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, gene rated by the
bus master. The START condition is followed by a
Device Select Code and RW
bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the mem ory in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and after a NoAck for READ.
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Reset (POR) circuit is included. The internal reset is
held active until the V
CC
voltage has reached the
POR threshold value, and all operations are disabled – the device will not respond to any command. In the same way, when V
CC
drops from the
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any com ma nd. A s table a nd v alid V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slower clock, the master must have an open drain output, and a pull-up resistor must be connected from
the SCL line to V
CC
. (Figure 3 indicates how the
value of the pull-up res istor c an be calculated). In
most applications, though, this method of synchronization is not employed, and so the pull-up resis-
Figure 2A. DIP Connections
Note: 1. NC = Not Connected
SDAV
SS
SCL
WCNC
NC V
CC
NC
AI01883
M24256
M24128
1
2
3
4
8
7
6
5
Figure 2B. SO C on ne ct i on s
Note: 1. NC = Not Connected
1
AI01884
2
3
4
8
7
6
5
SDAV
SS
SCL
WCNC
NC V
CC
NC
M24256
M24128
Table 2. Absolute Maximum Ratings
1
Note: 1. Exc ept for the rating “Operating Temperature Ra nge”, stres ses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indi cated in t he Operating sect i ons of thi s specifi cation i s not impl i ed. Exposure to Absolute M aximum Rating c onditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL -STD-883C, 3015.7 (1 00 pF, 1500 Ω)
Symbol Parameter Value Unit
T
A
Ambient Operating Temperature –40 to 125 °C
T
STG
Storage Temperature –65 to 150 °C
T
LEAD
Lead Temperature during Soldering
PSDIP8: 10 sec
SO8: 40 sec
260
215
°C
V
IO
Input or Output range –0.6 to 6.5 V
V
CC
Supply Voltage –0.3 to 6.5 V
V
ESD
Electrostatic Discharge Voltage (Human Body model)
2
4000 V
3/16
M24256, M24128
tor is not necessary, provided that the master has
a push-pull (rather than open drain) output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to transfer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to V
CC
. (Figure 3 indicates how the value of the
pull-up resistor can be calculated).
Write Control (WC
)
The hardware Write Control pin (WC
) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC
=VIL) or disable (WC=VIH)
write instructions to the entire memory area. When
unconnected, the WC
input is internally read as
V
IL
, and write operations are allowed.
When WC
=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowledged.
Please see the Application Note
AN404
for a more
detailed description of the Write Control feature.
DEVICE OPERATION
The memory device supports the I
2
C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001
. Any device that sends data on to the bus
is defined to be a transm itter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is k nown as the master,
and the other as the slave. A data transfer can only
be initiated by the mas ter, which wi ll also provide
the serial clock for synchronization. The memory
device is always a slave device in all comm unication.
Start Condition
START is identified by a high t o low transition of
the SDA line while the clock, SCL, is s table i n t he
high state. A START condition must precede any
data transfer comman d. Th e m em ory devi ce continuously monitors (except during a program ming
cycle) the SDA and SCL lines for a START condition, and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line wh ile th e clock S CL is sta ble in the h igh
state. A STO P condition terminates c ommunication between the memory device and the bus master. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the interna l EEPRO M write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a successful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9
th
clock
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transition, and the data must change
only
when the SCL
line is low.
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I2C Bus
AI01665
V
CC
C
BUS
SDA
R
L
MASTER
R
L
SCL
C
BUS
100
0
4
8
12
16
20
C
BUS
(pF)
Maximum RP value (kΩ)
10 1000
fc = 400kHz
fc = 100kHz
M24256, M24128
4/16
Memory Addressing
To start communication betwee n the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code i s further su bdi v i de d i n to : a 4 -b i t D e vi c e Type I d en t if i er ,
and a 3-bit Chip Enable “Address” (0, 0, 0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
The 8
th
bit is th e RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Cod e, th e corresponding memory gives an acknowledgment on the SDA bus during the 9
th
bit time. If the memo ry does n ot ma tch
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
There are two modes both for read and write.
These are summarized in Table 4 and described
Figure 4. I
2
C Bus Protocol
SCL
SDA
SCL
SDA
SDA
START
CONDITION
SDA
INPUT
SDA
CHANGE
AI00792
STOP
CONDITION
1 23 789
MSB
ACK
START
CONDITION
SCL
1 23 789
MSB ACK
STOP
CONDITION
Table 3. Device Select Code
1
Note: 1. The most significant bit, b7, is sent firs t.
Device Type Identifier Chip Enable RW
b7 b6 b5 b4 b3 b2 b1 b0
Device Select Code 1 0 1 0 0 0 0 RW
5/16
M24256, M24128
later. A communication between the m aster and
the slave is ended with a STOP condition.
Each data byte in the m emory has a 16-bit (two
byte wide) address. The Most Significant Byte (Table 5) is sent first, f ollowed by the Least significant
Byte (Table 6). Bits b15 to b0 form t he addre ss of
the byte in memory. Bit b15 is t reated as a Don’t
Care bit on the M24256 memory. Bits b15 and b14
are treated as Don’t Care bits on the M24128
memory.
Table 4. Operating Modes
Note: 1. X = V
IH
or V
IL
.
Mode RW bit
WC
1
Data Bytes Initial Sequence
Current Address Read 1 X 1 START, Device Select, RW
= ‘1’
Random Address Read
0X
1
START, Device Select, RW
= ‘0’, Address
1 X reSTART, Device Select, RW
= ‘1’
Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read
Byte Write 0
V
IL
1 START, Device Select, RW = ‘0’
Page Write 0
V
IL
≤ 64 START, Device Select, RW = ‘0’
Figure 5. Wri te Mo de S e qu e nces with WC =1 (data wri te inhibi ted)
STOP
START
BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN
WC
START
PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1
WC
DATA IN 2
AI01120B
PAGE WRITE
(cont'd)
WC (cont'd)
STOP
DATA IN N
ACK ACK ACK NO ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK NO ACK
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