SGS Thomson Microelectronics M14256, M14128 Datasheet

M14256
M14128

Memory Card IC

256/128 Kbit Serial I²C Bus EEPROM

PRELIMINARY DATA

■ Compat ible with I

■ Two Wire I

2

C Extended Addressing

2

C Serial Interface

Supports 400 kHz Protocol

■ Single Supply Voltage (2.5 V to 5.5 V)

■ Hardware Write Control

■ BYTE and PAGE WRITE (up to 64 Bytes)

■ BYTE, RANDOM and SEQUENTIAL READ

Modes

■ Self-Tim e d P ro g r amming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behaviour

■ 100,000 Erase/Write Cycles (minimum)

■ 40 Year Data Retention (minimum)

■ 5 ms Programming Time (typical)

DESCRIPTION

Each device is an electrically erasable program ­mable memory (EEPROM) fabricated with STMi-

croelectronics’s High Endurance, Double
Polysilicon, CMOS technology. This guarantees
an endurance typically well above 100,000 Erase/
Write cycles, with a data retention of 40 years. The
memory operates with a powe r supply as low as

2.5 V.
The M14256 and M 14128 are avail able in micro-

module form only. For availability of the M14256 or

Micromodule (D22)

Figure 1. Logic Diag ram

V

CC

Table 1. Signal Names

SDA Serial Data/Address Input/

Output
SCL Serial Clock
WC
V

CC

GND Ground

October 1999

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Write Control

Supply Voltage

SCL

M14xxxWC

GND

SDA

AI02217

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M14256, M14128

Figure 2. D22 Contact Connections

V

CC

WC

SCL

GND

SDA

AI02204

M14128 in wafer form, please contact your ST
sales office.

Each memory device is compatible with the I

2

extended memory standard. This is a two wire se­rial interface that uses a bi-directional data bus
and serial clock. The memory device carries a
built-in 7-bit unique Device Type Identifier code
(1010000) in accordance with the I
tion. Only one memory de vice can be attached to

2

each I
The memory device behaves as a slave dev ice in

the I

C bus.

2

C protocol, with all memory operations syn-

2

C bus d efini-

chronized by the serial clock. Read and write op­erations are initiated by a START condition,
generated by the bus master. T he START condi­tion is followed by the Device Select Code which is
composed of a stream of 7 bits (1010000), plus
one read/write bit (R/W

) and is terminated by an

acknowledge bit.

When writing data to the m emory, the memory de­vice inserts an acknowledge bit during the 9

time, following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af­ter a NoACK for READ.

Power On Reset: V

Lock-Out Write Protect

CC

In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re­set (POR) circuit is included. The internal reset is
held active until the V

voltage has reached the

CC

POR threshold value, and all operations are dis­abled – the device will not respond to any com­mand. In the same way, when V

drops from the

CC

operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any com ma nd. A s table a nd v alid V
must be applied before applying any logic signal.

C

SIGNAL DESCRIPTION
Serial Clock (SCL)

The SCL input pin is used to synchronize a ll data
in and out of the memory. A pull up resistor can be
connected from the SCL line to V

CC

dicates how the value of the pull-up resistor can be
calculated).

Serial Data (SDA)

The SDA pin is bi-directional, and is used to trans­fer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to V

. (Figure 3 indicates how the value of the

CC

pull-up resistor can be calculated).

th

bit

CC

. (Figure 3 in-

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

STG

V

IO

V

CC

V

ESD

Note: 1. Exc ept for the rating “Operating Temperature Ra nge”, stres ses above those listed in the Table “Absolute Maximum Ratings” may

2/12

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indi cated in t he Operating sect i ons of thi s specifi cation i s not impl i ed. Exposure to Absolute M aximum Rating c ondi­tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL -STD-883C, 3015.7 (1 00 pF, 1500 Ω)

3. EIA J I C-121 (Condition C) (200 pF, 0 Ω)

Ambient Operating Temperature 0 to 70 °C
Storage Temperature -40 to 120 °C
Input or Output range -0.6 to 6.5 V
Supply Voltage -0.3 to 6.5 V

Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)

1

2

3

4000 V

400 V

M14256, M14128

Write Control (WC)

The hardware Write Control contact (WC

) is useful
for protecting the entire contents of the memory
from inadvertent erase/write. The Write Control
signal is used to enable (WC
(WC

=VIH) write instructions to the entire memory
area. When unconnected, the WC
ly read as V

When WC

and write operations are allowed.

IL

=1, Device Select and Address bytes

=VIL) or disable

input is internal-

are acknowledged, Data bytes are not acknowl­edged.

Please see the Application Note

AN404

for a more

detailed description of the Write Control feature.

DEVICE OPERATION

2

The memory device supports the XI

2

C) protocol, as summarized in Figure 4. Any de-

I

C (Extended

vice that sends data on to the bus is defined to be
a transmitter, and any dev ice that reads the dat a
to be a receiver. The device that controls the data
transfer is known as the master, and the other as
the slave. A data transfer can o nly be initiated by
the master, which will also provide the serial clock
for synchronization. The memory device is always
a slave device in all communication.

Start Condition

START is identified by a high t o low transition of
the SDA line while the clock, SCL, is s table i n t he
high state. A START condition must precede any
data transfer comman d. Th e m em ory devi ce con­tinuously monitors (except during a program ming
cycle) the SDA and SCL lines for a START condi­tion, and will not respond unless one is given.

Stop Condition

STOP is identified by a low to high transition of the
SDA line while the clock, SCL, is stable in the high

state. A STO P condition terminates c ommunica­tion between the memory device and the bus mas­ter. A STOP condition at the end of a Read
command, after (and only after) a NoACK , forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a suc­cessful data transfer. The bus transmitter, either
master or slave, will release the SDA bus after
sending 8 bits of data. During t he 9

th

clock pulse
period the receiver pulls the SDA bus low to ac­knowledge the receipt of the 8 data bits.

Data Input

During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transi-

only

tion, and the data must change

when the SCL

line is low.

Memory Addressing

To start communication betwee n the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
8 bits to the SDA bus line (with the most significant
bit first). These bits represent the Device Select
Code (7 bits) and a RW

bit.

The seven most s ignificant bits of the Device Se­lect Code are the Device Type Identifier, according
to the I

2

C bus definition. For the mem ory device,
the seven bits are fixed at 1010000b (A0h), as
shown in Table 5.

th

The 8

bit is the read or write bit (RW). This bit is

set to ‘1’ for read and ‘0’ for write operations. If a
match occurs on the Device Select Code, the cor-

Figure 3. Maximum R

20

16

12

8

Maximum RP value (kΩ)

4

0

10 1000

Value versus Bus Capacitance (C

L

fc = 100kHz

fc = 400kHz

100

C

(pF)

BUS

) for an I2C Bus

BUS

V

MASTER

CC

SDA

SCL

R

R

C

BUS

L

C

BUS

AI01665

3/12

L

M14256, M14128

2

Figure 4. I

C Bus Protocol

SCL

SDA

SCL

SDA

SCL

SDA

START

CONDITION

START

CONDITION

SDA

INPUT

1 23 789

MSB

1 23 789

MSB ACK

SDA

CHANGE

CONDITION

ACK

STOP

STOP

CONDITION

AI00792

responding memory gives an acknowledgment on
the SDA bus during the 9
does not match the Device Select code, it will de­select itself from the bus, and go into stand-by
mode.

Each data byte in the m emory has a 16-bit (two

th

bit time. If the memory

Table 3. Most Significant Byte

b15 b14 b13 b12 b11 b10 b9 b8

Note: 1. b15 is Don’t Care on the M14256 series.

b15 and b14 ar e Don’t Care on t he M 14128 seri es.

byte wide) address. The Most Significant Byte (Ta­ble 3) is sent first, f ollowed by the Least significant
Byte (Table 4). Bits b15 to b0 form t he addre ss of

the byte in memory. Bit b15 is t reated as a Don’t

Table 4. Least Significant Byte

b7 b6 b5 b4 b3 b2 b1 b0

Care bit on the M14256 memory. Bits b15 and b14
are treated as Don’t Care bits on the M14128
memory.

Table 5. Device Select Code

b7 b6 b5 b4 b3 b2 b1 b0

Device Select 1010000RW

Note: 1. The most significant bit, b7, is sent firs t.

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1

Device Code Chip Enable RW