SGS Thomson Microelectronics EF6805U3 Datasheet

8-BIT MICROCOMPUTER UNIT

HARDWAR E FEATU RES DESCRIPTI O N

.32 TTL/CMOSCOMPATIBLE I/O LINES

.24 BIDIRECTIONAL (8 lines are LED compati-

ble)

.8 INPUT-ONLY

.3776 BYTES OF USER ROM

.112 BYTES OF RAM

.SELF-CHECK MODE

.ZERO-CROSSINGDETECT/INTERRUPT

.INTERNAL 8-BIT TIMER WITH 7-BIT SOFT-

WARE PROGRAMMABLE PRESCALER AND
CLOCKSOURCE

The EF6805U3 Microcomputer Unit (MCU) is a
member of the 6805 Family of low-costsingle-chip
Microcomputers. The 8-bit microcomputer contains
a CPU, on-chip CLOCK, ROM, RAM, I/O, and TI­MER.It is designed for the userwho needs an eco­nomical microcomputer withtheproven capabilities
of the 6800-based instruction set. A comparison of
thekey featuresofseveral members ofthe 6805Fa­mily of Microcomputers is shown at the end of this
data sheet.The following are someof the hardware
and softwarehighlights of the EF6805U3 MCU.

.5V SINGLE SUPPLY

SOFTWARE FEATURES

.10 POWERFUL ADDRESSINGMODES

.BYTE EFFICIENT INSTRUCTION SET WITH

TRUE BIT MANIPULATION, BIT TEST, AND
BRANCHINSTRUCTIONS

.SINGLE INSTRUCTION MEMORY EXA-

MINE/CHANGE

.POWERFUL INDEXED ADDRESSING FOR

TABLES

.FULL SET OF CONDITIONALBRANCHES

.MEMORYUSABLE AS REGISTER/FLAGS

.COMPLETE DEVELOPMENT SYSTEM SUP-

PORTON INICE

USER SELECTAB LE OPTIONS

PIN CONNECTIONS

.8 BIDIRECTIONAL I/O LINES WITH TTL OR

TTL/CMOSINTERFACE OPTION

.8 BIDIRECTIONALI/O LINES WITHTTL ORO-

PEN-DRAIN INTERFACEOPTION

.CRYSTALOR LOW-COST RESISTOR OSCIL-

LATOROPTION

.LOWVOLTAGE INHIBIT OPTION

.VECTORED INTERRUPTS : TIMER, SOFT-

WARE, AND EXTERNAL

.USER CALLABLE SELF-CHECK SUBROU-

TINES

EF6805U3

1

P

(PDIP40)

FN

(PLCC44)

March1989

1/31

EF6805U3

Figure 1 : EF6805U3 HMOS Microcomputer BlockDiagram.

ABSOLUTEMAXIMUM RATINGS

Symbol Parameter Value Unit

V

CC

V

in

Supply Voltage – 0.3 to + 7.0 V
Input Voltage (except TIMER in self-check mode and

– 0.3 to + 7.0 V

open-drain inputs)

V

in

T

A

T

stg

T

This device contains circuitry to protect the inputs against damage due to high static voltages or electrical fields, however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
For proper operation it is recommended that Vinand V
hanced if unused inputs except EXTAL are tied to an appropriate logic voltage level (e.g., either VSSor VCC).

Input Voltage (open-drain pins, TIMER pin in self-check mode) – 0.3 to + 15.0 V
Operating Temperature Range

(T

to TH)

L

VSuffix
TSuffix

0to+70

–40to+85

– 40 to + 105
Storage Temperature Range – 55 to + 150 °C
Junction Temperature

j

Plastic Package
PLCC

be constrained to the range VSS(Vinor V

out

150
150

. Reliability of operation is en-

out)VCC

°C

°C

THERMALDATA

θ

JA

Thermal Resistance

Plastic
PLCC

50
80

°C/W

2/31

EF6805U3

POW ER CO NSIDE R ATIONS

Theaverage chip-junctiontemperature,TJ, inCcan
be obtainedfrom :
TJ=TA+(PD.JA) (1)
Where :
TA= AmbientTemperature, C
JA=Package ThermalResistance,Junction-to-Am­bient,C/W
PD=P

INT+PPORT

P

INT=ICCxVCC

P

= Port Power Dissipation, Watts - User De-

PORT

, Watts - Chip Internal Power

termined
For most applications P

glected. P

maybecomesignificant if thedevice

PORT

PORTPINT

and can be ne-

is configured to drive Darlington bases or sink LED
loads.

An approximate relationship between PDandTJ(if
P

is neglected) is :

PORT

PD=K+(TJ+273C) (2)
Solving equations 1 and2 forK gives :
K=PD.(TA+273C) + JA.P

2

(3)

D

Where K is a constant pertaining to the particular
part.K can be determined from equation 3 bymea­suring PD(atequilibrium) for a known TA. Usingthis
valueof K the values of PDandTJcanbe obtained
by solving equations (1) and (2) iteratively for any
valueof TA.

ELECTRICAL CHARACTERISTICS(VCC= + 5.25Vdc ± 0.5Vdc, VSS= 0Vdc, TA=TLto THunless
otherwise noted)

Symbol Parameter Min. Typ. Max. Unit

V

IH

V

IH

V

IL

V

IRES +

V

IRES –

V

INT

P

D

C

in

V

LVR

VL

I

in

* Due to internal biasing this input (when unused) floats to approximately 2.2V.

Input High Voltage

RESET (4.75 ≤ V

(VCC< 4.75)

INT (4.75 ≤ V

(VCC< 4.75)

All Other (except timer)

CC

≤ 5.75)

CC

≤ 5.75)

4.0
– 0.5

V

CC

4.0

V

– 0.5

CC

•

•

2.0

Input High Voltage Timer

Timer Mode
Self-check Mode

2.0

9.0 10.0

Input Low Voltage

RESET
INT
All Other

V

SS

V

SS

V

SS

•

RESET Hystereris Voltages (see figures 10, 11 and 12)

”Out of Reset”
”Into Reset”

INT Zero Crossing Input Voltage, Through a

2.1

0.8

24V

Capacitor
Power Dissipation - (no port loading, VCC= 5.75V)

TA=0°C

TA=–40°C

520
580

Input Capacitance

EXTAL
All Other

25

10
Low Voltage Recover 4.75 V
Low Voltage Inhibit 2.75 3.75 4.70 V

VI

Input Current

TIMER (V
INT (Vin= 2.4V to VCC)
EXTAL (V

= 0.4V)

in

= 2.4V to VCC- crystal option)

in

20

(Vin= 0.4V - crystal option)

RESET (Vin= 0.8V) - External Capacitor Charging

– 40.0

Current

V
V
V
V
V

V

CC

15.0

0.8

1.5

0.8

4.0

2.0

740
800

20
50
10

– 1600

–40

CC
CC
CC
CC
CC

+ 1.0

V

V

V

V

ac p-p

mW

pF

µA

3/31

EF6805U3

SWITCHING CHARACTERISTICS

(VCC= + 5.25Vdc ± 0.5Vdc, VSS= 0Vdc, TA=TLto THunless otherwise noted)

Symbol Parameter Min. Typ. Max. Unit

f

osc

t

cyc

t

WL,tWH

t

RWL

f

INT

PORT ELECTRICAL CHARACTERISTICS

(VCC= + 5.25Vdc ± 0.5Vdc, VSS= 0Vdc, TA=TLto THunless otherwise noted)
PORT A WITH CMOS DRIVEENABLED

Symbol Parameter Min. Typ. Max. Unit

V

OL

V

OH

V

IH

V

IL

I

IH

I

IL

Oscillator Frequency 0.4 4.2 MHz
Cycle Time (4/f
INT, INT2, and TIMER Pulse Width (see interrupt

) 0.95 10 µs

osc

t

+ 250 ns

cyc

section)
RESET Pulse Width t

+ 250 ns

cyc

INT Zero-crossing Detection Input Frequency 0.03 1 kHz
External Clock Input Duty Cycle (EXTAL) 40 50 60 %
Crystal Oscillator Start-up Time* 100 ms

Output Low Voltage (I

= 1.6mA) 0.4 V

Load

Output High Voltage

I

= – 100µ A

Load

I

=– 10µA

Load

Input High Voltage (I
Input Low Voltage (I

= – 300µA max.) 2.0 V

Loa d

= – 500µA max.) V

Load

2.4

VCC– 1.0

SS

CC

0.8 V
High Z State Input Current (Vin= 2.0V to VCC) – 300 µA
High Z State Input Current (Vin= 0.4V) – 500 µA

V

V

PORT B

Symbol Parameter Min. Typ. Max. Unit

V

OL

V

OH

I

OH

V

IH

V

IL

I

TSI

Output Low Voltage

I

= 3.2mA

Loa d

I

= 10mA (sink)

Loa d

Output High Voltage I

=– 200µA 2.4 V

Load

0.4

1.0

Darlington Current Drive (source) VO= 1.5V – 1.0 – 10 mA
Input High Voltage 2.0 V
Input Low Voltage V

SS

CC

0.8 V
High Z State Input Current < 2 10 µA

PORT C AND PORT A WITH CMOS DRIVE DISABLED

Symbol Parameter Min. Typ. Max. Unit

V

OL

V

OH

V

IH

V

IL

I

TSI

Output Low Voltage I
Output High Voltage I
Input High Voltage 2.0 V
Input Low Voltage V

= 1.6mA 0.4 V

Load

= – 100µA 2.4 V

Load

CC

SS

0.8 V
High Z State Input Current < 2 10 µs

V

V

V

4/31

EF6805U3

Figure 2 : TTL Equivalent Test Load (port B). Figure3 :CMOS Equivalent Test Load (port A).

Figure 4 : TTL Equivalent Test Load (port A

andC).

SIGNAL DESCRIPTION

The input and output signals for theMCU,shown in
figure 1, are described in the following paragraphs.

VCCANDVSS-Power is supplied to the MCU using
thesetwopins. VCCispower and VSSis the ground
connection.

INT - This pin provides the capability for asynchro­nously applying an external interrupt to the MCU.
Refer to Interrupts Section for additional informa­tion.

XTALAND EXTAL - These pins provide controlin­put for theon-chip clockoscillator circuit. A crystal,
a resistor, or an external signal, depending on user
selectable manufacturing mask option, can be
connected to these pins to provide a system clock
withvariousdegreesof stability/costtradeoffs.Lead

Figure 5 : Open-drain Equivalent Test Load (port
C).

length and stray capacitance on these two pins
should be minimized. Refer to InternalClock Gen­erator Options Section for recommendations about
these inputs.

NOTE : Pin 7 in DIL package/pin 8 in PLCC
package is connected to internal protection.

TIMER- The pinallowsan externalinputto be used
to control the internal timer circuitry and also to ini­tiatetheselftestprogram. Referto TimerSection for
additional information about the timer circuitry.

RESET - This pin allows resetting of the MCU at
times other than the automatic resetting capability
already in the MCU. The MCUcan be resetby pul­ling RESET low. Refer to Resets Section for addi­tionalinformation.

5/31

EF6805U3

INPUT/OUTPUTLINES(PA0-PA7, PB0-PB7,PC0­PC7, PD0-PD7) - These32 liens arearranged into
four 8-bit ports (A, B, C, and D). Ports A, B, and C
areprogrammable as eitherinputs oroutputs under
software control of the data direction registers
(DDRs).Port D is for digital input only and bit 6 may
be used for a second interrupt INT2. Refer to In­put/OutputSectionand Interrupts Section for addi­tional information.

MEMORY-TheMCUiscapable ofaddressing4096
bytes of memory and I/O registers with its program
counter. The EF6805U3 MCU has implemented
4090 of these bytes. This consists of : 3776 user
ROM bytes, 192 self-check ROM bytes, 112 user
RAM bytes, 7 portI/O bytes, 2 timerregisters, and
a miscellaneous register ; see figure 6 for the Ad­dress map. The user ROM has been split into two
areas. The main user ROM area is from $080 to
$F37. The last 8 userROM locationsat the bottom
of memory are for the interrupt vectors.

Figure 6 : EF6805U3 MCU Address Map.

TheMCUreservesthefirst-16memorylocationsfor
I/O features, of which 10 have been implemented.
These locations are used for the ports, the port
DDRs,the timer and the INT2miscellaneous regis­ter, and the 112 RAM bytes, 31 bytes are shared
with the stack area. The stack must be used with
carewhen data shares thestack area.
Thesharedstackareaisusedduringtheprocessing
of an interrupt or subroutine calls to save the
contents of the CPUstate. The register contents are
pushed onto the stack in the order shown in figure

7. Since the stack pointer decrements during
pushes, the low order byte (PCL) of the program
counter is stackedfirst, then the high order fourbits
(PCH)are stacked.This ensures that the program
counter is loaded correctly during pulls from the
stack since the stack pointer increments when it
pulls data from the stack. A subroutine call results
in only the program counter (PCL, PCH) contents
beingpushed onto thestack ;theremaining CPUre­gistersare not pushed.

* Caution : Data direction registers (DDRs) are write only, they read as $FF.

6/31

EF6805U3

Figure 6 : Interrupt Stacking Order.

CENTRAL P ROC ESSIN G U NI T

The CPU of theEF6805 Family is implemented in­dependently from the I/O or memory configuration.

Figure 8 : Programming Model.

Consequently, it can be treated as an independent
central processor communicating with I/O and me­mory via internal address, data, and control buses.

REGISTERS

The 6805 FamilyCPUhasfiveregistersavailable to
the programmer. Theyareshowninfigure8 andare
explained in the following paragraphs.

ACCUMULATOR(A)-Theaccumulatoris ageneral
purpose 8-bitregisterusedto holdoperandsandre­sults of arithmetic calculations or data manupula­tions.

INDEX REGISTER(X) - The index register is an 8­bit register usedfor the indexed addressing mode.
It contains an 6-bit value that may be added to an
instruction value tocreate aneffectiveaddress. The
indexregister can also be used for data manipula­tions using the read-modify-write instructions. The
Index Register may also be used as a temporary
storagearea.

PROGRAMCOUNTER (PC) - The Program Coun­ter is a 12 bit registerthat contains th address of the
next instructionto be executed.

STACK POINTER(SP) - The stackpointer is a 12­bitregisterthatcontains the address of thenextfree
location on the stack. During an MCU reset or the
resetstackpointer(RSP)instruction, thestackpoin­ter is set to location$07F. The stackpointer is then
decremented as data is pushed onto the stack and
incremented asdata is then pulled from the stack.
The seven most significant bits of the stack pointer
are permanently set to 0000011. Subroutines and

interrupts maybe nested down tolocation $061(31
bytes maximum) which allows the programmer to
use up to 15 levelsof subroutine calls (less if inter­rupts are allowed).

CONDITIONCODE REGISTER(CC) - The condi­tioncoderegisterisa5-bitregisterin whichfoourbits
areusedto indicate theresultsof the instructionjust
executed. Thesebitscan be individually tested by a
program andspecificactiontakenasaresult oftheir
state. Each bit is explained in the following para­graphs.

7/31

EF6805U3

HalfCarry(H) -Setduring ADDandADCoperations
to indicate that a carry occurred betweenbits3 and

4.
Interrupt(I) - Whenthisbitis set, the timeran exter-

nalinterrupts(INTandINT2)are masked(disabled).
Ifaninterruptoccurswhile thisbitisset,the interrupt
is latchedandis processed as soonas the interrupt
bitis cleared.

Negative (N) - When set, this bit indicatesthat the
resultof the last arithmetic,logical, or data manipu­lationwasnegative (bit7intheresultisalogical ”1”).

Zero (Z) - When set,this bit indicates thatthe result
of the last arithmetic, logical, or data manipulation
waszero.

Carry/Borrow (C) - When set, this bit indicates that
a carry or borrow ou of the Arithmetic Logic Unit
(ALU)occurred during thelast arithmetic operation.
Thisbitisalso affected during bit test and branch in­structions plus shifts and rotates.

TIM ER

The timercircuitry for theEF6805U3is shown infig­ure 10. The timer contains a single 8-bit software
programmable counter with a 7-bit software selec­table prescaler. The counter may be preset under
program control and decrements toward zero.
When the counterdecrements to zero, the timerin­terrupt request bit, i.e., bit 7 of the timer control re­gister(TCR),is set. Thenif the timer interrupt is not
masked, i.e.,bit 6 of the TCR and the I bit in the
conditioncoderegister arebothcleared, the proces­sorreceivesaninterrupt.Aftercompletionofthecur­rentinstruction,the processor proceeds tostore the
appropriate registers on the stack,and thenfetches
the timer interrupt vector from locations $FF8 and
$FF9 inorder to begin servicing the interrupt.

Thecountercontinuestocountafterit reaches zero,
allowing the softwaretodetermine the number ofin­ternalor external input clocks since the timer inter­rupt request bit was set.The counter may be read
at any time by the processor without disturbing the
count. The contents of the counter become stable
priortothereadportionofacycleanddonotchange
during the read. The timer interrupt request bit re­mains setuntil cleared by the software. If awrite oc­cursbeforethe timerinterrup issericed, theinterrupt
is lost.TCR7 may also be used as a scanned status
bitin a non-interrupt mode of operation (TCR6 = 1).

The prescaler is a 7-bit divider which is usedto ex­tend the maximum length of the timer. Bit 0, bit 1,
andbit 2 of theTCR areprogrammed to choosethe
appropriate prescaler outptu which is used as the
counter input. The processor cannot writ eijto or

read from the prescaler ; however, its contentsare
cleared to all zeros by the write operation into TCR
when bit 3 of thewritten data equals one, which al­lows for truncation-free counting.

The timerinput canbe configured for threedifferent
operating modes, plus a disable mode, depending
on the value writtento the TCR4 and TCR5 control
bits. For further information seefigure 9.

Timer Input Mode 1 - If TCR5 adn TCR4 are both
programmed to a zero, the inpt to thetimer is from
an internal clock and the external TIMER inputisdi­sabled.The internal clock mode canbe used for pe­riodic interrupt generation, as well as a referene in
frequency and event measurement. The internal
clockis the instruction cycle clock.

Timer Input Mode 2 - With TCR5 = 0 and TCR4 =
1, theinternalclockandtheTIMERinputpinareAN­Ded toform the timerinput signal. Thismodecanbe
usedtomeasure externalpulse widths.Theexternal
timer input pulse simply turns on the internal clock
for the duration of the pulse widths.

TimerInputMode3 - IfTCR5=1andTCR4=0,then
all inputs tothe timer are disabled.

Timer InputMode4-If TCR5= 1 and TCR4=1,the
internal clock input to the timer is disabled and the
TIMERinput pinbecomes theinput to thetimer.The
external TIMER pin can, in this mode, be used to
count external events as well as external frequen­cies for generating periodic interrupts.
TCR7 - TimerInterruptRequest Bit :

76543210

TCR7TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0$009

* Write only (read as zero).

1 - Set when TDR goes to zero, or under pro­gramcontrol
0 - Clearedon external Reset,Power-On-Re­set,or under ProgramControl.

TCR6 - Timer Interrupt Mask Bit :

1 - Timer Interrupt masked (disabled) Set on
external Reset, Power-On-Reset, or under
Program Control
0 - Clearedunder Program Control.

TCR5 - External or Internal ClockSource Bit:

1 - External Clock Source. Set on externalRe­set, Power-On-Reset, or under Program
Control
0 - Clearedunder Program Control.

TCR4 - External Enable Bit :

1 - Enable external TIMERpin.Set on external
Reset, Poxer-On-Reset, or under Program

8/31

EF6805U3

Control.
0 - Clearedunder Program Control.

TCR3 - Timer prescaler reset bit : Aread of TCR3

TCR5 TCR4 Result

0
0

1
1

0

Internal Clock to Timer

1

AND of Internal Clock and TIMER
Pin to Timer

0

Input to timer disabled.

1

TIMER Pin to Timer

always indicates a zero.

1 - Set on externalReset, Power-On-Reset or
under Program Control.
0 - Clearedunder Program Control

Figure 10 : Timer Block Diagram.

TCR2 , TCR1, and TCR0 - Prescaler address
bits :
1 - All set on external Reset, Power-On-Reset
or under Program Control.
0 - Cleared under Program Control.

Figure9 : Timer Control Register (TCR).

TCR2 TCR1 TCR0 Result

0

0

0

1

0

0

0

1

0

1

1

0

TCR2 TCR1 TCR0 Result

+1
+2
+4
+8

0

1

0

1

1

1

1

1

0
1
0
1

+16
+32
+64

+128

Notes : 1. Prescaler and8-bit counter are clockedon thefailingedgeof the internal clock (AS)or external input.

SELF-CHECK - The self-check capability of the
EF6805U3 MCU provides an internal check to de­termineifthepart isfunctional.Connect theMCU as
shownin figure 11 and monitorthe output of Port C
bit 3 for an oscillation of approximately 7Hz. A 10­volt level(through a 10k resistor) on thetimer input,
pin 8 and pressing then releasing the RESET but­ton, energizes the ROM-based self-check feature.
The self-check program exercices the RAM, ROM,
TIMER, interrupts, and I/O ports.

Several of the self-checksubroutines can be called
by a user program with a JSR or BSR instruction.
TheyaretheRAM,ROM.Thetimerroutinemayalso
be called ifthe timer input is the internal2 clock.

2. Counter is written toduring dat strobe(DS) and counts down continuously.

To call those subroutines in customer application,
please contact your local SGS-THOMSON Micro­electronics sales office in order to obtain the
complete description of the self-check program and
the entrance/exit conditions.

RAMSELF-CHECKSUBROUTINE- TheRAM self­checkis calledat location $F84 andreturnswiththe
Z bit clear if any error is detected ; otherwise the Z
bit is set.The RAM test causes each byte to count
from0 upto 0 again with a check after each count.

The RAM test must be called with the stack pointer
at $07F and A= 0. Whenrun,thetest checks every
RAM cell except for $07F and $07E which are as­sumedto containthe return address.

9/31

EF6805U3

The A and X registersandallRAM locations except
$07F and $07E are modified.

ROM CHECKSUM SUBROUTINE - The ROM self­check is called at location $F95. The A register
should be cleared before calling the routine. If any
error is detected, it returns with the Z bit cleared ;

Figure 11 : Self-check Connections.

otherwise Z= 1, X = 0 on return,and A is zero if the
testpasses. RAM location $040to $043 is overwrit­ten.The checksumisthecomplement of theexecu­tionOR ofthe contents of the user ROM.

* This connection depends on clock oscillator user selectable
mask option. Use jumper if the RC mask option is selected.

LED MEANINGS

PC0 PC1 PC2 PC3

1

0

1

0

Bad I/O

0

0

1

0

Bad Timer

1

1

0

0

Bad RAM

0

1

0

0

Bad ROM

0

0

0

0

Bad Interrupts or RequestFlag

All Flashing Good Device

10/31

Remarks

(1 : LED ON ; 0 : LED OFF)