The DDR110 provides 10 bits resistor Network to
be used for SDR/DDR (double data rate) SDRAM
bus Termination.
This device has a series resistors (Rs) to reduce
signalreflectionnoise.Thiseliminatestheneedfor
external terminating resistors.
The DDR Termination Nerwork is enabled with the
output Enable pin (OE). When OE is HIGH Inputs
are connected to Outputs (A connected to B).
When OE is LOW every inputs are in High
impedance state (Hi - Z).
The DDR Termination Network is a bidirectional
device when the internal switch is ON. When the
switch is OFF, the device will block current in both
directions.
TM
This device is made using ST IPAD
(Integrated
Passive & Active devices) technology.
FEATURES AND BENEFITS
■
10 bits Termination Network.
■
Integrated Termination resistor (Rs)
■
Enable input TTL level compatible
■
Impedance matching ± 2% (A0-B0 / An-Bn)
■
OptimizedLowCrosstalkforparallel
Termination to Vtt.
■
Optimized Low propagation delay
1
1
VSS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
24
TSSOP24
Rs
Rs
Rs
Rs
Rs
Rs
Rs
Rs
Rs
Rs
12
VCC
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
24
May 2001 - Ed: 2
12
OE
GATE
CONTROL
NC
1/5
DDR110-xxT7RL
FUNCTION TABLE
OEB0 - B9Function
HighA0 - A9Connect Termination
LowHi - ZDisconnect Termination
ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C)
Value
SymbolParameterTest Conditions
V
CC
V
Supply voltage range
Input voltage range DQ0/7, DM0,
IN
DQS0
V
TT
V
OE
I
IN
V
ESD
T
STG
Termination voltage
Termination Enable Voltage range
Continuous input current
ESD ratings (input / output YOE)HBM MIL STD 883C
Storage temperature
RECOMMENDED OPERATING CONDITIONS (Tamb = 25°C)
SymbolParameterTestConditions
V
IN
Input voltage DQ0/7, DM0, DQS0OE LOW
OE HIGH
V
IH
Output Enable (OE) HIGH voltageGuaranteed logic
HIGH level
V
IL
Output Enable (OE) LOW voltageGuaranteed logic
LOW level
V
CC
V
TT
(1) Opencollectoroutput with 10k pull-up resistor to 5V is recommended for typical OE signal.
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