SGS Thomson Microelectronics CB65000 Datasheet
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CB65000 Series
March 2002
FEATURE
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0.18micron drawn , sixlayers of metal connected
by fully stackable vias and contacts, Shallow
Trench Isolation, low resistance, salicided
active areas and gates. Deep UV lithography.
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1.8 V opt imized High Performance and Low
Leakage transistors with 3.3 V I/O and supply
interface capability.
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Average gate density: 85K/mm2, plus low power
consumption of 30nanoWatt/Ga te/MHz /
Stdload.
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Two input NAND delay of 35ps with High
Performane transistor and 60ps with Low
Leakage transistor.
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Library available in commercial, industrial and
military temperature range. Power supply
ranging from 1.2V and 1.95V for Core
(according to JESD 8-7 specification) and
between 3.0V and 3.6V for I/Os (alligned w ith
JESD 8-A specification).
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Broad I/O functionality including:
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Low Voltage CMOS.
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Low Voltage TTL,HSTL, SSTL.
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AGP 2X and 4X, USB, PCI, LVDS I/O interfaces
are also available.
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Drive capability up to 8 mA per buffer with slew
rate control, current spike suppression
impedance matching, and process
compensation capability to reduce delay
variation.
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Designs easily portable from previous
generations of CB55000 with an average factor
2 density increase, 30% speed improvement
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and 2.5 power reduction at respective nominal
voltages.
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Generators to support Single Port, Dual port
and multiple Port RAM, and ROMs with BIST
options.
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Extensive embedded function library including
ST DSP and micro-cores, third-party IPs,
Synopsys and Mentor Inventra synthetic
libraries id ea lly su it e d for c omplete System On
Chip fast integration .
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Embedded DRAM Capability
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80µm pitch linear and 50µm staggered pad
libraries.
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Fully independent power and ground
configuration for core and I/Os supported.
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I/O ring capability up to 1500 pads.
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Latch-up trigger current > ± 500 mA. ESD
protection above 4 kV in H.B.M.
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Oscillators and PLLs for wide frequency
spectrum.
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Broad range of more than 600 SSI cells.
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Design for test features including IEEE 1149.1
JTAG Boundary Scan architecture.
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Synopsys, Cadence and Mentor based design
systems with interface from multiple
workstations.
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Broad range of packaging solutions, including
PBGA, LBGA, SBGA, HPBGA, TQFP, PQFP,
PLCC up to 1000 pins with enhanced power
dissipation options.
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1.25 GigaHertzGigabit DLL technique.
CB65000 Super Integration
Cost Effective Product
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Architecture partitioning
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Trouble-free integration
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Application-specific
Your Product is Unique
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User specified cell integration
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Design confidentiality
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IP fully re-usable
HCMOS8D 0.18µm Standard Cells Family
CB65000 SERIES
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Figure 1. Process cross section and Interconnect pers pective vie w
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CB65000 SERIES
1 GENERAL DESCRIPTION
The CB65000 standard cell series uses a hi gh performan ce, low-voltage, 0.18µm drawn, six metal levels , high
density and high speed HCMOS8D process.
With an average routed gate density of 85,000 gates/mm
2
, the CB65000 family allows the integration of up to
30 million equival ent gates and is ideal for high-complexity or hi gh-performanc e devi ces fo r computer , tel ecommunication and consumer products.
With a gate delay of 35 ps with High Performance transistor and 60 ps with Low Leakage transisto r (for a 2- input
NAND gate at fan-out 1), the library meets the most demanding speed requirements in telecommunication and
computer application designs today.
Optim ized for 1. 8 V operati on, the librar y f eat ur e s a po we r c on su mp t i on of l es s th an 35 nW/Gate/M Hz (High
Performance; fan-out=1) and 25 nW/Gate/MHz (Low Leakage; fan-out=1) at 1.8 V.
The I/O buffers can be fully configured for both 1.8 V and 3.3 V interface options, with several high speed buffer
types available. These i nclude: l o w vol tage differential (LVDS) I/Os, PCI, AGP, USB, LVTTL, LVCMOS and SSTL.
The pad pitch down to 50µm, in a staggered arrangement, meets the requirements of high pin-count devices
which tend to become pad-limited at such library densiti es. For very high pin-count ICs, advanced solutions such
as Ball Grid Array packages are available.
New packaging solutions using a flip-chip approach are currently being developed.
Figure 2. HCMOS8D Front end cross section
CB65000 SERIES
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2 TECHNOLOGY OVERVIEW
The advanced HCMOS8D transistor architecture: at 0.18µm, very thin gate oxide: 35 Amstrong, optimized
threshold voltages and salicided source, drain, and gate leads to intrinsically high performances in both
N channel and P channel driving currents.
The major scaling factor is obtained through deep UV lithography at most masking levels, making sub-micron
pitch a reality.
Further integration in the process front-end comes from the use of the Shallow Trench Isolation process between active regions, both improving density and planarity of transistors. In or der to allow full utiliz ation of such
transistor density, up to 6 levels of metal are made available for routing.
The local interconnection level made in Tungsten, allows short interconnection at silicon layer improving memory and cell density., while all the six metal levels are of low resistivity aluminum for long range interconnection
and power distribution.
Figure 3. HCM OS 8 D Local Interconn e ct
The thick inter-level dielectric is completely planarized by Chemical Mechanical Polishing, which provides defect-free isolation between stripes within the same as well as between different levels.
Usage of Tungsten plugs at contacts and vias allows extremely dense and reliable interconnection between
metal layers. These vias and contacts are fully stackable, providing a direct vertical electrical connection from
the active level up to the sixth metal level. This efficient interconnect scheme makes routing fast and easy, as
well as having a very positive impact on high gate count, random-logic blocks density and routability.
The combination of both high drive and dense transistors, easily interconnected with up to six fine-pitch metal
levels and isolated by thick and low K dielectric leads to an optimum gate density, with low parasitic resistance
and capacitance. This results in very short interconnected gate delay and minimized power consumption.
Figure 4.
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