SGS Thomson Microelectronics 74ACT74TTR, 74ACT74MTR, 74ACT74M, 74ACT74B Datasheet

74ACT74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
HIGH SPEED:
f
= 250MHz (TYP.) at VCC = 5V
MAX
LOW POWER DISSIPATION:
I
= 4µA(MAX.) at TA=25°C
CC
COMPATIBLE WITH TTL OUTPUTS
V
= 2V (MIN.), VIL = 0.8V (MAX.)
IH
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
| = IOL = 24mA (MIN)
OH
BALANCED PROPAGATION DELAYS:
t
t
PLH
OPERATING VOL TAGE RANGE:
V
CC
PIN AND FUNCTION COMPATIBLE WITH
PHL
(OPR) = 4.5V to 5.5V
74 SERIES 74
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT74 is an advanced high-speed CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C
2
MOS tecnology. A signal on the D INPUT is transferred to the Q and Q
OUTPUTS during the positive going
transition of the clock pulse.
TSSOPDIP SOP
ORDER CODES
PACKAGE TUBE T & R
DIP 74ACT74B
SOP 74ACT74M 74ACT74MTR
TSSOP 74ACT74TTR
CLEAR and PRESET are independent of the clock and accomplished by a low setting on the appropriate input. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against stat ic discharge, giving them 2KV ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/12April 2001
74ACT74
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1, 13 1CLR 2, 12 1D, 2D Data Inputs
3, 11 1CK, 2CK Clock Input
4, 10 1PR
5, 9 1Q, 2Q True Flip-Flop Outputs 6, 8 1Q
7 GND Ground (0V)
14 V
TRUTH TABLE
, 2CLR
, 2PR Asyncronous Set - Direct
, 2Q Complement Flip-Flop
CC
Asyncronous Reset ­Direct Input
(LOW to HIGH, Edge Triggered)
Input
Outputs
Positive Supply Voltage
INPUTS OUTPUTS
CLR
PR DCKQ Q
L H X X L L CLEAR
H L X X H L PRESET
LLXXHH
HHL LH HHH HL HHX
X : Don’t Care
Q
n
Q
n
LOGIC DIAGRAM
FUNCTION
NO CHANGE
This log i c diagram has not be used to estimate propagation del ays
2/12
74ACT74
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
V
I
I
OK
I
I
or I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
V
T
dt/dv
1) VIN from 0.8V to 2.0V
Supply Voltage
CC
DC Input Voltage -0.5 to VCC + 0.5
I
DC Output Voltage -0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current DC Output Current
O
DC VCC or Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
Supply Voltage
CC
Input Voltage 0 to V
I
Output Voltage 0 to V
O
Operating Temperature
op
Input Rise and Fall Time V
= 4.5 to 5.5V (note 1)
CC
-0.5 to +7 V
± 20 mA ± 20 mA ± 50 mA
± 200 mA
-65 to +150 °C 300 °C
4.5 to 5.5 V
CC CC
-55 to 125 °C 8 ns/V
V V
V V
3/12
74ACT74
DC SPECIFICATIONS
Test Condition Value
T
Symbol Parameter
V
CC
(V)
V
V
V
V
I
CCT
I
I
OLD
I
OHD
1) Maxim um test duration 2ms, one output loaded at time
2) Incid ent wave switchi ng is guarant eed on transmission lines with i m pedances as low as 50
High Level Input
IH
Voltage Low Level Input
IL
Voltage High Level Output
OH
Voltage
Low Level Output
OL
Voltage
I
Input Leakage Cur-
I
rent Max ICC/Input
Quiescent Supply
CC
Current Dynamic Output
Current (note 1, 2)
4.5 VO = 0.1 V or V
-0.1V
CC
4.5 VO = 0.1 V or V
5.5 1.5 0.8 0.8 0.8
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
5.5
5.5
V
5.5
V
5.5
V
-0.1V
CC
=-50 µA
I
O
I
=-50 µA
O
I
=-24 mA
O
I
=-24 mA
O
=50 µA
I
O
I
=50 µA
O
I
=24 mA
O
I
=24 mA
O
= VCC or GND
I
VI = VCC - 2.1V
= VCC or GND
I
= 1.65 V max
OLD
= 3.85 V min
OHD
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
2.0 1.5 2.0 2.0
1.5 0.8 0.8 0.8
4.4 4.49 4.4 4.4
5.4 5.49 5.4 5.4
3.86 3.76 3.7
4.86 4.76 4.7
0.001 0.1 0.1 0.1
0.001 0.1 0.1 0.1
0.36 0.44 0.5
0.36 0.44 0.5
± 0.1 ± 1 ± 1 µA
0.6 1.5 1.6 mA 44040µA
-40 to 85°C -55 to 125°C
75 50 mA
-75 -50 mA
Unit
V5.5 2.0 1.5 2.0 2.0
V
V
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf = 3ns)
Test Condition Value
T
Symbol Parameter
t
PLH tPHL
t
PLH tPHL
Propagation Delay Time CK to Q or Q
Propagation Delay Time PR
or CLR to
Q or Q
t
Pulse Width HIGH
W
or LOW, CK or PR or CLR
Setup Time D to CK
t
s
HIGH or LOW
t
Hold Time D to CK
h
HIGH or LOW
t
REM
f
MAX
(*) Vol tage range is 5.0V ± 0.5V
Removal Tim|
or CLR to CK
PR Maximum Clock
Frequency
= 25°C
V
CC
(V)
(*)
5.0
(*)
5.0
(*)
5.0
(*)
5.0
(*)
5.0
(*)
5.0
(*)
5.0
A
Min. Typ. Max. Min. Max. Min. Max.
5.0 10.0 11.0 11.0 ns
5.0 10.0 11.0 11.0 ns
1.5 5.0 6.0 6.0 ns
0.5 3.0 3.5 3.5 ns
-0.5 1.0 1.0 1.0 ns
-0.7 1.0 1.0 1.0 ns
100 250 85 85 MHz
-40 to 85°C -55 to 125°C
Unit
4/12
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