Semiconductor NCV81277A User Manual

4/3/2/1 Phase Buck
Controller with PWM_VID

2

and I

C Interface

NCV81277A

The NCV81277A is a multiphase synchronous controller optimized
for new generation computing and graphics processors. The device is
capable of driving up to 4 phases and incorporates differential voltage
and phase current sensing, adaptive voltage positioning and
PWM_VID interface to provide and accurately regulated power for
computer or graphic controllers. The integrated power saving
interface (PSI) allows for the processors to set the controller in one of
three modes, i.e. all phases on, dynamic phases shedding or fixed low
phase count mode, to obtain high efficiency in light-load conditions.
The dual edge PWM multiphase architecture ensures fast transient
response and good dynamic current balance.

Features

• Compliant with NVIDIA

• Supports Up to 4 Phases

• 4.5 V to 20 V Supply Voltage Range

• 250 kHz to 1.2 MHz Switching Frequency (4 Phase)

• Power Good Output

• Under Voltage Protection (UVP)

• Over Voltage Protection (OVP)

• Over Current Protection (OCP)

• Per Phase Over Current Protection

• Startup into Pre-Charged Loads while Avoiding False OVP

• Configurable Adaptive Voltage Positioning (AVP)

• High Performance Operational Error Amplifier

• True Differential Current Balancing Sense Amplifiers for Each Phase

• Phase-to-Phase Dynamic Current Balancing

• Current Mode Dual Edge Modulation for Fast Initial Response to

Transient Loading

• Power Saving Interface (PSI)

• Automatic Phase Shedding with User Settable Thresholds

• PWM_VID and I

2

• Compact 40 Pin QFN Wettable Flank Package

• Operating Temperature Range: −40°C to +105°C

• AEC−Q100 Grade 2 Approved

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

• GPU and CPU Power

• Automotive Applications

®

OVR4+ Specifications

C Control Interface

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401

QFNW40

CASE 484AK

MARKING DIAGRAM

1

NCV81277A = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package

ON

NCV

81277A

AWLYYWW

G

PIN CONNECTIONS

VSP

VSN

VCC

SDA

SCL

EN

PSI

PGOOD

VID_BUFF

REFIN

VREF

VRMP

OCP

LPC1

LPC2

PWM4/PHTH1

PWM3/PHTH2

PWM2/PHTH3

PWM_VID

40

39

1

2

3

4

SS

5

6

7

8

9

10

12

11

DRON

PHTH4

PWM1/

35

36

37

38

NCV81277A

(TOP VIEW )

Tab: GROUND

13

161514

NCNCNC

NC

34

17

CSP4

33

18

CSP3

32

19

CSP2

31

30

29

28

27

26

25

24

23

22

21

20

CSP1

COMP

FB

DIFF

FSW

LLTH/I2C_ADD

IOUT

ILIM

CSCOMP

CSSUM

CSREF

ORDERING INFORMATION

Device Package Shipping

NCV81277AMNTXG QFNW40

(Pb-Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D

.

5000/Tape & Reel

†

© Semiconductor Components Industries, LLC, 2019

March, 2021 − Rev. 4

1 Publication Order Number:

NCV81277A/D

VCC_DUT

TP51

TP50

TP49

TP48

TP47

TP46

TP45

VSN_sense

J4

R38

SDA

2.2R

C5

SCL

J3

C17

1000pF

EN

NCV81277A

R125

R124

C21 470pF

R126

22

CSSUM

CSCOMP

PWM3/PHTH2

9

R57

20k

R56

10k

R55

R54

R127

100k

24.9k

R50

C13

21

41

CSREF

PWM2/PHTH3

10

3.3n

RT1

390nF

PAD

CSP1

20

CSP2

19

CSP3

18

CSP4

17

NC

16

NC

15

NC

14

NC

13

DRON

12

PWM1/PHTH4

11

TP62

R14

C19

49.9k

R51

DRON

C20

1n

TP60

10R

R45

10R

R44

C10 0.1uF

TP61

10R

R47

10R

R46

0.1uF

C11

0.1uF

C12

0.1uF

C14

2.94k

2.94k

2.94k

2.94k

R27

R26

R24

R23

0R

R

34k

34k

R36

R34 34k

R35 34k

R32

R149 0R

R148

R147 0

R146 0 R

CSN1

CSN2

CSN3

CSN4

SWN2

SWN3

SWN4

SWN1

0R

0R

TP59

TP58

TP57

20.5k

R28

4.12k
R25

R49

C18

R43

C15

REFIN

R21

R16

1.8k

TP56

TP55

2.74k
1k

R48

2.2n

1.5k
27pF

C16

15nF

28FB29

30

FSW27DIFF

COMP

VSP

31

VSN

32

VCC

33

SDA

34

SCL

35

EN

36

PSI

37

PGOOD

38

PWM_VID

39

VID_BUFF

40

VREF

REFIN1VRAMP3SS4OCP5LPC16LPC27PWM4/PHTH1

U1

2

14.7k

C4

2

10nF

C3

4.7nF

23

24

25

26

ILIM

IOUT

LLTH/I2C ADD

NCV81277A

8

VSP_sense

TP54

TP53

TP52

1uF

R37

10.2k

TP44

PSI

PGOOD

C2

4.7nF

1

2

J1

PWM_VID in

PWM2

PWM1

R13

R10

R7

R4

26.1k

R2

26.1k

TP43

VREF

R9

1k

C1

0.01uF

VIN

TP40

TP41

TP39

TP38

TP42

TP37

TP36

TP1

PWM3

345

PWM4

Figure 1. Typical Controller Application Circuit

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2

NCV81277A

VCORE_SNS

VCORE_GND_SNS

SW1

SWn

VCORE_SNS

VCORE_GND_SNS

CSP1

CSPn

NCV81277A/5A

VRMP

VIN

NCV3025833

VSP

VSN

DIFF

FB

COMP

CSSUM

DRON

PWM1

CSP1

CSREF

DRON

CSREF

EN

PWM

DrMOS

VIN

SW

...

NTC

CSCOMP

ILIM

IOUT

PWMn

CSPn

DRON

NCV3025833

DrMOS

EN

PWM

VIN

SW

Figure 2. Typical Phase Application Circuit (5x5 DrMOS with no IMON)

DRON

VIN

EN

PWM

IMON REFIN

NCV303150

DrMOS

VIN

SW

NCV81277A/5A

VSP

VSN

DIFF

FB

COMP

CSSUM

VRMP

DRON

PWM1

CSP1

CSREF

CSP1

CSREF

...

DRON

NCV303150

DrMOS

EN

PWM

IMON REFIN

VIN

SW

CSCOMP

ILIM

IOUT

PWMn

CSPn

CSREF

VIN

VIN

VIN

VIN

VIN

SW1

SW

SW1

SWn

VCORE

n

CSREF

VCORE

Figure 3. Typical Phase Application Circuit (6x5 DrMOS with IMON)

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NCV81277A

Table 1. PIN FUNCTION DESCRIPTION

Pin

Number

1 REFIN I Reference voltage input for output voltage regulation.

2 VREF O 2.0 V output reference voltage. A 10 nF ceramic capacitor is required to connect this pin

3 VRMP I Feed-forward input of VIN for the ramp slope compensation. The current fed into this pin

4 SS I/O Soft Start setting. During startup it is used to program the soft start time with a resistor to

5 OCP I/O Per OCP setting. During startup it is used to program the OCP level per phase and latch

6 LPC1 I/O Low phase count 1. During startup it is used to program the power zone (when PSI is set

7 LPC2 I/O Low phase count 2. During startup it is used to program boot-up power zone (when PSI

8 PWM4/PHTH1 I/O PWM 4 output/Phase Shedding Threshold 1. During startup it is used to program the

9 PWM3/PHTH2 I/O PWM 3 output/Phase Shedding Threshold 2. During startup it is used to program the

10 PWM2/PHTH3 I/O PWM 2 output/Phase Shedding Threshold 3. During startup it is used to program the

11 PWM1/PHTH4 I/O PWM 1 output/Phase Shedding Threshold 4. During startup it is used to program the

12 DRON I/O Bidirectional gate driver enable for external drivers.

13 NC N/A No connect pin. Please leave floating.

14 NC N/A No connect pin. Please leave floating.

15 NC N/A No connect pin. Please leave floating.

16 NC N/A No connect pin. Please leave floating.

17 CSP4 I Non-inverting input to current balance sense amplifier for phase 4. Pull-up to VCC via a

18 CSP3 I Non-inverting input to current balance sense amplifier for phase 3. Pull-up to VCC via a

19 CSP2 I Non-inverting input to current balance sense amplifier for phase 2. Pull-up to VCC via a

20 CSP1 I Non-inverting input to current balance sense amplifier for phase 1. Pull-up to VCC via a

21 CSREF I Total output current sense amplifier reference voltage input.

22 CSSUM I Inverting input of total current sense amplifier.

23 CSCOMP O Output of total current sense amplifier.

24 ILIM O Over current shutdown threshold setting output. The threshold is set by a resistor be-

25 IOUT O Total output current. A resistor to GND is required to provide a voltage drop of 2 V at the

26 LLTH/I2C_ADD I Load line selection from 0% to 100% and I2C address pin.

27 FSW I Resistor to ground form this pin sets the operating frequency of the regulator.

28 DIFF O Output of the regulators differential remote sense amplifier.

29 FB I Error amplifier inverting (feedback) input.

30 COMP O Output of the error amplifier and the inverting input of the PWM comparator.

31 VSP I Differential Output Voltage Sense Positive terminal.

Pin

Name

Pin

Type

Description

to ground.

is used to control of the ramp of PWM slope.

ground.

off time with a resistor to ground.

low) with a resistor to ground.

is set low) with a resistor to ground.

phase shedding threshold 1 (PSI set to mid state) with a resistor to ground.

phase shedding threshold 2 (PSI set to mid state) with a resistor to ground.

phase shedding threshold 3 (PSI set to mid state) with a resistor to ground.

phase shedding threshold 4 (PSI set to mid state) with a resistor to ground.

2K to disable the PWM4 output.

2K to disable the PWM3 output.

2K to disable the PWM2 output.

2K to disable the PWM1 output.

tween ILIM and to CSCOMP pins.

maximum output current.

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4

NCV81277A

Table 1. PIN FUNCTION DESCRIPTION (continued)

Pin

Number

32 VSN I Differential Output Voltage Sense Negative terminal.

33 VCC I

34 SDA I/O Serial Data bi-directional pin, requires pull-up resistor to VCC.

35 SCL I Serial Bus clock signal, requires pull-up resistor to VCC.

36 EN I Logic input. Logic high enables regulator output logic low disables regulator output.

37 PSI I

38 PGOOD O Open Drain power good indicator.

39 PWM_VID I PWM_VID buffer input.

40 VID_BUFF O PWM_VID pulse output from internal buffer.

41 AGND GND Analog ground and thermal pad, connected to system ground.

Pin

Name

Table 2. MAXIMUM RATINGS

Rating

Pin Voltage Range (Note 1)

Pin Current Range

Moisture Sensitivity Level MSL 1 −

Lead Temperature Soldering Reflow (SMD Styles Only),
Pb-Free Versions (Note 2)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

1. All signals referenced to GND unless noted otherwise.

2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

Pin

Type

Description

Power for the internal control circuits. A 1 mF decoupling capacitor is requires from this
pin to ground.

Power level control 3 level control. Use a current limiting resistor of 100 kW when driving
the pin with 5 V logic.

Pin Symbol Min Typ Max Unit

VSN GND−0.3 GND + 0.3 V

VCC −0.3 6.5 V

VRMP −0.3 25 V

PWM_VID −0.3

All Other Pins

with the

COMP

CSCOMP

DIFF

PGOOD

VSN −1 1 mA

T

SLD

(−2, < 50 ns)

−0.3 VCC + 0.3 V

−2 2 mA

260 °C

VCC + 0.3 V

.

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NCV81277A

Table 3. THERMAL CHARACTERISTICS

Rating

Thermal Characteristics, (QFN40, 5 × 5 mm)

Thermal Resistance, Junction-to-Air (Note 1)

Process Junction Temperature Range (Note 2) T

Operating Ambient Temperature Range T

Maximum Storage Temperature Range T

1. JESD 51−5 (1S2P Direct-Attach Method) with 0 LFM.

2. JESD 51−7 (1S2P Direct-Attach Method) with 0 LFM.

Table 4. ELECTRICAL CHARACTERISTICS

(Unless otherwise stated: −40°C < TA < 105°C; 4.6 V < VCC < 5.4 V; C

Parameter

VRMP

Supply Range

UVLO

VRMP Rising V

VRMP Falling V

VRMP UVLO Hysteresis V

BIAS SUPPLY

Supply Voltage Range

VCC Quiescent current

Enable Low

4 Phase Operation 32 mA

1 Phase-DCM Operation 10 mA

UVLO Threshold

VCC Rising UVLO

VCC Falling UVLO

VCC UVLO Hysteresis UVLO

SWITCHING FREQUENCY

Switching Frequency Range

Switching Frequency Accuracy

4 Phase Configuration F

FSW = 810 kHz

all range −10 +10

ENABLE INPUT

Input Leakage

EN = 0 V or VCC I

Upper Threshold V

Lower Threshold V

DRON

Output High Voltage

Output Low Voltage

Rise Time

Sourcing 500 mA

Sinking 500 mA

Cl(PCB) = 20 pF,
DV

Fall Time

Cl(PCB) = 20 pF,
DVO = 10% to 90%

Internal Pull-up Resistance R

Internal Pull-down Resistance VCC = 0 V R

Test Conditions Symbol Min Typ Max Unit

= 10% to 90%

O

Symbol Min Ty p Max Unit

R

θJA

J

A

STG

= 0.1 mF)

VCC

PULL_DOWN

− 68 −

°C/W

−40 − 150

−40 − 105

−55 − 150

_C

_C

_C

VRMP 4.5 20 V

RMPrise

RMPfall

RMPhyst

3 V

800 mV

4.2 V

VCC 4.6 5.4 V

ICC

Rise

Fall

Hyst

SW

DF

SW

L

IH

IL

V

OH

V

OL

t

R

t

F

PULL−UP

4 V

200 mV

250 1200 kHz

−4 +4

−1.0 1.0

1.2 V

3.0 V

160 ns

3 ns

2.0

40

4.5 V

0.6 V

0.1 V

70

mA

%

mA

kW

kW

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NCV81277A

Table 4. ELECTRICAL CHARACTERISTICS (continued)

(Unless otherwise stated: −40°C < TA < 105°C; 4.6 V < VCC < 5.4 V; C

Parameter UnitMaxTypMinSymbolTest Conditions

PGOOD

I

Output Low Voltage

Leakage Current P

= 10 mA (Sink) V

PGOOD

= 5 V I

GOOD

Output Voltage Initialization Time From EN to DRON T_init 1.5 ms

Minimum Output Voltage Ramp

REFIN = 1.0 V T_ramp

Time

Maximum Output Voltage Ramp

REFIN = 1.0 V T_ramp

Time

PROTECTION-OCP, OVP, UVP

Under Voltage Protection (UVP)

Relative to REFIN Voltage UVP 250 300 350 mV

Threshold

Under Voltage Protection (UVP)
Delay

Over Voltage Protection (OVP)

Relative to REFIN Voltage OVP 360 400 430 mV

Threshold

Over Voltage Protection (OVP)
Delay

Over Current Protection (ILIM) internal current source ILIM

PWM OUTPUTS

Output High Voltage

Sourcing 500 mA

Output Mid Voltage V

Output Low Voltage

Rise and Fall Time

Sinking 500 mA

CL(PCB) = 50 pF, DVO = 10% to
90% of VCC

Tri-state Output Leakage Gx = 2.0 V, x = 1−8, EN = Low I

Minimum On Time FSW = 600 kHz To n 12 ns

0% Duty Cycle Comp Voltage when PWM Outputs

Remain LOW

100% Duty Cycle Comp Voltage when PWM Outputs

Remain HIGH

PWM Phase Angle Error Between Adjacent Phases ø ±15 °

PHASE DETECTION

Phase Detection Threshold Volt-

CSP2 to CSP4 V

age

Phase Detect Timer CSP2 to CSP4 T

ERROR AMPLIFIER

Input Bias Current

Open Loop DC Gain CL = 20 pF to GND,

= 10 kW to GND

R

L

Open Loop Unity Gain Bandwidth CL = 20 pF to GND,

= 10 kW to GND

R

L

Slew Rate

Maximum Output Voltage I

Minimum Output Voltage I

DVIN = 100 mV, G = −10 V/V,

= 0.75–1.52 V, CL = 20 pF

DV

OUT

to GND, R

SOURCE

SINK

= 10 kW to GND

L

= 2 mA V

= 2 mA V

VCC

= 0.1 mF)

OL

T

UVP

T

OVP

V

OH

MID

V

OL

tR, t

VCOMP

VCOMP

PHDET

PHDET

I

BIAS

G

L

L

OL

MIN

MAX

0.15 ms

10 ms

5

5

th

9.5 10 10.5

VCC − 0.2 V

1.9 2.0 2.1 V

F

10 ns

−1.0 1.0

0%

100%

1.3 V

2.5 V

1.1 ms

−400 400 nA

80 dB

0.4 V

0.2

0.7 V

VCC − 0.1 V

GBW 20 MHz

SR 5

OUT

OUT

3.5 V

1 V

V/ms

mA

ms

ms

mA

mA

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NCV81277A

Table 4. ELECTRICAL CHARACTERISTICS (continued)

(Unless otherwise stated: −40°C < TA < 105°C; 4.6 V < VCC < 5.4 V; C

Parameter UnitMaxTypMinSymbolTest Conditions

DIFFERENTIAL SUMMING AMPLIFIER

Input Bias Current

VSP Input Voltage V

VSN Input Voltage V

−3dB Bandwidth CL = 20 pF to GND,
= 10 kW to GND

R

L

Closed Loop DC Gain

VSP to VSN = 0.5 to 1.3 V G 1 V/V

(VSP−VSN to DIFF)

Droop accuracy CSREF − DROOP = 80 mV,

V

= 0.8 V to 1.2 V

REFIN

Maximum Output Voltage I

Minimum Output Voltage I

= 2 mA V

SOURCE

= 2 mA V

SINK

CURRENT SUMMING AMPLIFIER

Offset Voltage

Input Bias Current CSSUM = CSREF = 1 V I

Open Loop Gain G 80 dB

Current sense Unity Gain Band­width

Maximum CSCOMP Output Volt­age

Minimum CSCOMP Output Voltage I

CL = 20 pF to GND,

= 10 kW to GND

R

L

I

= 2 mA V

SOURCE

= 2 mA V

SINK

CURRENT BALANCE AMPLIFIER

Input Bias Current

Common Mode Input Voltage

CSPX − CSP

CSPX = CSREF V

= 1.2 V I

X+1

Range

Differential Mode Input Voltage

CSREF = 1.2 V V

Range

Closed Loop Input Offset Voltage
Matching

CSPX = 1.2 V, Measured from the
Average

Current Sense Amplifier Gain 0 V < CSPX < 0.1 V G 5.7 6.0 V/V

Multiphase Current Sense Gain

CSREF = CSP = 10 mV to 30 mV

Matching

−3dB Bandwidth BW 8 MHz

IOUT

Input Reference Offset Voltage

Output Current Max

Current Gain

ILIM to CSREF V

ILIM Sink Current 20 mA

IOUT/ILIM, R

= 5 kW

R

IOUT

= 20 kW,

LIM

VOLTAGE REFERENCE

I

VREF Reference Voltage

VREF Reference accuracy T

= 1 mA VREF 1.98 2 2.02 V

REF

< TJ < T

JMIN

JMAX

VCC

= 0.1 mF)

I

BIAS

IN

IN

−400 400 nA

0 2 V

−0.3 0.3 V

BW 27 MHz

DDROOP

OUT

OUT

V

OS

L

78 82 mV

3 V

0.8 V

−500 500

−7.5 7.5

GBW 10 MHz

OUT

OUT

BIAS

CM

DIFF

3.5 V

0.1 V

−50 50 nA

0 2 V

−100 100 mV

−1.5 1.5 mV

DG

I

OUT

OS

−3 3 %

−3 +3 mV

200

G 9.5 10 10.5 A/A

DVREF

1 %

mV

mA

mA

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