Semiconductor NCV81277A User Manual

4/3/2/1 Phase Buck
Controller with PWM_VID

2

and I

C Interface

NCV81277A

The NCV81277A is a multiphase synchronous controller optimized
for new generation computing and graphics processors. The device is
capable of driving up to 4 phases and incorporates differential voltage
and phase current sensing, adaptive voltage positioning and
PWM_VID interface to provide and accurately regulated power for
computer or graphic controllers. The integrated power saving
interface (PSI) allows for the processors to set the controller in one of
three modes, i.e. all phases on, dynamic phases shedding or fixed low
phase count mode, to obtain high efficiency in light-load conditions.
The dual edge PWM multiphase architecture ensures fast transient
response and good dynamic current balance.

Features

• Compliant with NVIDIA

• Supports Up to 4 Phases

• 4.5 V to 20 V Supply Voltage Range

• 250 kHz to 1.2 MHz Switching Frequency (4 Phase)

• Power Good Output

• Under Voltage Protection (UVP)

• Over Voltage Protection (OVP)

• Over Current Protection (OCP)

• Per Phase Over Current Protection

• Startup into Pre-Charged Loads while Avoiding False OVP

• Configurable Adaptive Voltage Positioning (AVP)

• High Performance Operational Error Amplifier

• True Differential Current Balancing Sense Amplifiers for Each Phase

• Phase-to-Phase Dynamic Current Balancing

• Current Mode Dual Edge Modulation for Fast Initial Response to

Transient Loading

• Power Saving Interface (PSI)

• Automatic Phase Shedding with User Settable Thresholds

• PWM_VID and I

2

• Compact 40 Pin QFN Wettable Flank Package

• Operating Temperature Range: −40°C to +105°C

• AEC−Q100 Grade 2 Approved

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

• GPU and CPU Power

• Automotive Applications

®

OVR4+ Specifications

C Control Interface

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401

QFNW40

CASE 484AK

MARKING DIAGRAM

1

NCV81277A = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package

ON

NCV

81277A

AWLYYWW

G

PIN CONNECTIONS

VSP

VSN

VCC

SDA

SCL

EN

PSI

PGOOD

VID_BUFF

REFIN

VREF

VRMP

OCP

LPC1

LPC2

PWM4/PHTH1

PWM3/PHTH2

PWM2/PHTH3

PWM_VID

40

39

1

2

3

4

SS

5

6

7

8

9

10

12

11

DRON

PHTH4

PWM1/

35

36

37

38

NCV81277A

(TOP VIEW )

Tab: GROUND

13

161514

NCNCNC

NC

34

17

CSP4

33

18

CSP3

32

19

CSP2

31

30

29

28

27

26

25

24

23

22

21

20

CSP1

COMP

FB

DIFF

FSW

LLTH/I2C_ADD

IOUT

ILIM

CSCOMP

CSSUM

CSREF

ORDERING INFORMATION

Device Package Shipping

NCV81277AMNTXG QFNW40

(Pb-Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D

.

5000/Tape & Reel

†

© Semiconductor Components Industries, LLC, 2019

March, 2021 − Rev. 4

1 Publication Order Number:

NCV81277A/D

VCC_DUT

TP51

TP50

TP49

TP48

TP47

TP46

TP45

VSN_sense

J4

R38

SDA

2.2R

C5

SCL

J3

C17

1000pF

EN

NCV81277A

R125

R124

C21 470pF

R126

22

CSSUM

CSCOMP

PWM3/PHTH2

9

R57

20k

R56

10k

R55

R54

R127

100k

24.9k

R50

C13

21

41

CSREF

PWM2/PHTH3

10

3.3n

RT1

390nF

PAD

CSP1

20

CSP2

19

CSP3

18

CSP4

17

NC

16

NC

15

NC

14

NC

13

DRON

12

PWM1/PHTH4

11

TP62

R14

C19

49.9k

R51

DRON

C20

1n

TP60

10R

R45

10R

R44

C10 0.1uF

TP61

10R

R47

10R

R46

0.1uF

C11

0.1uF

C12

0.1uF

C14

2.94k

2.94k

2.94k

2.94k

R27

R26

R24

R23

0R

R

34k

34k

R36

R34 34k

R35 34k

R32

R149 0R

R148

R147 0

R146 0 R

CSN1

CSN2

CSN3

CSN4

SWN2

SWN3

SWN4

SWN1

0R

0R

TP59

TP58

TP57

20.5k

R28

4.12k
R25

R49

C18

R43

C15

REFIN

R21

R16

1.8k

TP56

TP55

2.74k
1k

R48

2.2n

1.5k
27pF

C16

15nF

28FB29

30

FSW27DIFF

COMP

VSP

31

VSN

32

VCC

33

SDA

34

SCL

35

EN

36

PSI

37

PGOOD

38

PWM_VID

39

VID_BUFF

40

VREF

REFIN1VRAMP3SS4OCP5LPC16LPC27PWM4/PHTH1

U1

2

14.7k

C4

2

10nF

C3

4.7nF

23

24

25

26

ILIM

IOUT

LLTH/I2C ADD

NCV81277A

8

VSP_sense

TP54

TP53

TP52

1uF

R37

10.2k

TP44

PSI

PGOOD

C2

4.7nF

1

2

J1

PWM_VID in

PWM2

PWM1

R13

R10

R7

R4

26.1k

R2

26.1k

TP43

VREF

R9

1k

C1

0.01uF

VIN

TP40

TP41

TP39

TP38

TP42

TP37

TP36

TP1

PWM3

345

PWM4

Figure 1. Typical Controller Application Circuit

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2

NCV81277A

VCORE_SNS

VCORE_GND_SNS

SW1

SWn

VCORE_SNS

VCORE_GND_SNS

CSP1

CSPn

NCV81277A/5A

VRMP

VIN

NCV3025833

VSP

VSN

DIFF

FB

COMP

CSSUM

DRON

PWM1

CSP1

CSREF

DRON

CSREF

EN

PWM

DrMOS

VIN

SW

...

NTC

CSCOMP

ILIM

IOUT

PWMn

CSPn

DRON

NCV3025833

DrMOS

EN

PWM

VIN

SW

Figure 2. Typical Phase Application Circuit (5x5 DrMOS with no IMON)

DRON

VIN

EN

PWM

IMON REFIN

NCV303150

DrMOS

VIN

SW

NCV81277A/5A

VSP

VSN

DIFF

FB

COMP

CSSUM

VRMP

DRON

PWM1

CSP1

CSREF

CSP1

CSREF

...

DRON

NCV303150

DrMOS

EN

PWM

IMON REFIN

VIN

SW

CSCOMP

ILIM

IOUT

PWMn

CSPn

CSREF

VIN

VIN

VIN

VIN

VIN

SW1

SW

SW1

SWn

VCORE

n

CSREF

VCORE

Figure 3. Typical Phase Application Circuit (6x5 DrMOS with IMON)

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3

NCV81277A

Table 1. PIN FUNCTION DESCRIPTION

Pin

Number

1 REFIN I Reference voltage input for output voltage regulation.

2 VREF O 2.0 V output reference voltage. A 10 nF ceramic capacitor is required to connect this pin

3 VRMP I Feed-forward input of VIN for the ramp slope compensation. The current fed into this pin

4 SS I/O Soft Start setting. During startup it is used to program the soft start time with a resistor to

5 OCP I/O Per OCP setting. During startup it is used to program the OCP level per phase and latch

6 LPC1 I/O Low phase count 1. During startup it is used to program the power zone (when PSI is set

7 LPC2 I/O Low phase count 2. During startup it is used to program boot-up power zone (when PSI

8 PWM4/PHTH1 I/O PWM 4 output/Phase Shedding Threshold 1. During startup it is used to program the

9 PWM3/PHTH2 I/O PWM 3 output/Phase Shedding Threshold 2. During startup it is used to program the

10 PWM2/PHTH3 I/O PWM 2 output/Phase Shedding Threshold 3. During startup it is used to program the

11 PWM1/PHTH4 I/O PWM 1 output/Phase Shedding Threshold 4. During startup it is used to program the

12 DRON I/O Bidirectional gate driver enable for external drivers.

13 NC N/A No connect pin. Please leave floating.

14 NC N/A No connect pin. Please leave floating.

15 NC N/A No connect pin. Please leave floating.

16 NC N/A No connect pin. Please leave floating.

17 CSP4 I Non-inverting input to current balance sense amplifier for phase 4. Pull-up to VCC via a

18 CSP3 I Non-inverting input to current balance sense amplifier for phase 3. Pull-up to VCC via a

19 CSP2 I Non-inverting input to current balance sense amplifier for phase 2. Pull-up to VCC via a

20 CSP1 I Non-inverting input to current balance sense amplifier for phase 1. Pull-up to VCC via a

21 CSREF I Total output current sense amplifier reference voltage input.

22 CSSUM I Inverting input of total current sense amplifier.

23 CSCOMP O Output of total current sense amplifier.

24 ILIM O Over current shutdown threshold setting output. The threshold is set by a resistor be-

25 IOUT O Total output current. A resistor to GND is required to provide a voltage drop of 2 V at the

26 LLTH/I2C_ADD I Load line selection from 0% to 100% and I2C address pin.

27 FSW I Resistor to ground form this pin sets the operating frequency of the regulator.

28 DIFF O Output of the regulators differential remote sense amplifier.

29 FB I Error amplifier inverting (feedback) input.

30 COMP O Output of the error amplifier and the inverting input of the PWM comparator.

31 VSP I Differential Output Voltage Sense Positive terminal.

Pin

Name

Pin

Type

Description

to ground.

is used to control of the ramp of PWM slope.

ground.

off time with a resistor to ground.

low) with a resistor to ground.

is set low) with a resistor to ground.

phase shedding threshold 1 (PSI set to mid state) with a resistor to ground.

phase shedding threshold 2 (PSI set to mid state) with a resistor to ground.

phase shedding threshold 3 (PSI set to mid state) with a resistor to ground.

phase shedding threshold 4 (PSI set to mid state) with a resistor to ground.

2K to disable the PWM4 output.

2K to disable the PWM3 output.

2K to disable the PWM2 output.

2K to disable the PWM1 output.

tween ILIM and to CSCOMP pins.

maximum output current.

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4

NCV81277A

Table 1. PIN FUNCTION DESCRIPTION (continued)

Pin

Number

32 VSN I Differential Output Voltage Sense Negative terminal.

33 VCC I

34 SDA I/O Serial Data bi-directional pin, requires pull-up resistor to VCC.

35 SCL I Serial Bus clock signal, requires pull-up resistor to VCC.

36 EN I Logic input. Logic high enables regulator output logic low disables regulator output.

37 PSI I

38 PGOOD O Open Drain power good indicator.

39 PWM_VID I PWM_VID buffer input.

40 VID_BUFF O PWM_VID pulse output from internal buffer.

41 AGND GND Analog ground and thermal pad, connected to system ground.

Pin

Name

Table 2. MAXIMUM RATINGS

Rating

Pin Voltage Range (Note 1)

Pin Current Range

Moisture Sensitivity Level MSL 1 −

Lead Temperature Soldering Reflow (SMD Styles Only),
Pb-Free Versions (Note 2)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

1. All signals referenced to GND unless noted otherwise.

2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

Pin

Type

Description

Power for the internal control circuits. A 1 mF decoupling capacitor is requires from this
pin to ground.

Power level control 3 level control. Use a current limiting resistor of 100 kW when driving
the pin with 5 V logic.

Pin Symbol Min Typ Max Unit

VSN GND−0.3 GND + 0.3 V

VCC −0.3 6.5 V

VRMP −0.3 25 V

PWM_VID −0.3

All Other Pins

with the

COMP

CSCOMP

DIFF

PGOOD

VSN −1 1 mA

T

SLD

(−2, < 50 ns)

−0.3 VCC + 0.3 V

−2 2 mA

260 °C

VCC + 0.3 V

.

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5

NCV81277A

Table 3. THERMAL CHARACTERISTICS

Rating

Thermal Characteristics, (QFN40, 5 × 5 mm)

Thermal Resistance, Junction-to-Air (Note 1)

Process Junction Temperature Range (Note 2) T

Operating Ambient Temperature Range T

Maximum Storage Temperature Range T

1. JESD 51−5 (1S2P Direct-Attach Method) with 0 LFM.

2. JESD 51−7 (1S2P Direct-Attach Method) with 0 LFM.

Table 4. ELECTRICAL CHARACTERISTICS

(Unless otherwise stated: −40°C < TA < 105°C; 4.6 V < VCC < 5.4 V; C

Parameter

VRMP

Supply Range

UVLO

VRMP Rising V

VRMP Falling V

VRMP UVLO Hysteresis V

BIAS SUPPLY

Supply Voltage Range

VCC Quiescent current

Enable Low

4 Phase Operation 32 mA

1 Phase-DCM Operation 10 mA

UVLO Threshold

VCC Rising UVLO

VCC Falling UVLO

VCC UVLO Hysteresis UVLO

SWITCHING FREQUENCY

Switching Frequency Range

Switching Frequency Accuracy

4 Phase Configuration F

FSW = 810 kHz

all range −10 +10

ENABLE INPUT

Input Leakage

EN = 0 V or VCC I

Upper Threshold V

Lower Threshold V

DRON

Output High Voltage

Output Low Voltage

Rise Time

Sourcing 500 mA

Sinking 500 mA

Cl(PCB) = 20 pF,
DV

Fall Time

Cl(PCB) = 20 pF,
DVO = 10% to 90%

Internal Pull-up Resistance R

Internal Pull-down Resistance VCC = 0 V R

Test Conditions Symbol Min Typ Max Unit

= 10% to 90%

O

Symbol Min Ty p Max Unit

R

θJA

J

A

STG

= 0.1 mF)

VCC

PULL_DOWN

− 68 −

°C/W

−40 − 150

−40 − 105

−55 − 150

_C

_C

_C

VRMP 4.5 20 V

RMPrise

RMPfall

RMPhyst

3 V

800 mV

4.2 V

VCC 4.6 5.4 V

ICC

Rise

Fall

Hyst

SW

DF

SW

L

IH

IL

V

OH

V

OL

t

R

t

F

PULL−UP

4 V

200 mV

250 1200 kHz

−4 +4

−1.0 1.0

1.2 V

3.0 V

160 ns

3 ns

2.0

40

4.5 V

0.6 V

0.1 V

70

mA

%

mA

kW

kW

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6

NCV81277A

Table 4. ELECTRICAL CHARACTERISTICS (continued)

(Unless otherwise stated: −40°C < TA < 105°C; 4.6 V < VCC < 5.4 V; C

Parameter UnitMaxTypMinSymbolTest Conditions

PGOOD

I

Output Low Voltage

Leakage Current P

= 10 mA (Sink) V

PGOOD

= 5 V I

GOOD

Output Voltage Initialization Time From EN to DRON T_init 1.5 ms

Minimum Output Voltage Ramp

REFIN = 1.0 V T_ramp

Time

Maximum Output Voltage Ramp

REFIN = 1.0 V T_ramp

Time

PROTECTION-OCP, OVP, UVP

Under Voltage Protection (UVP)

Relative to REFIN Voltage UVP 250 300 350 mV

Threshold

Under Voltage Protection (UVP)
Delay

Over Voltage Protection (OVP)

Relative to REFIN Voltage OVP 360 400 430 mV

Threshold

Over Voltage Protection (OVP)
Delay

Over Current Protection (ILIM) internal current source ILIM

PWM OUTPUTS

Output High Voltage

Sourcing 500 mA

Output Mid Voltage V

Output Low Voltage

Rise and Fall Time

Sinking 500 mA

CL(PCB) = 50 pF, DVO = 10% to
90% of VCC

Tri-state Output Leakage Gx = 2.0 V, x = 1−8, EN = Low I

Minimum On Time FSW = 600 kHz To n 12 ns

0% Duty Cycle Comp Voltage when PWM Outputs

Remain LOW

100% Duty Cycle Comp Voltage when PWM Outputs

Remain HIGH

PWM Phase Angle Error Between Adjacent Phases ø ±15 °

PHASE DETECTION

Phase Detection Threshold Volt-

CSP2 to CSP4 V

age

Phase Detect Timer CSP2 to CSP4 T

ERROR AMPLIFIER

Input Bias Current

Open Loop DC Gain CL = 20 pF to GND,

= 10 kW to GND

R

L

Open Loop Unity Gain Bandwidth CL = 20 pF to GND,

= 10 kW to GND

R

L

Slew Rate

Maximum Output Voltage I

Minimum Output Voltage I

DVIN = 100 mV, G = −10 V/V,

= 0.75–1.52 V, CL = 20 pF

DV

OUT

to GND, R

SOURCE

SINK

= 10 kW to GND

L

= 2 mA V

= 2 mA V

VCC

= 0.1 mF)

OL

T

UVP

T

OVP

V

OH

MID

V

OL

tR, t

VCOMP

VCOMP

PHDET

PHDET

I

BIAS

G

L

L

OL

MIN

MAX

0.15 ms

10 ms

5

5

th

9.5 10 10.5

VCC − 0.2 V

1.9 2.0 2.1 V

F

10 ns

−1.0 1.0

0%

100%

1.3 V

2.5 V

1.1 ms

−400 400 nA

80 dB

0.4 V

0.2

0.7 V

VCC − 0.1 V

GBW 20 MHz

SR 5

OUT

OUT

3.5 V

1 V

V/ms

mA

ms

ms

mA

mA

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7

NCV81277A

Table 4. ELECTRICAL CHARACTERISTICS (continued)

(Unless otherwise stated: −40°C < TA < 105°C; 4.6 V < VCC < 5.4 V; C

Parameter UnitMaxTypMinSymbolTest Conditions

DIFFERENTIAL SUMMING AMPLIFIER

Input Bias Current

VSP Input Voltage V

VSN Input Voltage V

−3dB Bandwidth CL = 20 pF to GND,
= 10 kW to GND

R

L

Closed Loop DC Gain

VSP to VSN = 0.5 to 1.3 V G 1 V/V

(VSP−VSN to DIFF)

Droop accuracy CSREF − DROOP = 80 mV,

V

= 0.8 V to 1.2 V

REFIN

Maximum Output Voltage I

Minimum Output Voltage I

= 2 mA V

SOURCE

= 2 mA V

SINK

CURRENT SUMMING AMPLIFIER

Offset Voltage

Input Bias Current CSSUM = CSREF = 1 V I

Open Loop Gain G 80 dB

Current sense Unity Gain Band­width

Maximum CSCOMP Output Volt­age

Minimum CSCOMP Output Voltage I

CL = 20 pF to GND,

= 10 kW to GND

R

L

I

= 2 mA V

SOURCE

= 2 mA V

SINK

CURRENT BALANCE AMPLIFIER

Input Bias Current

Common Mode Input Voltage

CSPX − CSP

CSPX = CSREF V

= 1.2 V I

X+1

Range

Differential Mode Input Voltage

CSREF = 1.2 V V

Range

Closed Loop Input Offset Voltage
Matching

CSPX = 1.2 V, Measured from the
Average

Current Sense Amplifier Gain 0 V < CSPX < 0.1 V G 5.7 6.0 V/V

Multiphase Current Sense Gain

CSREF = CSP = 10 mV to 30 mV

Matching

−3dB Bandwidth BW 8 MHz

IOUT

Input Reference Offset Voltage

Output Current Max

Current Gain

ILIM to CSREF V

ILIM Sink Current 20 mA

IOUT/ILIM, R

= 5 kW

R

IOUT

= 20 kW,

LIM

VOLTAGE REFERENCE

I

VREF Reference Voltage

VREF Reference accuracy T

= 1 mA VREF 1.98 2 2.02 V

REF

< TJ < T

JMIN

JMAX

VCC

= 0.1 mF)

I

BIAS

IN

IN

−400 400 nA

0 2 V

−0.3 0.3 V

BW 27 MHz

DDROOP

OUT

OUT

V

OS

L

78 82 mV

3 V

0.8 V

−500 500

−7.5 7.5

GBW 10 MHz

OUT

OUT

BIAS

CM

DIFF

3.5 V

0.1 V

−50 50 nA

0 2 V

−100 100 mV

−1.5 1.5 mV

DG

I

OUT

OS

−3 3 %

−3 +3 mV

200

G 9.5 10 10.5 A/A

DVREF

1 %

mV

mA

mA

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8

NCV81277A

Table 4. ELECTRICAL CHARACTERISTICS (continued)

(Unless otherwise stated: −40°C < TA < 105°C; 4.6 V < VCC < 5.4 V; C

Parameter UnitMaxTypMinSymbolTest Conditions

PSI

PSI High Threshold

PSI Mid threshold V

PSI Low threshold V

PSI Input Leakage Current V

= 0 V I

PSI

PWM_VID BUFFER

Upper Threshold

Lower Threshold V

PWM_VID Switching Frequency F

Output Rise Time t

Output Fall Time t

Rising and Falling Edge Delay

Propagation Delay tPD = t

Propagation Delay Error

Dt = tR − t

PDHL

DtPD = t

F

PDHL

= t

− t

PDLH

PDLH

REFIN

REFIN Discharge Switch
ON-Resistance

Ratio of Output Voltage Ripple
Transferred from REFIN/REFIN
Voltage Ripple

I

REEFIN(SINK)

F

PWM_VID

F

≤ 600 kHz

SW

F

PWM_VID

F

≤ 600 kHz

SW

= 2 mA R

= 400 kHz,

= 1000 kHz,

I2C

Logic High Input Voltage

From 10% to 90% V

Logic Low Input Voltage From 10% to 90% V

Hysteresis (Note 4) 80 mV

Output Low Voltage I

= −6mA V

SDA

Input Current I

Input Capacitance (Note 4) C

Clock Frequency

See Figure 4

SCL Low Period (Note 4) t

SCL High Period (Note 4) t

SCL/SDA Rise Time (Note 4) t

SCL/SDA Fall Time (Note 4) t

Start Condition Setup Time
(Note 4)

Start Condition Hold Time
(Note 1, 4)

Data Setup Time (Note 2, 4) t

Data Hold Time (Note 2, 4) t

Stop Condition Setup Time
(Note 3, 4)

Bus Free Time between Stop
and Start (Note 4)

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

1. Time from 10% of SDA to 90% of SCL.

2. Time from 10% or 90%of SDA to 10% of SCL.

3. Time from 90% of SCL to 10% of SDA.

4. Guaranteed by design, not production tested.

VCC

= 0.1 mF)

V

MID

V

PWM_VID

Dt

t

PD

Dt

DISCH

V

ORP/VREFIN

V

ORP/VREFIN

SDA

f

SCL

LOW

HIGH

t

SU;STA

t

HD;STA

SU;DAT

HD;DAT

t

SU;STO

t

BUF

IH

L

IH

R

F

PD

IH

IL

OL

L

, C

R

F

1.45 V

0.8 1 V

IL

−1 1

0.575 V

mA

1.21 V

IL

0.575 V

400 5000 kHz

3 ns

3 ns

0.5 ns

8 ns

0.5 ns

10

10

W

%

30

1.7 V

0.5 V

0.4 V

SCL

−1 1

5 pF

mA

400 kHz

1.3

0.6

ms

ms

300 ns

300 ns

600 ns

600 ns

100 ns

300 ns

600 ns

1.3

ms

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9

NCV81277A

SCLK

SDATA

t

t

HD:DAT

R

t

HIGH

t

LOW

t

HD:STA

t

BUF

STOP START START STOP

t

SU:DAT

t

F

t

SU:STA

t

HD:STA

t

SU:STO

Figure 4. I2C Timing Diagram

EN

VOUT

PGOOD

T_init

T_ramp

Figure 5. Soft Start Timing Diagram

Applications Information

The NCV81277A is a buck converter controller
optimized for the next generation computing and graphic
processor applications. It contains four PWM channels
which can be individually configured to accommodate buck
converter configurations up to four phases. The controller
regulates the output voltage all the way down to 0 V with no
load. Also, the device is functional with input voltages as
low as 3.3 V.

The output voltage is set by applying a PWM signal to the
PWM_VID input of the device. The controller converts the
PWM_VID signal with variable high and low levels into
a constant amplitude PWM signal which is then applied to
the REFIN pin. The device calculates the average value of
this PWM signal and sets the regulated voltage accordingly.

The output voltage is differentially sensed and subtracted
from the REFIN average value. The result is biased up to

1.3 V and applied to the error amplifier. Any difference

between the sensed voltage and the REFIN pin average
voltage will change the PWM outputs duty cycle until the
two voltages are identical. The load current is current is
continuously monitored on each phase and the PWM
outputs are adjusted to ensure adjusted to ensure even
distribution of the load current across all phases. In addition,
the total load current is internally measured and used to
implement a programmable adaptive voltage positioning
mechanism.

The device incorporates overcurrent, under and

overvoltage protections against system faults.

The communication between the NCV81277A and the
user is handled with two interfaces, PWM_VID to set the
output voltage and I

2

C to configure or monitor the status of
the controller. The operation of the internal blocks of the
device is described in more details in the following sections.

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10

NCV81277A

VID_BUFF VREF VCC EN

REF UVLO & EN

PWM_VID

DIFFOUT

PGOOD

REFIN

FB

COMP

PGOOD

Comparator

−

+

1.3V

Mux

EN

VSP
VSN

OVP

OVP

PSI

OCP

1.3V

EN

+

−

VSP

VSN

Measurment , ILIM & OCP

S

S

Soft start

Total Output Current

LLTH

LLTH

+

−

VSP

VSN

CSCOMP

CSREF

CSSUM

ILIM

IOUT

SDA

SCL

FSW

VRMP

PSI

FSW

CSP1 to CSP4

LLTH/I2C_ADD

PWM

Generators

GND LLTH/I2C_ADD

ADC

Data

Registers

Control

Interface

Ramp

Generators

OVP

OCP

IOUT

PWM1 to PWM4

Ramp1
Ramp2
Ramp3

Ramp4

EN

Figure 6. NCV81277A Functional Block Diagram

IPH1
IPH2
IPH3
IPH4

Current Balance

Amplifiers

and

per Phase OCP

Comparators

Power State

Stage

CSP1
CSP2
CSP3

CSP4

PWM1/PHTH4
PWM2/PHTH3
PWM3/PHTH2

PWM4/PHTH1
LPC2

LPC1

OCP
SS

DRON

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11

NCV81277A

F

PWM_VID Interface

PWM_VID is a single wire dynamic voltage control
interface where the regulated voltage is set by the duty cycle
of the PWM signal applied to the controller.

The device controller converts the variable amplitude
PWM signal into a constant 2 V amplitude PWM signal
while preserving the duty cycle information of the input
signal. In addition, if the PWM_VID input is left floating,
the VID_BUFF output is tri-stated (floating).

The constant amplitude PWM signal is then connected to
the REFIN pin through a scaling and filtering network (see
Figure 7). This network allows the user to set the minimum
and maximum REFIN voltages corresponding to 0% and
100% duty cycle values.

VCC

0.1 mF

PWM_VID

Internal

precision

reference

= 2 V

V

REF

Controller

VREF

VID_BUFF

R3

GND

REFIN

R1

R2

10n

C1

Figure 7. PWM_VID Interface

The minimum (0% duty cycle), maximum (100% duty
cycle) and boot (PWM_VID input floating) voltages can be
calculated with the following formulas:

1 )

R1@ǒR2)R

1 )

@

REF

1

R

1@R3

R2@ǒR1)R

1

R2@R

3

1

R

1

1 )

R

2

(eq. 1)

Ǔ

3

Ǔ

3

(eq. 2)

(eq. 3)

Soft Start

V

+ V

BOOT

REF

REF

@

@

+ V

V

MAX

MIN

+ V

V

Soft start is defined as the transition from Enable assertion
high to the assertion of Power good as shown in Figure 5.

The output is set to the desired voltage in two steps, a fixed
initialization step of 1.5 ms followed by a ramp-up step
where the output voltage is ramped to the final value set by
the PWM_VID interface. During the soft start phase,
PGOOD pin is initially set low and will be set high when the
output voltage is within regulation and the soft start ramp is
complete. The PGOOD signal only de-asserts (pull low)
when the controller shuts down due to a fault condition
(UVLO, OVP or OCP event).

The output voltage ramp-up time is user settable by
connecting a resistor between pin SS and GND. The
controller will measure the resistance value at power-up by
sourcing a 10 mA current through this resistor and set the
ramp time (t

) as shown in Table 16. When a fast SS ramp

ramp

is selected, external filtering should ensure REFIN signal
settled before the PGOOD signal asserted.

Remote Voltage Sense

A high performance true differential amplifier allows the
controller to measure the output voltage directly at the load
using the VSP (VOUT) and VSN (GND) pins. This keeps
the ground potential differences between the local controller
ground and the load ground reference point from affecting
regulation of the load. The output voltage of the differential
amplifier is set by the following equation:

V

DIFOUT

+ǒV

ǒ

)

VSP

V

DROOP

* V

VSN

) V

CSREF

Ǔ

)ǒ1.3 V * V

Ǔ

REFIN

Ǔ

)

(eq. 4)

Where:

V

DIFOUT

V

VSP

is the output voltage of the differential amplifier.

− V

is the regulated output voltage sensed at the

VSN

load.

V

is the voltage at the output pin set by the

REFIN

PWM_VID interface.

V

DROOP

− V

is the expected drop in the regulated

CSREF

voltage as a function of the load current (load-line).

1.3 V is an internal reference voltage used to bias the

amplifier inputs to allow both positive and negative

output voltage for V

Error Amplifier

DIFOUT

.

A high performance wide bandwidth error amplifier is
provided for fast response to transient load events. Its
inverting input is biased internally with the same 1.3 V
reference voltage as the one used by the differential sense
amplifier to ensure that both positive and negative error
voltages are correctly handled.

An external compensation circuit should be used (usually
type III) to ensure that the control loop is stable and has
adequate response.

Ramp Feed-Forward Circuit

The ramp generator circuit provides the ramp used to
generate the PWM signals using internal comparators (see
Figure 8) The ramp generator provides voltage
feed-forward control by varying the ramp magnitude with
respect to the VRMP pin voltage. The PWM ramp time is
changed according to the following equation:

V

RAMPpk+pk

+ 0.1 @ V

pp

VRMP

(eq. 5)

The VRMP pin also has a UVLO function. The VRMP
UVLO is only active after the controller is enabled. The

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12

NCV81277A

VRMP pin is high impedance input when the controller is
disabled.

V

IN

V

Comp-IL

Duty

Figure 8. Ramp Feed-Forward Circuit

PWM Output Configuration

ramp_pp

By default the controller operates in 4 phase mode,
however with the use of the CSP pins the phases can be
disabled by connecting the CSP pin to VCC. At power-up
the NCV81277A measures the voltage present at each CSP
pin and compares it with the phase detection threshold. If the
voltage exceeds the threshold, the phase is disabled. The
phase configurations that can be achieved by the device are
listed in Table 6. The active phase (PWM

) information is

X

also available to the user in the phase status register.

PSI, LPCX, PHTH

X

The NCV81277A incorporates a power saving interface
(PSI) to maximize the efficiency of the regulator under
various loading conditions. The device supports up to six
distinct operation modes, called power zones using the PSI,
LPC

and PHTHX pins (see Table 7). At power-up the

X

controller reads the PSI pin logic state and sources a 10 mA
current through the resistors connected to the LPC
PHTH

pins, measures the voltage at these pins and

X

X

and

configures the device accordingly.

The configuration can be changed by the user by writing
to the LPC

and PHTHX configuration registers.

X

After EN is set high, the NCV81277A ignores any change
in the PSI pin logic state until the output voltage reaches the
nominal regulated voltage.

When PSI = High, the controller operates with all active
phases enabled regardless of the load current. If PSI = Mid,
the NCV81277A operates in dynamic phase shedding mode
where the voltage present at the IOUT pin (the total load
current) is measured every 10 ms and compared to the
PHTH

thresholds to determine the appropriate power

X

zone.

The resistors connected between the PHTH

and GND

X

should be picked to ensure that a 10 mA current will match
the voltage drop at the IOUT pin at the desired load current.
Please note that the maximum allowable voltage at the

IOUT pin at the maximum load current is 2 V. Any PHTH
threshold can be disabled if the voltage drop across the
PHTH

resistor is ≥ 2 V for a 10 mA current, the pin is left

X

floating or 0xFF is written to the appropriate PHTH
configuration register.

At power-up, the automatic phase shedding mode is only
enabled after the output voltage reaches the nominal
regulated voltage.

When PSI = Low, the controller is set to a fixed power
zone regardless of the load current. The LPC2 hardware
setting controls the power zone when EN is turned on and
PSI=low. If PSI stays low, its power zone can be further
changed by the I2C register 0x36, Bit[5:3] if the secondary
function is enabled. If PSI transitions to other levels (Mid or
High) and back to Low level when the device is enabled, the
power zone control will switch to LPC1 configuration
hardware setting or I2C register 0x36, Bit[2:0] if the
secondary function is enabled.

LLTH/I2C_ADD

The LLTH/I2C_ADD pin enables the user to change the
percentage of the externally programmed droop that takes
effect on the output. In addition, the LLTH/I2C_ADD pin
sets the I

2

C slave address of the NCV81277A. The

maximum load line is controlled externally by setting the
gain of the current sense amplifier. On power up a 10 mA
current is sourced from the LLTH/I2C_ADD pin through a
resistor and the resulting voltage is measured. The load line

2

and I

C slave address configurations achievable using the
external resistor is listed in the table below. The percentage
load line can be fine-tuned over the I

2

C interface by writing

to the LL configuration register.

Table 5. LLTH/I2C_ADD PIN SETTING

Resistor

(kW)

10

23.2 0 0x20

37.4 100 0x30

54.9 0 0x30

78.7 100 0x40

110 0 0x40

147 100 0x50

249 0 0x50

NOTE: 1% tolerance.

Load Line

(%)

100 0x20

Slave Address

(Hex)

X

X

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13

NCV81277A

Table 6. PWM OUTPUT CONFIGURATION

(3 = Normal Connection, X = Tied to VCC)

Configuration

1 4 Phase

2 3 Phase

3 2 Phase

4 1 Phase

Phase

Configuration

CSP1 CSP2 CSP3 CSP4

3 3 3 3

3 3 3

3 3

3

Table 7. PSI, LPCX, PHTHX CONFIGURATION (Note 1)

PSI

Logic

State

High Disabled

Low

Mid Function

1. 1% tolerance.

2. Power zone 4 is DCM @100 kHz switching frequency, while zones 0 to 3 are CCM.

LPC

X

Resistor

(kW)

10 0 0 0 0

23.2 0 0 0 0

37.4 2 0 0 0

54.9 3 3 3 0

78.7 4 4 4 4

Disabled

IOUT vs. PHTHX Comparison

Function Disabled

IOUT > PHTH4 0 0 0 0

PTHT4 > IOUT > PHTH3 0 0 0 0

PHTH3 > IOUT > PHTH2 2 0 0 0

PHTH2 > IOUT > PHTH1 3 3 3 0

IOUT < PHTH1 4 4 4 4

CSP Pin Configuration

X X X 1

4 Phase 3 Phase 2 Phase 1 Phase

0 0 0 0

Enabled

PWM Outputs

(PWM

1, 2, 3, 4

X 1, 2, 3

X X 1, 2

Power Zone (Note 2)

Pins)

X

Table 8. PHASE SHEDDING CONFIGURATIONS

Power Zone PWM Output Configuration

0

2

3

4

0

3

4

0

3

4

0

4

4 Phase

3 Phase

2 Phase

1 Phase

PWM Output Status (3 = Enabled, X = Disabled)

PWM1 PWM2 PWM3 PWM4

3 3 3 3

3

3

3

3 3 3

3

3

3 3

3

3

3

3

X

X X X

X X X

X X X

X X X

X X X

X X X

X X X

X X X

3

X X

X

X

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14

NCV81277A

Power Zone Transition/Phase Shedding

The power zones supported by the NCV81277A are set by
the resistors connected to the LPC
PHTH

pins (PSI = Mid).

X

pins (PSI = Low) or

X

When PSI is set to the Mid-state, the NCV81277A
employs a phase shedding scheme where the power zone is
automatically adjusted for optimal efficiency by
continuously measuring the total output current (voltage at
the IOUT pin) and compare it with the PHTH

thresholds.

X

When the comparison result indicates that a lower power
zone number is required (an increase in the IOUT value), the
controller jumps to the required power zone immediately.
A decrease in IOUT that indicates that the controller needs
to switch into a higher power zone number, the transition
will be executed with a delay of 200 ms set by the phase shed
delay configuration register. The value of the delay can be
adjusted by the user in steps of 10 ms if required. To avoid
excessive ripple on the output voltage, all power zone
changes are gradual and include all intermediate power
zones between the current zone and the target zone set by the
comparison of the output current with the PHTH
thresholds, each transition introducing a programmable
200 ms delay. To avoid false changes from one power zone
to another caused by noise or short IOUT transients, the
comparison between IOUT and PHTH

threshold uses

X

hysteresis. The switch to a lower power zone is executed if
IOUT exceeds the PHTH

threshold values while

X

a transition to a higher power zone number is only executed
if IOUT is below PHTH

-Hysteresis value. The hysteresis

X

value is set to 0x10h and can be changed by the user by
writing to the phase shedding configuration register. If
a power zone/PHTHX threshold is disabled, the controller
will skip it during the power zone transition process.

When PSI = Low and the user requires to change the
power zone, the transition to the new power zone is identical
to the transition process used when PSI is set to the
Mid-state. The only exception is when the target power zone
is disabled in automatic phase shedding mode. In this case,
the controller will automatically enable the target power
zone and allow the transition. When the controller is set to
automatic phase shedding, the power zone will be
automatically disabled.

Switching Frequency

A programmable precision oscillator is provided. The
clock oscillator serves as the master clock to the ramp
generator circuit. This oscillator is programmed by a resistor
to ground on the FSW pin. The FSW pin provides
approximately 2 V out and the source current is mirrored
into the internal ramp oscillator. The oscillator frequency is
approximately proportional to the current flowing in the
resistor. Table 19 lists the switching frequencies that can be
set using discrete resistor values for each phase
configuration. Also, the switching frequency information is
available in the FSW configuration register and it can be
changed by the user by writing to the FSW configuration
register.

Total Current Sense Amplifier

The controller uses a patented approach to sum the phase
currents into a single temperature compensated total current
signal (Figure 9).

This signal is then used to generate the output voltage
droop, total current limit, and the output current monitoring
functions. The total current signal is floating with respect to
CSREF. The current signal is the difference between
CSCOMP and CSREF. The REF(n) resistors sum the signals
from the output side of the inductors to create a low
impedance virtual ground.

The amplifier actively filters and gains up the voltage
applied across the inductors to recover the voltage drop
across the inductor series resistance (DCR). RTH is placed
near an inductor to sense the temperature of the inductor.
This allows the filter time constant and gain to be a function
of the NTC’s resistance (RTH) and compensate for the
change in the DCR with temperature.

The DC gain equation for the current sensing:

X

V

CSCOMP*CSREF

RREF1

CSN1

CSN4

RREF4

SWN1

RPH1

SWN4

RPH4

Figure 9. Total Current Summing Amplifier

RCS2 )

+*

CREF

CSREF

CSSUM

CCS

RCS2

RCS1@RTH

RCS1)RTH

RPH

Controller

+

−

CSCOMP

RCS1

@ I

+

−

RILIM

RTH

Set the gain by adjusting the value of the RPH resistors.
The DC gain should be set to the output voltage droop. If the
voltage from CSCOMP to CSREF is less than 100 mV at the
maximum output current IOUT

then it is recommend

MAX

increasing the gain of the CSCOMP amp. This is required to
provide a good current signal to offset voltage ratio for the
ILIMIT pin. The NTC should be placed near the inductor
used by phase 1. The output voltage droop should be set with
the droop filter divider.

The pole frequency in the CSCOMP filter should be set
equal to the zero from the output inductor. This allows the
circuit to recover the inductor DCR voltage drop current
signal. It is best to fine tune this filter during transient
testing.

DCR@25C

FZ+

2 @ p @ L

Phase

ILIM

OUT

Total

VCC

1:10

(eq. 6)

@ DCR

IOUT

RIMON

(eq. 7)

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15

NCV81277A

Programming the Current Limit ILIM

The current limit thresholds are programmed with
a resistor between the ILIMIT and CSCOMP pins. The
ILIMIT pin mirrors the voltage at the CSREF pin and
mirrors the sink current internally to IOUT (reduced by the
IOUT Current Gain) and the current limit comparators. The
100% current limit (CLIM1) trips if the ILIMIT sink current
exceeds 10 mA for 50 ms. The 150% current limit (CLIM2)
trips with minimal delay if the ILIMIT sink current exceeds
15 mA. Set the value of the current limit resistor based on the
CSCOMP−CSREF voltage as shown below.

V

RILIM +

CSCOMP*CSREF@ILIMIT

10 mA

(eq. 8)

or

RCS2)

RILIM +

RCS1@RTH

RCS1)RTH

RPH

10 mA

@ I

OUT

LIMIT

@ DCR

(eq. 9)

When PSI=low, current limit threshold will be scaled
down according to its remaining phase count in the power
zone: e.g. Iout_limit_2ph=2*Iout_limit/N. In this case total
phase number N=4.

Programming DROOP

The signals CSCOMP and CSREF are differentially
summed with the output voltage feedback to add precision
voltage droop to the output voltage.

ǒ

Droop + DCR @

RCS1 ø RTHǓ) RCS2

RPH

(eq. 10)

Programming IOUT

The IOUT pin sources a current in proportion to the
ILIMIT sink current. The voltage on the IOUT pin is
monitored by the internal A/D converter and should be
scaled with an external resistor to ground such that a load
equal to system max current generates a 2 V signal on IOUT.
A pull-up resistor to VCC can be used to offset the IOUT
signal positive if needed.

R

IOUT

+

RCS2)

10 @

2.0 V @ RILIM

RCS1@RTH

RCS1)RTH
RPH

@ I

OUT

MAX

@ DCR

(eq. 11)

the value of the current limit resistor based on the
CSCOMP−CSREF voltage as shown in the Programming
the Current Limit ILIM section.

In addition to the total current protection, the device
incorporates an OCP function on a per phase basis
(CLIM_phase) by continuously monitoring the
CSPX−CSREF voltage. The per-phase OCP limit is selected
on startup when a 10 mA current is sourced from the OCP.
The resulting voltage read on the pin selects both the max per
phase current and delay time (see Table 9). These can also
be programmed over I

Table 9. PER PHASE OCP SETTINGS

Resistance

(kW)

10 65 4

14.7 75 4

20 100 4

26.1 134 4

33.2 65 6

41.2 75 6

49.9 100 6

60.4 134 6

71.5 65 8

84.5 75 8

100 100 8

118.3 134 8

136.6 65 10

157.7 75 10

182.1 100 10

249 134 10

NOTE: 1% tolerance.

Under Voltage Lock-Out (VCC UVLO)

2

C (see Table 17).

Per Phase Voltage

(mV)

Latch Off Delay

(ms)

VCC is constantly monitored for the under voltage
lockout (UVLO) During power up both the VRMP and the
VCC pin are monitored Only after both pins exceed their
individual UVLO threshold will the full circuit be activated
and ready for the soft start ramp.

PROTECTIONS

OCP

The device incorporates an over current protection
mechanism to shut down and latch off to protect against
damage due to an over current event. The current limit
threshold set by the ILIM pin on a full system basis.

The current limit thresholds are programmed with
a resistor between the ILIMIT and CSCOMP pins. The
ILIMIT pin mirrors the voltage at the CSREF pin and
mirrors the sink current internally to IOUT (reduced by the
IOUT Current Gain) and the current limit comparators. Set

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Over Voltage Protection

An output voltage monitor is incorporated into the
controller. Over voltage protection will be tripped under the
following situations: for REFIN below 1.6V, if the output
voltage is 400 mV over the REFIN value; for REFIN over

1.6 V, as long as the output is above 2 V, the output will be
clamped to 2 V before being discharged. Once the over
voltage protection trips, the PGOOD pin will be pulled low,
but DRON will stay high. PWM outputs will only be
allowed to toggle between mid and low to discharge the

16

NCV81277A

output. The PWM output high will remain disabled until the
power is cycled or the EN pin is toggled.

Under Voltage Protection

An under voltage protection will be tripped if the output
is 300 mV below the REFIN voltage. When under voltage
protection trips, the PGOOD pin will be pulled low, the
DRON will stay high. PWM outputs will only be allowed to
toggle between mid and low to discharge the output. The
PWM output high will remain disabled until the power is
cycled or the EN pin is toggled.

I2C Interface

The controller is connected to this bus as a slave device,
under the control of a master controller.

Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, because a low-to-high
transition when the clock is high might be interpreted as
a stop signal. The number of data bytes that can be
transmitted over the serial bus in a single read or write
operation is limited only by what the master and slave
devices can handle.

The serial bus protocol operates as follows:

1. The master initiates data transfer by establishing
a START condition, defined as a high-to-low
transition on the serial data line SDA while the serial
clock line, SCL, remains high. This indicates that an
address/data stream will follow. All slave
peripherals connected to the serial bus respond to the
START condition, and shift in the next eight bits,
consisting of a 7-bit address (MSB first) plus an R/W
bit, which determines the direction of the data
transfer, i.e., whether data will be written to or read
from the slave device. The peripheral whose address
corresponds to the transmitted address responds by
pulling the data line low during the low period before
the ninth clock pulse, known as the Acknowledge
Bit. All other devices on the bus now remain idle
while the selected device waits for data to be read
from or written to it. If the R/W bit is a 0, the master
will write to the slave device. If the R/W bit is a 1, the
master will read from the slave device.

2. Data is sent over the serial bus in sequences of nine
clock pulses, eight bits of data followed by an
Acknowledge Bit from the slave device. Transitions
on the data line must occur during the low period of
the clock signal and remain stable during the high
period, as a low-to-high transition when the clock is
high may be interpreted as a STOP signal. The
number of data bytes that can be transmitted over the
serial bus in a single READ or WRITE operation is

limited only by what the master and slave devices
can handle.

3. When all data bytes have been read or written, stop
conditions are established. In WRITE mode, the
master will pull the data line high during the 10
clock pulse to assert a STOP condition. In READ
mode, the master device will override the
acknowledge bit by pulling the data line high during
the low period before the ninth clock pulse. This is
known as No Acknowledge. The master will then
take the data line low during the low period before
the tenth clock pulse, then high during the tenth
clock pulse to assert a STOP condition.

4. Any number of bytes of data may be transferred over
the serial bus in one operation, but it is not possible
to mix read and write in one operation because the
type of operation is determined at the beginning and
cannot subsequently be changed without starting
a new operation. To write data to one of the device
data registers or read data from it, the Address
Pointer Register must be set so that the correct data
register is addressed, and then data can be written
into that register or read from it. The first byte of
a write operation always contains an address that is
stored in the Address Pointer Register. If data is to be
written to the device, the write operation contains
a second data byte that is written to the register
selected by the address pointer register. The device
address is sent over the bus followed by R/W set to

0. This is followed by two data bytes. The first data
byte is the address of the internal data register to be
written to, which is stored in the Address Pointer
Register. The second data byte is the data to be
written to the internal data register.

READ A SINGLE WORD

The master device asserts the start condition. The master
then sends the 7-bit slave address. It is followed by a R/W
bit that indicates the direction of operation, which will be
a write operation in this case. The slave whose address is on
the bus acknowledges it by an ACK signal on the bus (by
holding SDA line low). The master then sends register
address on the bus. The slave device accepts it by an ACK.
The master then asserts a repeated start condition followed
by a 7-bit slave address. The master then sends a direction
bit R/W which is Read for this case. Controller
acknowledges it by an ACK signal on the bus. This will start
the read operation and controller sends the high byte of the
register on the bus. Master reads the high byte and asserts an
ACK on the SDA line. Controller now sends the low byte of
the register on the SDA line. The master acknowledges it by
a no acknowledge NACK on the SDA line. The master then
asserts the stop condition to end the transaction.

th

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17

NCV81277A

S 0 ACKSr 1 PNACKACK ACKSlave Address Register Address Slave Address Register Data

= Generated by the Master

= Generated by the Slave

READING THE SAME REGISTERS
MULTIPLE TIMES

The master device asserts the start condition. The master
then sends the 7-bit slave address. It is followed by a R/W
bit that indicates the direction of operation, which will be
a write operation in this case. The slave whose address is on
the bus acknowledges it by an ACK signal on the bus
(holding SDA line low). The master then sends register
address on the bus. The slave device accepts it by an ACK.
The master then asserts a repeated start condition followed
by a 7-bit slave address. The master then sends a direction
bit R/W which is Read for this case. Slave device
acknowledges it by an ACK signal on the bus. This will start
the read operation:

S Slave Address 0 ACK Register Address Sr Slave AddressACK 1 ACK RD1 NACK PACK RD2 ACK RDN

= Generated by the Master

= Generated by the Slave

S = Start Condition

P = Stop Condition

S = Start Condition

P = Stop Condition

Figure 10. Single Register Read Operation

Sr = Repeated Start Condition

ACK/NACK = Acknowledge/No Acknowledge

1. The slave device sends the high byte of the register
on the bus.

2. The master reads the high byte and asserts an ACK
on the SDA line.

3. The slave device now sends the low byte of the
register on the SDA line.

4. The master acknowledges it by an ACK signal on the
SDA line.

5. The master and slave device keeps on repeating steps
1−4 until the low byte of the last reading is
transferred. After receiving the low byte of the last
register, the master asserts a not acknowledge
NACK on the SDA. The master then asserts a stop
condition to end the transaction.

Sr = Repeated Start Condition

ACK/NACK = Acknowledge/No Acknowledge

RD1…N = Register Data 1…N

Figure 11. Multiple Register Read Operation

WRITING A SINGLE WORD

The master device asserts the start condition. The master
then sends the 7-bit to the slave address. It is followed by a
R/W bit that indicates the direction of operation, which will
be a write operation in this case. The slave whose address is
on the bus acknowledges it by an ACK signal on the bus (by
holding SDA line low). The master then sends register
address on the bus. The slave device accepts it by an ACK.

S Slave Address 0 ACK Register Address Register DataACK PACK

= Generated by the Master

= Generated by the Slave

Figure 12. Single Register Write Operation

S = Start Condition

P = Stop Condition

WRITING MULTIPLE WORDS TO
DIFFERENT REGISTERS

The master device asserts the start condition. The master
then sends the 7-bit slave address. It is followed by a bit
(R/W) that indicates the direction of operation, which will
be a write operation in this case. The slave whose address is

The master then sends a data byte of the high byte of the
register. The slave device asserts an acknowledge ACK on
the SDA line. The master then sends a data byte of the low
byte of the register. The slave device asserts an acknowledge
ACK on the SDA line. The master asserts a stop condition
to end the transaction.

ACK = Acknowledge

on the bus acknowledges it by an ACK signal on the bus (by
holding SDA line low).

The master then sends first register address on the bus.

The slave device accepts it by an ACK. The master then

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18

NCV81277A

sends a data byte of the high byte of the first register. The
slave device asserts an acknowledge ACK on the SDA line.
The master then sends a data byte of the low byte of the first
register. The slave device asserts an acknowledge ACK on
the SDA line.

The master then sends the second register address on the
bus. The slave device accepts it by an ACK. The master then

slave device asserts an acknowledge ACK on the SDA line.
The master then sends a data byte of the low byte of the
second register. The slave device asserts an acknowledge
ACK on the SDA line.

A complete word must be written to a register for proper
operation. It means that both high and low bytes must be
written.

sends a data byte of the high byte of the second register. The

S Slave Address 0 ACK RA1 ACK PRD1 ACK RA2 ACK RD2 ACK RAN ACK RDN ACK

= Generated by the Master

= Generated by the Slave

Table 10. REGISTER MAP

Address

0x20 R/W 0xFF IOUT_OC_WARN_LIMIT

0x21 R 0x00 STATUS BYTE

0x22 R/W 0x00 Fault Mask

0x23 R 0x00 STATUS Fault

0x24 R 0x00 STATUS Warning

0x26 R 0x00 READ_IOUT

0x27 R 0x1A MFR_ID

0x28 R 0x76 MFR_MODEL

0x29 R 0x04 MFR_REVISION

0x2A R/W 0x00 Lock/Reset

0x2B R 0x00 Soft Start Status

0x2C N/A 0x00 Reserved

0x2D R Per phase OCP Status

0x2E R/W 0x00 Per phase OCP Configuration

0x2F R Switching Frequency Status

0x30 R/W 0x00 Switching Frequency Configuration

0x31 N/A 0x00 Reserved

0x32 R PSI Status

0x33 R Phase Status

0x34 R/W 0x1F LPC_Zone_enable

0x35 R LPC Status

0x36 R/W 0x00 LPC Configuration

0x38 R LL Status

0x39 R/W 0x03 LL Configuration

0x3A RW 0x00 PHTH1 Configuration

0x3B R PHTH1 Status

0x3C R/W 0x00 PHTH2 Configuration

0x3D R PHTH2 Status

0x3E R/W 0x00 PHTH3 Configuration

0x3F R PHTH3 Status

0x40 R/W 0x00 PHTH4 Configuration

0x41 R PHTH4 Status

0x44 R/W 0x08 Phase Shedding Hysteresis

S = Start Condition

P = Stop Condition

RD1…N = Register Data 1…N

ACK = AcknowledgeRA1…N = Register Address 1…N

Figure 13. Multiple Register Write Operation

R/W Default Value Description

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19

Table 10. REGISTER MAP (continued)

Address DescriptionDefault ValueR/W

0x45 R/W 0x14 Phase Shedding Delay

0x46 R/W 0x00 Second Function Configuration Register Latch A

0x47 R/W 0x00 Second Function Configuration Register Latch B

0x48 R DLT_READBACK_1, Die Level Traceability

0x49 R DLT_READBACK_2, Die Level Traceability

0x4A R DLT_READBACK_3, Die Level Traceability

0x4B R DLT_READBACK_4, Die Level Traceability

0x4C R DLT_READBACK_5, Die Level Traceability

NCV81277A

IOUT_OC_WARN_LIMIT Register (0x20)

This sets the high current limit. Once the READ_IOUT
register value exceeds this limit IOUT_OC_WARN_LIMIT
bit is set in the Status Warning register and an ALERT is
generated.

STATUS BYTE Register (0x21)

Table 11. STATUS BYTE REGISTER SETTINGS

Bits Name Description

7:6 Reserved N/A

5 VOUT_OV This bit gets set whenever the

NCV81277A goes into OVP mode.

4 IOUT_OC This bit gets set whenever the

NCV81277A latches off due to an over
current event.

0:3 Reserved N/A

Fault Mask Register (0x22)

Table 12. FAULT MASK REGISTER SETTINGS

Bits Name Description

7:5 Reserved

4 Clim1 When this bit is set, the Clim1 bit from

the STATUS FAULT register will not
be set.

3 Clim2 When this bit is set, the Clim2 bit from

the STATUS FAULT register will not
be set.

2 Clim_phase When this bit is set, the Clim_phase

bit from the STATUS FAULT register
will not be set.

1 OVP When this bit is set, the OVP bit from

the STATUS FAULT register will not
be set.

0 UVP When this bit is set, the UVP bit from

the STATUS FAULT register will not
be set.

STATUS Fault Register (0x23)

Table 13. STATUS FAULT REGISTER SETTINGS

Bits Name Description

7:5 Reserved N/A

4 Clim1 If not masked, this bit gets set when

3 Clim2 If not masked, this bit gets set when

2 Clim_phase If not masked, this bit gets set when

1 OVP If not masked, this bit is set when an

0 UVP If not masked, this bit is set when an

IOUT exceeds the ILIM value.

IOUT exceeds the ILIM value.

the phase Current (V
exceeds the OCP configuration value.

OVP event is detected.

UVP event is detected.

CSN−VCSREF

STATUS Warning Register (0x24)

Table 14. STATUS WARNING REGISTER SETTINGS

Bits Name Description

7:1 Reserved N/A

0 IOUT Overcurrent

Warning Reserved

This bit gets set if IOUT ex­ceeds its programmed high
warning limit(register 0x20).
This bit is only cleared when
EN is toggled.

READ_IOUT Register (0x26)

Read back output current. ADC conversion 0xFF = 2 V

on IOUT pin which should equate to max current.

Lock/Reset Register (0x2A)

Table 15. LOCK/RESET REGISTER SETTINGS

Bits Name Description

7:1 Reserved N/A

0 Lock Logic 1 locks all limit values to their

current settings. Once this bit is set,
all lockable registers become
read-only and cannot be modified un­til the NCV81277A is powered down
and powered up again. This prevents
rogue programs such as viruses from
modifying critical system limit settings
(Lockable).

)

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20

NCV81277A

Soft Start Status Register (0x2B)

This register contains the value that sets the slew rate of
the output voltage during power-up. When EN is set high,
the controller reads the value of the resistor connected to the
SS pin and sets the slew rate. The codes corresponding to
each resistor setting are shown in Table 16. The resistor
settings are updated on every rising edge of the EN signal.

Table 16. SOFT START STATUS REGISTER SETTINGS

T

RAMP

Resistor

(kW)

10

14.7 0001 0.3 0.24

20 0010 0.45 0.36

26.1 0011 0.6 0.48

33.2 0100 0.75 0.6

41.2 0101 0.9 0.72

49.9 0110 1 0.8

60.4 0111 2 1.6

71.5 1000 3 2.4

84.5 1001 4 3.2

100 1010 5 4

118.3 1011 6 4.8

136.6 1100 7 5.6

157.7 1101 8 6.4

182.1 1110 9 7.2

249 1111 10 8

NOTE: 1% tolerance.

Bits Name Value

− 7:4 Reserved N/A N/A N/A

3:0 T_Ramp

0000 0.15 0.12

T_ramp

(ms) ,

REFIN

=1 V

T_ramp

(ms),

REFIN

=0.8 V

Per Phase OCP Status Register and Configuration
Register (0x2D, 0x2E)

These registers contain the values that set the per phase
OCP current levels for each phase individually as well as the
latch off delay time for the OCP event. When EN is set high,
the controller reads the value of the resistor connected to the
OCP pin and sets the OCP threshold and latch off delay time
according to Table 9. The codes corresponding to each
setting are shown in Table 17. The resistor settings are
updated on every rising edge of the EN signal.

The OCP configuration register (0x2E) allows the user to
dynamically change the OCP threshold and latch off delay
through the I

2

C interface provided that the OCP bits from
the second function configuration registers A and B (0x46,
0x47) are set. In addition, the OCP levels and latch off delay
times can be adjusted independently when the OCP
configuration register is used. The achievable switching
frequency settings are listed in Table 17.

Table 17. OCP STATUS AND CONFIGURATION

REGISTER SETTINGS

Bits Name Description

7:4 Reserved N/A

3:2 Per Phase OCP Limit 00 = 65 mV

1:0 OCP_latch Off Delay 00 = 4 ms

01 = 75 mV
10 = 100 mV
11 = 134 mV

01 = 6 ms
10 = 8 ms
11 = 10 ms

Switching Frequency Status and Configuration
Registers (0x2F, 0x30)

These registers contain the values that set the switching
frequency of the controller. When EN is set high, the
controller reads the value of the resistor connected to the
FSW pin and sets the switching frequency according to
Table 19. The codes corresponding to each setting are also
shown in Table 19. The resistor settings are updated on
every rising edge of the EN signal.

The switching frequency configuration register allows the
user to dynamically change the switching frequency through

2

the I

C interface provided that the FSW bits from the second
function configuration registers A and B (0x46, 0x47) are
set.

PSI Status Register (0x32)

The PSI status register provides the information regarding

the current status of the PSI pin though the I

2

C interface as

shown in Table 18.

Table 18. PSI STATUS REGISTER SETTINGS

Bits Description

7:2 Reserved

1:0 00 = PSI MID

01 = PSI LOW
10 = PSI HIGH

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21

NCV81277A

Table 19. SWITCHING FREQUENCY STATUS AND CONFIGURATION REGISTER SETTINGS

FSW Pin
Resistor

Value (kW)

10

14.7

20

26.1

33.2

41.2

49.9

60.4 0111 01110 518 688 526 518

71.5 1000 10000 581 789 583 578

84.5 1001 10010 708 930 698 698

100 1010 10100 799 1095 807 818

118.3 1011 10110 919 1233 899 938

136.6 1100 11000 993 1341 1003 1014

157.7 1101 11010 1098 1450 1096 1106

182.1 111 0 11100 1200 1619 1205 1201

249 1111 11110 1291 1674 1274 1280

NOTE: 1% tolerance.

Bits

7:5 Reserved Reserved N/A N/A N/A N/A

4:0

Status

Register

Value Switching Frequency (kHz)

Configuration

Register

0000 00000 221 293 223 232

− 00001 244 329 243 252

0001 00010 266 358 264 272

− 00011 293 381 294 297

0010 00100 307 407 317 322

− 00101 333 450 335 340

0011 00110 351 480 352 361

− 00111 373 510 380 385

0100 01000 394 530 399 413

− 01001 421 562 420 435

0101 01010 449 600 436 456

− 01011 469 614 454 478

0110 01100 479 631 483 500

− 01101 509 663 508 509

− 01111 543 722 543 540

− 10001 649 859 656 638

− 10011 751 1010 771 758

− 10101 866 1147 860 878

− 10111 964 1260 950 972

− 11001 1059 1372 1052 1067

− 11011 1141 1539 1154 1155

− 11101 1236 1618 1227 1245

− 11111 1312 1724 1316 1330

4

Phase

3

Phase

2

Phase

1

Phase

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22

NCV81277A

Phase Status Register (0x33)

The Phase Status register provides the information about
the status of each of the four available phases as shown in
Table 20.

Table 20. PHASE STATUS REGISTER SETTINGS

Bits Name Description

7:4 Reserved N/A

3 Phase 4 0 = Disabled

2 Phase 3 0 = Disabled

1 Phase 2 0 = Disabled

0 Phase 1 0 = Disabled

1 = Enabled

1 = Enabled

1 = Enabled

1 = Enabled

LPC_Zone_enable Register (0x34)

The LPC_Zone_enable register allows the user to enable
or disable power zones while the controller has the PSI set
low using the I

Table 21. LPC_ZONE_ENABLE REGISTER SETTINGS

Bits Name Description

7:4 Reserved N/A

4 Zone 4 0 = Disabled

3 Zone 3 0 = Disabled

2 Zone 2 0 = Disabled

1 Reserved N/A

0 Zone 0 0 = Disabled

2

C interface as shown in Table 21.

1 = Enabled

1 = Enabled

1 = Enabled

1 = Enabled

Table 22. CONFIGURATION REGISTER SETTINGS

Bits Name Value Level

7:6 Reserved N/A N/A

5:3 LPC2

Configuration

2:0 LPC1

Configuration

000 (default) 0

001 N/A

010 2

011 3

100 4

101 = Reserved N/A

110 = Reserved N/A

111 = Reserved N/A

000 (default) 0

001 N/A

010 2

011 3

100 4

101 = Reserved N/A

110 = Reserved N/A

111 = Reserved N/A

LL Status and Configuration Registers (0x38, 0x39)

These registers contain the values that set the fraction of
the externally configured load line (see Total Current Sense
Amplifier section) to be used during the normal operation of
the device. When EN is set high, the controller reads the
value of the resistor connected to the LL/I2C_ADD pin and
sets the load line according to Table 5. The codes
corresponding to each setting are shown in Table 23. The
load line resistor setting is updated on every rising edge of
the EN signal.

The LL configuration register allows the user to
dynamically change the load line settings through the I

2

interface provided that the LL bits from the second function
configuration registers A and B (0x46, 0x47) are set. The
achievable load line settings are listed in Table 23.

C

LPC Status and Configuration Registers (0x35, 0x36)

These registers contain the values that set the operating
power zone when the PSI pin is set low. When EN is set high,
the controller reads the value of the resistor connected to the
LPC1 and LPC2 pins and sets the power zone according to
Table 7. The LPC

resistor settings are updated on every

X

rising edge of the EN signal. LPC status register 0x35
records the status of LPC2(Bit[2:0]) and LPC1(Bit[5:3])
resistor setting during startup. The status register value
won’t change afterwards.

The LPC configuration register (0x36) allows the user to
dynamically change the power zone (PSI = Low) through

2

the I

C interface provided that the LPC bits from the second
function configuration registers A and B (0x46, 0x47) are
set. The achievable power zone settings are listed in
Table 22.

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Table 23. LL STATUS AND CONFIGURATION
REGISTER SETTINGS

Bits Description

7:2 Reserved

1:0 00 = 100% of externally set load line (default)

01 = 50% of externally set load line
10 = 25 of externally set load line
11 = 0% of externally set load line

PHTH1 to PHTH4 Configuration Registers (0x3A, 0x3C,
0x3E, 0x40)

These registers contain the values that control the phase
shedding thresholds and are active when the PHTH
from the second function configuration registers A and B
(0x46 and 0x47) are set be set. These thresholds allow the
user to dynamically change the thresholds through the I
interface. The values written to these registers should match
the value of the READ_IOUT register (0x26) at the desired
load current. If 0xFF is written to a register, the phase
shedding threshold corresponding to that register is
disabled.

23

X

bits

2

C

NCV81277A

PHTH1 to PHTH4 Status Registers
(0x3B, 0x3D, 0x3F 0x41)

These registers contain the phase shedding threshold

values set by the resistors connected to the PHTH

pins. The

X

values of the thresholds are updated on every rising edge of
the EN signal. The resistor values should be chosen to ensure
that the voltage drop across them developed by the 10 mA
current sourced by the NCV81277A during power-up (EN
set high) matches the value of the READ_IOUT register
(0x26) at the desired load current. Setting the resistors to
generate a voltage above 2 V will disable the PHTH
threshold for that pin.

Phase Shedding Hysteresis Register (0x44)

This register sets the hysteresis during a transition from
a high count phase to a low count phase configuration. The
hysteresis is expressed in codes (LSBs) of the PHTH
threshold values, by default its value is 08H. .

Phase Shedding Delay Register (0x45)

This register sets the delay during a transition from a high
count phase to a low count phase configuration. The
power-up default value is 200 ms (14H) and it can be
dynamically changed in steps of 10 ms (1 LSB) through the

2

C interface.

I

Second Function Configuration Register
Latch A and B Registers (0x46, 0x47)

These registers allow the user to select whether the second
functions settings (LL, Soft Start, OCP, LPC and PHTH

X

are controlled by the external resistors or the configuration
registers (see Table 24). When/EN is toggled the default
control mode for the second functions is the external resistor.
Switching between the two modes can be done by simply
writing the appropriate byte (the same byte) to both registers
(the order doesn’t matter).

Table 24. SECOND CONFIGURATION LATCH

REGISTER A AND B

Second Function

Configuration

Bits

7:6 Reserved N/A

5 FSW 0 = set by external resistor

X

X

4 LL 0 = set by external resistor

3 Reserved N/A

2 OCP 0 = set by external resistor

1 LPC1, LPC2 0 (default) = low power zone set

0 PHTH

Register

Description

(see Table 19)
1 = set by register 0x30

(see Table 19)

(see Table 5)
1 = set by register 0x39

(see Table 9)
1= set by register 0x2E

by external resistor
1 = low power zone set by regis­ter 0x36

X

0 = set by external resistors con­nected between PHTH
GND

1 = set by registers 0x3A, 0x3C,
0x3E and 0x40

pins and

X

)

NVIDIA is a registered trademark of of NVIDIA Corporation in the U.S. and/or other countries. All other brand names and product names appearing in this
document are registered trademarks or trademarks of their respective holders.

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24

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

QFNW40 5x5, 0.4P

CASE 484AK

ISSUE B

EXPOSED
COPPER

DATE 19 FEB 2020

GENERIC

MARKING DIAGRAM*

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