Semiconductor NCP1271 User Manual

NCP1271

PW

M Controller, Soft-Skip &
trade; Standby, with
Adjustable Skip Level and

External Latch

The NCP1271 represents a new, pin to pin compatible, generation
of the successful 7−pin current mode NCP12XX product series. The
controller allows for excellent stand by power consumption by use of
its adjustable Soft−Skip mode and integrated high voltage startup
FET. This proprietary Soft−Skip also dramatically reduces the risk of
acoustic noise. This allows the use of inexpensive transformers and
capacitors in the clamping network. Internal frequency jittering, ramp
compensation, timer−based fault detection and a latch input make
this controller an excellent candidate for converters where
ruggedness and component cost are the key constraints.

Features

• Fixed−Frequency Current−Mode Operation with Ramp

Compensation and Skip Cycle in Standby Condition

• Timer−Based Fault Protection for Improved Overload Detection

• “Soft−Skip Mode” Technique for Optimal Noise Control in Standby

• Internal High−Voltage Startup Current Source for Lossless Startup

• "5% Current Limit Accuracy over the Full Temperature Range

• Adjustable Skip Level

• Internal Latch for Easy Implementation of Overvoltage and

Overtemperature Protection

• Frequency Jittering for Softened EMI Signature

• +500 mA/−800 mA Peak Current Drive Capability

• Sub−100 mW Standby Power can be Achieved

• Pin−to−Pin Compatible with the Existing NCP120X Series

• This is a Pb−Free Device

Typical Applications

• AC−DC Adapters for Notebooks, LCD Monitors

• Offline Battery Chargers

• Consumer Electronic Appliances STB, DVD, DVDR

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SOIC−7

D SUFFIX

CASE 751U

PDIP−7 VHVIC

P SUFFIX

CASE 626B

8

1

x = A or B

A= 65 kHz

B= 100 kHz
xxx = Device Code: 65, 100
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package

(Note: Microdot may be in either location)

PIN CONNECTIONS

FB

CS

GND

1

2

3

4

(Top View)

Skip/latch

1

8

6

5

MARKING

DIAGRAMS

8

1271x

ALYWG

G

1

1271Pxxx

AWL

YYWWG

HV

V

CC

Drv

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2009

September, 2009 − Rev. 6

1 Publication Order Number:

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.

NCP1271/D

NCP1271

+

AC

Input

*Optional

EMI

Filter

R

skip

latch input*

skip/latch
FB
CS
Gnd

HV

Vcc

Drv

NCP1271

Figure 1. Typical Application Circuit

R

*

ramp

Output

Voltage

−

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2

NCP1271

MAXIMUM RATINGS (Notes 1 and 2)

Rating Symbol Value Unit

VCC Pin (Pin 6)

Maximum Voltage Range
Maximum Current

Skip/Latch, FB, CS Pin (Pins 1−3)

Maximum Voltage Range
Maximum Current

Drv Pin (Pin 5)

Maximum Voltage Range
Maximum Current

HV Pin (Pin 8)

Maximum Voltage Range
Maximum Current

Power Dissipation and Thermal Characteristics

Thermal Resistance, Junction−to−Air, PDIP−7, Low Conductivity PCB (Note 3)
Thermal Resistance, Junction−to−Lead, PDIP−7, Low Conductivity PCB
Thermal Resistance, Junction−to−Air, PDIP−7, High Conductivity PCB (Note 4)
Thermal Resistance, Junction−to−Lead, PDIP−7, High Conductivity PCB
Thermal Resistance, Junction−to−Air, SO−7, Low Conductivity PCB (Note 3)
Thermal Resistance, Junction−to−Lead, SO−7, Low Conductivity PCB
Thermal Resistance, Junction−to−Air, SO−7, High Conductivity PCB (Note 4)
Thermal Resistance, Junction−to−Lead, SO−7, High Conductivity PCB

Operating Junction Temperature Range T

Maximum Storage Temperature Range T

ESD Protection

Human Body Model ESD Pins 1−6
Human Body Model ESD Pin 8
Machine Model ESD Pins 1−4, 8
Machine Model ESD Pins 5, 6
Charged Device Model ESD

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

1. ESD protection per JEDEC JESD22−A114−F for HBM, per JEDEC JESD22−A115−A for MM, and per JEDEC JESD22−C101D for CDM.
This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.

2. Guaranteed by design, not tested.

3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm2 of 2 oz copper traces and heat spreading area. As specified for
a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.

4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.

V

max

I

max

V

max

I

max

V

max

I

max

V

max

I

max

R

q

JA

R

q

JL

R

q

JA

R

q

JL

R

q

JA

R

q

JL

R

q

JA

R

q

JL

J

stg

HBM
HBM

MM
MM

CDM

−0.3 to +20
100

−0.3 to +10
100

−0.3 to +20

−800 to +500

−0.3 to +500

100

142

57

120

56

177

75

136

69

°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W

−40 to +150 °C

−60 to +150 °C

2000

700
200
150

1000

V

mA

V

mA

V

mA

V

mA

V
V
V
V
V

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3

NCP1271

R

skip

Skip/ latch

R

ramp

R

CS

FB

CS

Gnd

I

skip

1

−

+

13 us filter

S

R

10V

V

= R

* I

skip

skip

or

skip

= 1.2 V when pin 1 is opened

V

skip

4.8 V

2.85 V

FB

16.7k

V

2

75.3k

1 / 3

10V

V

3

CS

V / 3

FB

0

180 ns

LEB

10V

TLD

−

+

V

ss

(1V max)

−

+

1

V

PWM

100uA

Soft start/ soft−skip

management
4 ms/ 300 us

130ms

delay

PWM

−

+

disable
soft
skip

V

V

skip

FB

&

skip
+

−

soft−skip

soft
start

short
circuit
fault

0

jittered ramp
current source

latch−off, reset
when Vcc < 4V

Q

4.1 mA when Vcc > 0.6 V

0.2 mA when Vcc < 0.6 V

S

Q

R

double
hiccup

B2

Counter

&

turn on internal bias

OR

turn off

V

−

+

UVLO

−

+

CC

12.6/

5.8 V

9.1 V

20V

8

HV

V

CC

6

Drv

8 V

4

1 0

7.5% Jittering
65, 100 kHz
Oscillator

R

S

Max duty

= 80%

Q

driver:
+500 mA
/ −800 mA

5

Figure 2. Functional Block Diagram

PIN FUNCTION DESCRIPTION

Pin No. Symbol Function Description

1 Skip/latch Skip Adjust or

Latchoff

A resistor to ground provides the adjustable standby skip level. Additionally, if this pin is
pulled higher than 8.0 V (typical), the controller latches off the drive.

2 FB Feedback An optocoupler collector pulls this pin low during regulation. If this voltage is less than

the Skip pin voltage, then the driver is pulled low and Soft−Skip mode is activated. If this
pin is open (>3 V) for more than 130 ms, then the controller is placed in a fault mode.

3 CS Current Sense This pin senses the primary current for PWM regulation. The maximum primary current

is limited to 1.0 V / RCS where RCS is the current sense resistor. Additionally, a ramp
resistor R

between the current sense node and this pin sets the compensation ramp

ramp

for improved stability.

4 Gnd IC Ground −

5 Drv Driver Output The NCP1271’s powerful output is capable of driving the gates of large Qg MOSFETs.

6 V

CC

Supply Voltage This is the positive supply of the device. The operating range is between 10 V (min) and

20 V (max) with a UVLO start threshold 12.6 V (typ).

8 HV High Voltage This pin provides (1) Lossless startup sequence (2) Double hiccup fault mode (3)

Memory for latch−off shutdown and (4) Device protection if VCC is shorted to GND.

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NCP1271

ELECTRICAL CHARACTERISTICS (For typical values T

= 25°C, for min/max values, TJ = −40°C to +125°C, VCC = 14 V,

J

HV = open, skip = open, FB = 2 V, CS = Ground, DRV = 1 nF, unless otherwise noted.)

Characteristic Pin Symbol Min Typ Max Unit

OSCILLATOR

Oscillation Frequency (65 kHz Version, T

= 25_C)

J

Oscillation Frequency (65 kHz Version, TJ = −40 to + 85_C)
Oscillation Frequency (65 kHz Version, T
Oscillation Frequency (100 kHz Version, T

= −40 to + 125_C)

J

= 25_C)

J

Oscillation Frequency (100 kHz Version, TJ = −40 to +85_C)
Oscillation Frequency (100 kHz Version, TJ = −40 to +125_C)

Oscillator Modulation Swing, in Percentage of f

osc

5 f

osc

61.75
58
55
95
89
85

65
65

65
100
100
100

68.25
69
69

105
107
107

5 − − "7.5 − %

Oscillator Modulation Swing Period 5 − − 6.0 − ms

Maximum Duty Cycle (VCS = 0 V, VFB = 2.0 V) 5 D

max

75 80 85 %

GATE DRIVE

Gate Drive Resistance

Output High (V

= 14 V, Drv = 300 W to Gnd)

CC

Output Low (VCC = 14 V, Drv = 1.0 V)

Rise Time from 10% to 90% (Drv = 1.0 nF to Gnd) 5 t

Fall Time from 90% to 10% (Drv = 1.0 nF to Gnd) 5 t

5

R

OH

R

OL

r

f

6.0

2.0

11

6.0

20
12

− 30 − ns

− 20 − ns

CURRENT SENSE

Maximum Current Threshold 3 I

Soft−Start Duration − t

Soft−Skip Duration − t

Leading Edge Blanking Duration 3 t

Limit

SS

SK

LEB

0.95 1.0 1.05 V

− 4.0 − ms

− 300 − ms

100 180 330 ns

Propagation Delay (Drv =1.0 nF to Gnd) − − − 50 150 ns

Ramp Current Source Peak 3 I

Ramp Current Source Valley 3 I

ramp(H)

ramp(L)

− 100 − mA

− 0 − mA

SKIP

Default Standby Skip Threshold (Pin 1 = Open) 2 V

Skip Current (Pin 1 = 0 V, TJ = 25_C) 1 I

Skip Level Reset (Note 5) 1 V

skip−reset

Transient Load Detection Level to Disable Soft−Skip Mode 2 V

skip

skip

TLD

− 1.2 − V

26 43 56 mA

5.0 5.7 6.5 V

2.6 2.85 3.15 V

EXTERNAL LATCH

Latch Protection Threshold 1 V

Latch Threshold Margin (V

latch−m

= V

CC(off)

− V

) 1 V

latch

latch

latch−m

7.1 8.0 8.7 V

0.6 1.2 − V

Noise Filtering Duration 1 − − 13 − ms

Propagation Delay (Drv = 1.0 nF to Gnd) 1 T

latch

− 100 − ns

SHORT−CIRCUIT FAULT PROTECTION

Time for Validating Short−Circuit Fault Condition 2 t

protect

− 130 − ms

5. Please refer to Figure 39 for detailed description.

6. Guaranteed by design.

kHz

W

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5

NCP1271

ELECTRICAL CHARACTERISTICS (continued) (For typical values T

= 25°C, for min/max values, TJ = −40°C to +125°C,

J

VCC = 14 V, HV = open, skip = open, FB = 2 V, CS = Ground, DRV = 1 nF, unless otherwise noted.)

Characteristic Pin Symbol Min Typ Max Unit

STARTUP CURRENT SOURCE

High−Voltage Current Source

Inhibit Voltage (I
Inhibit Current (V
Startup (V

= 200 mA, HV = 50 V)

CC

= 0 V, HV = 50 V)

CC

= V

CC

CC(on)

− 0.2 V, HV = 50 V)

Leakage (VCC = 14 V, HV = 500 V)

Minimum Startup Voltage (VCC = V

– 0.2 V, ICC = 0.5 mA) 8 V

CC(on)

6
6
6
8

V

inhibit

I

inhibit

I

HV

I

HV−leak

HV(min)

SUPPLY SECTION

VCC Regulation

Startup Threshold, VCC Increasing
Minimum Operating Voltage After Turn−On
V

Operating Hysteresis

CC

Undervoltage Lockout Threshold Voltage, V
Logic Reset Level (V

CC(latc h)

–V

CC(reset)

Decreasing

CC

> 1.0 V) (Note 7)

VCC Supply Current

Operating (VCC = 14 V, 1.0 nF Load, VFB = 2.0 V, 65 kHz Version)
Operating (VCC = 14 V, 1.0 nF Load, VFB = 2.0 V, 100 kHz Version)
Output Stays Low (VCC = 14 V, VFB = 0 V)
Latchoff Phase (VCC = 7.0 V, VFB = 2.0 V)

6

V

CC(on)

V

CC(off)

V

− V

CC(on)

V

CC(latc h)

V

CC(reset)

6

I

CC1

I

CC1

I

CC2

I

CC3

7. Guaranteed by design.

CC(off)

190

80

3.0
10

600
200

4.1
25

800
350

6.0
50

− 20 28 V

11.2

8.2

3.0

5.0

12.6

9.1

3.6

5.8

−

−

−

−

−

4.0

2.3

3.1

1.3
500

13.8
10

4.2

6.5

−

3.0

3.5

2.0

720

mV

mA

mA

mA

V
V
V
V
V

mA
mA
mA

mA

110

100

90

80

70

60

OSCILLATION FREQUENCY (kHz)

50

−25 −25

Figure 3. Oscillation Frequency vs.

TYPICAL CHARACTERISTICS

85

84

100 kHz

65 kHz

1251007550250−50

TEMPERATURE (°C) TEMPERATURE (°C)

Temperature

83

82

81

80

79

78

77

MAXIMUM DUTY CYCLE (%)

76

75

Figure 4. Maximum Duty Cycle vs.

Temperature

1251007550250−50

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6

NCP1271

5

5

TYPICAL CHARACTERISTICS

16

14

12

10

8

6

4

2

0

OUTPUT GATE DRIVE RESISTANCE (W)

8

7

6

5

4

3

2

1

SOFT−START DURATION (ms)

0

1.04

R

OH

R

OL

−25 −25

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−50

1.02

1.0

0.98

CURRENT LIMIT (V)

0.96

0.94

Figure 5. Output Gate Drive Resistance vs.

Temperature

350

300

250

200

150

100

50

LEADING EDGE BLANKING TIME (ns)

−25

1251007550250−50

TEMPERATURE (°C)

0

Figure 6. Current Limit vs. Temperature

−25

TEMPERATURE (°C)

1007550250−50

1251007550250−50

12

Figure 7. Soft−Start Duration vs. Temperature Figure 8. Leading Edge Blanking Time vs.

1.40

1.30

1.20

1.10

DEFAULT SKIP LEVEL (V)

1.00

−25

Figure 9. Default Skip Level vs. Temperature Figure 10. Skip Pin Current vs. Temperature

TEMPERATURE (°C)

45

44

43

42

41

40

39

38

37

SKIP PIN CURRENT (mA)

36

1251007550250−50

35

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7

−25

Temperature

TEMPERATURE (°C)

12

1007550250−50