SEC Mobile R & D Bremen-L3, NP-E352, NP-R528, NP-R530, NP-R728 Schematic

- - - This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic

4

3

SAMSUNG PROPRIETARY

THIS DOCUMENT CONTAINS CONFIDENTIAL

PROPRIETARY INFORMATION THAT IS

SAMSUNG ELECTRONICS CO’S PROPERTY.

DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS

EXCEPT AS AUTHORIZED BY SAMSUNG.

D
			Bremen-L3
		CPU		:Intel Penryn
		Chip Set :Intel Cantiga & ICH9M
C		Remarks		:Montevina Platform
		Model Name : Bremen-L3
		PBA Name		: MAIN
		PCB Code		: GCE : BA41-01226A
				NY : BA41-01227A
				HST : BA41-01228A
B		Dev. Step		: PV
		Revision		: 1.0
		T.R. Date		: 2009.10.27
			Design	CHECK APPROVAL

A

			Owner : SEC Mobile R & D		Signature :	X
4					3

2

1

D

C

B

A

	DRAW	DATE		TITLE			SAMSUNG
	Jun PARK	10/10/2008		Bremen-L3
	CHECK	DEV. STEP						ELECTRONICS
	YM.AHN		PV	MAIN
	APPROVAL	REV		COVER		PART NO.
	HJ.KIM	1.0						BA41-xxxxxA
	MODULE CODE	LAST EDIT					1		59
				October 27, 2009 14:27:43 PM	PAGE			OF
2				1

D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN

8-1

R530/R730

- - - This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic

4

SAMSUNG PROPRIETARY

THIS DOCUMENT CONTAINS CONFIDENTIAL

PROPRIETARY INFORMATION THAT IS

SAMSUNG ELECTRONICS CO’S PROPERTY.

DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.

D

LED LCD

17.3" HD+ / 15.6"

Page 36

CRT

Page 37

C

B

A

4

		3
		FAN
	CLOCK	Page 8			Intel Pentium
	CK-505M
					Intel Core2Duo
	Page 12	CPU
		Thermistor
		EMC2112
		Page 8		Page 9~11
					FSB ~1067MHz
	LVDS(15" Single, 17" Dual)				External -
					Cantiga-PM45
					Cantiga-GM45
					Internal -
					Cantiga-GL40
					BREMEN-UL
		P 2		Page 13~17
	Single USB Port
		P 4, 6	USB 2.0
	Dual USB Port
	ANT	P 5
	Bluetooth				ICH9-M
TBD
	0.3M
		P 8(17")
		P 9(15")
	CARDREADER				RTC
3-in-1	ALCOR AU6336 P 4
	Page 42
				Page 30~34
	SPI ROM
	Page 35			Definition	MICOM
	16Mbit
				High	MEC1308
					Page 45
	ALC269
	Page 39~40
					Space bar
	L	R			KEYBOARD
					Page 46

3

2 1

BREMEN-L

BLOCK DIAGRAM

D

Channel A (Reverse)

Dual channel DDR II 800

Channel B (Reverse)

DDR2-SODIMM x 2

Page 18~19

nVidia

C

gDDR3

N11M-GE

Page 25~28

Page 20~24

SATA

SATA0

2.5" HDD

Page 44

SATA1

12.7mm ODD

FFC

Page 44

PCIe

PEX1

WLAN

PEX4

( Half Type)

Page 43

B

10/100 LAN

RJ45

Controller

RTL8040

Page 41

Transformer

SENTELIC

TOUCHPAD

For 17"

For 15"

A

DRAW

DATE

TITLE

SAMSUNG

Jun PARK

9/23/2008

Bremen-L3

CHECK

DEV. STEP

ELECTRONICS

YM.AHN

PV

MAIN

APPROVAL

REV

BLOCK DIAGRAM

PART NO.

HJ.KIM

1.0

BA41-xxxxxA

MODULE CODE

LAST EDIT

PAGE 2 OF 59

undefined

October 27, 2009 14:27:43 PM

2

1

D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN

R530/R730

8-2

- - - This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic

4

3

2

1

SAMSUNG PROPRIETARY

THIS DOCUMENT CONTAINS CONFIDENTIAL

PROPRIETARY INFORMATION THAT IS

SAMSUNG ELECTRONICS CO’S PROPERTY.

DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS

BOARD INFORMATION

EXCEPT AS AUTHORIZED BY SAMSUNG.

D

SCHEMATIC ANNOTATIONS AND BOARD INFORMATION

D

I2 C / SMB Address

Voltage Rails

Devices

Address

Hex

Bus

Power Rail

Descriptions

Power Rail

Descriptions

ICH9M

Master

SMBUS Master

VDC_ADPT

Primary DC system power supply (9 to 19V)

P1.05V_PEG

P1.05V (Direct Media Interface Compensation)

CK-505M (Clock Generator)

1101 001X

D2h

Clock, Unused Clock Output Disable

VDC

P5.0V

5.0V Power Rail (off in S3-S5)

SODIMM0

1010 000X

A0h

-

VDC_CHG

Charger Reference Voltage Source

P3.3V

3.3V Power Rail (off in S3-S5)

SODIMM1

1010 001X

A4h

PRTC_BAT

3.3V supply for the RTC well.

P1.05

1.05V Power Rail (off in S3-S5)

P5.0V_ALW

5.0V always power well

P0.9V

DDR2 Termination

MICOM

Master

P5.0V_AUX

5.0V Power Rail (off in S4-S5)

P12.0V_ALW

12.0V always power well

P3.3V_AUX

3.3V Power Rail (off in S4-S5)

BATTERY

0001 011X

16h

P1.7V_VREF

Power Chip Reference

P1.8_AUX

1.8V Power Rail (off in S4-S5)

P2.0V_VREF

Power Chip Reference

CPU_CORE

Core Voltage for CPU

EMC2102

0111 101X

7Ah

P5.0V_VREF_FILT

Power Chip Reference

P3.3V_MICOM

Output voltage of RT8205AGQW

USB PORT Assignation

(if VDC is removed, it will be off)

AUD_P5V

5.0V supply for Audio

C

LCD_VDD3V

3.3V (LED LCD)

P4.75V_AUD

Auido Analog Voltage

C

Port Number

ASSIGNED TO

Port Number

ASSIGNED TO

KBC3_CHG4.2V

To charge battery

P5.0V_STB

To charge USB device at sleep status

UHCI_0

0

USB PORT (RIGHT, SUB)

UHCI_3

6

USB PORT (RIGHT, SUB)

P5.0V_ODD

5.0V supply at SUB_ODD Board

1

7

EGFX_CORE

nVidia Graphic Chip power

UHCI_1

2

USB PORT (LEFT)

UHCI_4

8

CAMERA(17")

P1.2V_LAN

3

9

CAMERA(15")

P2.5V_LAN

Internal Regulator’s Power of LAN Controller

P1.5V

1.5V Power Rail (off in S3-S5)

Power source of External

UHCI_2

4

CARD READER(AU6336)

UHCI_5

10

P1.5_AUX

1.5V Power Rail (off in S4-S5)

5

BLUETOOTH(TBD)

11

P3.3V_MCD

3.3V (3-in-1 Socket)

P1.8V

1.8V Power Rail (off in S3-S5)

SATA Assignation

Port Number

ASSIGNED TO

Port Number

ASSIGNED TO

SATA0

HDD

SATA1

ODD

SATA2

-

SATA3

-

B

B

PCI EXPRESS Assignation

Port Number

ASSIGNED TO

Port Number

ASSIGNED TO

PCIe1

WLAN

PCIe2

Wired LAN

PCIe3

-

PCIe4

-

REVISION HISTORY

Crystal / Oscillator

ICH9-M

USAGE

See rev notes for more information.

Crystal

32.768KHz

TYPE

PREQUENCY

DEVICE

Crystal

10MHz

MICOM

A

Crystal

14.318MHz

CLOCK-Generator

A

Crystal

25MHz

LAN

DRAW

DATE

TITLE

SAMSUNG

Jun PARK

9/23/2008

Bremen-L3

CHECK

DEV. STEP

ELECTRONICS

YM.AHN

PV

MAIN

APPROVAL

REV

BOARD INFO

PART NO.

HJ.KIM

1.0

BA41-xxxxxA

MODULE CODE

LAST EDIT

3

59

undefined

October 27, 2009 14:27:43 PM

PAGE

OF

4

3

2

1

D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN

8-3

R530/R730

- - - This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic

4			3	2			1
	SAMSUNG PROPRIETARY
	THIS DOCUMENT CONTAINS CONFIDENTIAL
	EXCEPT AS AUTHORIZED BY SAMSUNG.				POWER DIAGRAM
	PROPRIETARY INFORMATION THAT IS
	SAMSUNG ELECTRONICS CO’S PROPERTY.
	DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS

D		KBC3_SUSPWR		KBC3_PWRON				D
		(CHP3_S4_STATE*)
				(CHP3_SLPS3*)			KBC3_VRON
AC ADAPTER
	RT8205	P5.0V_ALW	P5.0V_AUX	P5.0V	EMC2112	ODD
					GL40	TOUTCHPAD
					CRT	CAMERA
	VDC	USB, Swithched Power		GL40	HDD	FAN
DC BATTERY				P5.0V_AUD ALC269Q
	P3.3V_MICOM	P3.3V_AUX
	SPI ROM, MICOM, LEDs	ICH9M, LED, Wire LAN, LED LCD		P3.3V	CK505M	80 PORT	WLAN	LEDs
		RTL8103EL, EMC2112			GL40	LED LCD	HDD
	P5.0V_STB				DDR2	ALC269Q	MICOM
					ICH9M	AU6336	LID SW
				P3.3V_MCD 3-in-1 Socket
C								C
	P12.0V_ALW	P1.8V_AUX		P1.8V	N11M-GE
	APW7141
		GL40, DDR II
				P0.9V	DDR II Termination
				P1.5V	PENTIUM CPU gDDR3
					CK505M	ICH9M
	APW7141				GL40
					ALC269Q
				P1.05V	PENTIUM CPU
					GL40
					ICH9M
	TPS51620			CPU_CORE PENTIUM CPU
B				P1.2V_LAN 88E8040				B
				P2.5V_LAN
	SC471			EGFX_CORE N11M-GE
	S5-S4	S3				S0

A								A
		DRAW	DATE	TITLE		SAMSUNG
		Jun PARK	9/23/2008	Bremen-L3
		CHECK	DEV. STEP				ELECTRONICS
		YM.AHN	PV	MAIN
		APPROVAL	REV	POWER DIAGRAM	PART NO.
		HJ.KIM	1.0				BA41-xxxxxA
		MODULE CODE	LAST EDIT			4		59
		undefined		October 27, 2009 14:27:43 PM	PAGE		OF
4	3	2		1
				D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN

R530/R730

8-4

- - - This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic

4

3

2

1

SAMSUNG PROPRIETARY

RTC

PRTC_BAT

1

POWER SEQUENCE

SAMSUNG ELECTRONICS CO’S PROPERTY.

THIS DOCUMENT CONTAINS CONFIDENTIAL

PROPRIETARY INFORMATION THAT IS

Battery CHP3_RTCRST#

EXCEPT AS AUTHORIZED BY SAMSUNG.

DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS

22) KBC3_CPURST# 22

PRTC_BAT

25) PLT3_RST#

21

16) P1.5V

9) P3.3V_AUX

D

12

17) P3.3V

EMC21112

D

ICH9-M

CK-505M

15) P5.0V

4) P3.3V_MICOM

11) CHP3_SLPS5#/4#/3#

POWER

21) CLK3_PWRGD

Sheet 8

16) P3.3V

11

Sheet 12

4) P3.3V_MICOM

S/W

12) KBC3_RSMRST#

MX25L

9) P3.3V_AUX

9) P3.3V_AUX LCD_VDD3V

Sheet 35

13

16) P3.3V

KBC

14) KBC3_PWRBTN#

17) P1.5V

2) VDC

VDD_LED

LED LCD

6

PWRSW#

18) P1.05V

15) P5.0V

CRT

23) KBC3_PWRGD 23

16) P3.3V

Sheet 36

VRMPWRGD

KBC3

20) VRM3_CPU_PWRGD

25) CHP3_SUSSTAT#

24

P5.0V_AUD

25

PWROK

24) CPU1_PWRGDCPU

15) P5.0V

Sheet 37

6)

7

P5.0V_AUD

P4.75V_AUD

7) KBC3_SUSPWR

26) PLT3_RST#

26

14

17) P1.5V

ALC 269

14) KBC3_PWRON

16) P3.3V

Sheet 39

20) VRM3_CPU_PWRGD

C

(KBC3_VRON)

Sheet 30~34

C

Sheet 45

2) VDC

9) P3.3V_AUX

88E8040

SUSPWRKBC37)

P1.8V_AUX

10) P1.8V_AUX

10

Sheet 41

BATTERYADAPTER

2

VDC

**USBCHGKBC3**

Sheet 9~11

27

4) P3.3V_MICOM

7) KBC3_SUSPWR

APW7141

19) CPU_CORE

VDC_ADPT /

Sheet 52

16) P3.3V

P3.3V_MCD

10) P1.8V_AUX

AU6336

VDC_CHG

BQ24751

2) VDC

P1.5V

17) P1.5V

CPU

Sheet 42

10 KOHM

10 KOHM

MEM1_VREF

14) KBC3_PWRON

APW7141 17) P1.5V

17

18) P1.05V

16) P3.3V

WLAN

Sheet 53

Sheet 43

2)

2-1) P12.0V_ALW

2) VDC

P1.5V

23) KBC3_PWRGD

27) CPU1_CPURST#

15) P5.0V

18) P1.05V

18

ODD

14) KBC3_PWRON

APW7141

CL_PWROK

Sheet 44

PWROK

3

9) P3.3V_AUX

9

Sheet 53

26) PLT3_RST#

16) P3.3V

B

P3.3V_AUX & P5V_ALW

B

RT8205

8) P5.0V_AUX

18) P1.05V

PM45

15) P5.0V

2.5" HDD

8) P5.0V_AUX

8

P0.9V

3) P5.0V_ALW

P0.9V

Sheet 44

0 OHM

14) KBC3_PWRON

APL5336

10) P1.8V_AUX

5

4) P3.3V_MICOM 4

Sheet 52

17) P1.5V

15) P5.0V

TOUCHPAD

5) P5.0V_STB

16) P3.3V

Sheet 13~17

Sheet 46

CHP3_DPRSLPVR

4) P3.3V_MICOM

CPU1_DPRSTP#

16) P3.3V

LED

10) P1.8V_AUX

9) P3.3V_AUX

Sheet 47

9) P3.3V_AUX

16

2) VDC

CPU_CORE

19) CPU_CORE

19

MEM1_VREF

DDR2

TPS51620

14) KBC3_PWRON

AO6409L

16) P3.3V

16) P3.3V

Sheet 56

19) VCCP3_PWRGD

Sheet 18~19

GCORE3_PWRGD

20) VRM3_CPU_PWRGD

15

Sheet 43

8) P5.0V_AUX

20

15) P5.0V

A

14) KBC3_PWRON

AP4435GM

A

Sheet 56

14-1

14-1) KBC3_PWRON_INV#

2) VDC

EGFX_CORE

DRAW

DATE

TITLE

SAMSUNG

Bremen-L3

SC471

Jun PARK

9/23/2008

10) P1.8V_AUX

MAIN

EGFX_CORE (Between P3.3V & P1.5V)

CHECK

YM.AHN

PV

ELECTRONICS

DEV. STEP

AO6409L

P1.8V (After P1.05V)

14) KBC3_PWRON

APPROVAL

REV

POWER SEQUENCE

PART NO.

14) KBC3_PWRON

BA41-xxxxxA

HJ.KIM

1.0

Sheet 56

MODULE CODE

LAST EDIT

5

OF 59

undefined

October 27, 2009 14:27:43 PM PAGE

4

3

2

1

D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN

8-5

R530/R730

- - - This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic

	4
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
P3.3V	FS(2:0)
D	1		266 MHz
CLK3_PWRGD*		MUX
ITP_EN
CPU_STP*	Main PLL		266 MHz
	SSC
			100 MHz (SRC0)
			CLK1_DREFSSCLK/DREFSSCLK#
		MUX	100 MHz (SRC4)
			96 MHz

C

B

SS(96/100) SEL

505M(w/ CLKREQ* & SSDC)	xSLG8SP513r05)
CK-

PLL3

SSC

48MHz PLL

MUX

100 MHz

100 MHz (SRC 6,9)

100 MHz (SRC 3)

48 MHz

100 MHz (SRC 2)

14.318 MHz

33 MHz

	3		2			1
			CLOCK DISTRIBUTION
	CLK0_HCLK/CLK#	CPU	BSEL				D
		FSB			667/800 MHz
	CLK0_HCLK1/HCLK1#	HPLL	333/400 MHz	CLK1_MCLK0/0#
					SODIMM #0
	PCI Express Gfx	MPLL	333/400 MHz	CLK1_MCLK1/1#
			Cantiga 333/400 MHz
	PEG			CLK1_MCLK3/3#
			MCH
	MCH3_CLKREQ#				SODIMM #1
	CLK1_MCH3GPLL/MCH3GPLL#	PCIE PLL	333/400 MHz	CLK1_MCLK4/4#
	CLK1_DREFCLK/DREFCLK#	DPLLA
	CLK1_DREFSSCCLK/DREFSSCCLK#	DPLLB		MIN3_CLKREQ*#
							C
				100 MHz (SRC 6) CLK1_MINIPCIE/MINIPCIE#			WLAN
		DMI
	CLK1_PCIEICH/PCIEICH#	PCIEPLL	ICH9-M	LOM3_CLKREQ*#
	CLK3_USB48			100 MHz (SRC 9) CLK1_PCIELOM/PCIELOM#		WIRED LAN
		USBPLL					25 MHz
	CHP3_SATACLKREQ#
	CLK1_SATA/SATA#	SATAPLL
	CLK3_PCLKICH	32.768 KHz
		OSC	AUD3_BCLK	HD Audio			B

PCI_STP*	33 MHz	33 MHz	CLK3_PCLKMICOM	KBC	10 MHz	RTC Clock
	Buffer					32.768 KHz
						KBC3_SPI_CLK	SPI
						17.86 MHz
	14 MHz
A	OSC										A
14.318 MHz	Page 8					DRAW		DATE	TITLE	SAMSUNG
							Jun PARK	9/23/2008	Bremen-L3
						CHECK		DEV. STEP			ELECTRONICS
							YM.AHN	PV	MAIN
						APPROVAL		REV	CLOCK DIAGRAM	PART NO.
							HJ.KIM	1.0			BA41-xxxxxA
						MODULE CODE		LAST EDIT		PAGE 6	OF 59
							undefined		October 27, 2009 14:27:43 PM
	4			3		2			1
									D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN

R530/R730

8-6

- - - This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic

4

SAMSUNG PROPRIETARY

THIS DOCUMENT CONTAINS CONFIDENTIAL

PROPRIETARY INFORMATION THAT IS

SAMSUNG ELECTRONICS CO’S PROPERTY.

DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.

D

C

B

A

4

3

2

1

THERMAL SENSOR & FAN CONTROL

D

P5.0V

P3.3V_AUX

P3.3V

P3.3V_AUX

nostuff

R567

1% 1%

1%

1%

49.9

1%

10K 10K

10K

10K

Check if PU is doubled to Micom Side.

nostuff

C562

C559 THM3_VDD_5V_MN

C564

THM3_VDD_3V_MN

nostuff

10000nF-X5R

100nF

100nF

6.3V

R549 R548

R550

R558

10V

10V

U503

1

EMC2112-BP-TR

14

19-D1,44-B3

C1048

VDD_3V

SMDATA

KBC3_THERM_SMDATA

1000nF-X5R

To remove glitch when system is booted up.

C

16

VDD_5V_1

SMCLK

15

19-D1,44-B3

KBC3_THERM_SMCLK

6.3V

19

VDD_5V_2

12

31-C3,44-C3

ALERT#

THM3_ALERT#

9

RESET#

SYS_SHDN#

8

44-D1

THM3_STP#

DN1

2

9-C4

CPU2_THERMDC

10mil width and 10mil spacing.

C565

P3.3V_AUX

17

DP1

3

For Intel 45nm(From penryn)

FAN5_VDD

7-B2

FAN_1

4

THM3_THERMDN_MN

2.2nF

9-C4

CPU2_THERMDA

18

DP3_DN2

50V

FAN3_FDBACK#

7-B2

20

FAN_2

5

THM3_THERMDP_MN

R568

TACH

DN3_DP2

R578

0

19-D2

GFX3_THERMDN

10

10K

ADDR_SEL

2

3

1%

THM3_SHDN_SEL_MN

6

SHDN_SEL

C566

MMBT3904

C615

1

Q506

THM3_TRIP_SET_MN

7

TRIP_SET

CLK

11

2.2nF

1

Q12

2.2nF

MMBT3904

13

50V

3

50V

2

R579

0

R566

R564

GND

19-D2

GFX3_THERMDP

THERMAL_PAD

21

0

1.5K

Opposite side of CPU.

Opposite side of GPU.

nostuff

1%

1209-001887

nostuff

TRIP_SET 1500 : 95 degree

nostuff

nostuff

SMBUS Address 7Ah

nostuff

B

P3.3V

M504

M502

M503

M505

HEAD

HEAD

HEAD

HEAD

Line Width = 20 mil

R43

DIA

DIA

DIA

DIA

LENGTH

LENGTH

LENGTH

LENGTH

10K

BA61-01090A

BA61-01090A

BA61-01090A

BA61-01090A

SHDN_SEL MODE

1%

J2

0

INTEL TR MODE

HDR-4P-1R-SMD

FAN5_VDD

7-C3

1

HIGH Z

AMD CPU/DIODE MODE

7-C3

2

1

EXT.DIODE 2 MODE

FAN3_FDBACK#

3

5

4

C62

6

MNT1

MNT2

10000nF-X5R

6.3V

3711-000456

ADDRESSS_SEL MODE

To support heatsink

0

0101 111xb

HIGH Z

0111 101xb (7A)

1

0101 110xb

A

DESIGN

DATE

TITLE

Bremen-L3

SAMSUNG

Jun PARK

9/23/2008

CHECK

DEV. STEP

ELECTRONICS

YM.AHN

PV

THERMAL SENSOR

APPROVAL

REV

THERMAL SENSOR EMC2112

PART NO.

HJ.KIM

1.0

BA41-xxxxxA

MODULE CODE

LAST EDIT

7

59

October 27, 2009 14:27:43 PM

PAGE

OF

3

2

1

D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN

8-7

R530/R730

- - - This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic

4

3

2

1

SAMSUNG PROPRIETARY

THIS DOCUMENT CONTAINS CONFIDENTIAL

PROPRIETARY INFORMATION THAT IS

SAMSUNG ELECTRONICS CO’S PROPERTY.

DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS

EXCEPT AS AUTHORIZED BY SAMSUNG.

D

CPU1_A#(16:3) 12-D1

C

CPU1_ADSTB0# 12-C1

CPU1_A#(35:17) 12-D1

CPU1_ADSTB1# 12-C1

B

P1.05V

R571

CPU1-1

56

PENRYN

CPU1_D#(15:0)

12-D4

1 / 4

0

J4

H1

3

A3#

ADS#

12-C1

CPU1_ADS#

1

4

L5

A4#

BNR#

E2

12-C1

CPU1_BNR#

2

5

L4

G5

12-C1

3

6

K5

A5#

BPRI#

CPU1_BPRI#

4

A6#

7

M3

0

BR0#

F1

12-C1

CPU1_BREQ#

5

10

N3

A7#

GROUP

F21

12-B1

8

A9#

DEFER#

CPU1_DEFER#

8

N2

A8#

H5

12-C1

6

9

J1

7

11

P5

A10#

ADDR

DRDY#

E1

12-B1

CPU1_DRDY#

9

A16#

CONTROL

LOCK#

CPU1_LOCK#

16

R1

H4

12-B1

14

12

P2

A11#

DBSY#

CPU1_DBSY#

10

13

L2

A12#

IERR#

D20

CPU1_IERR#_MN

11

14

P4

A13#

B3

29-C1

CPU1_INIT#

12

15

P1

A14#

INIT#

13

A15#

M1

ADSTB0#

C1

15

RESET#

12-B4

CPU1_CPURST#

CPU1_DSTBN0#

12-B1

12-A1

F3

12-B1

RS0#

F4

12-A1

CPU1_RS0#

CPU1_DSTBP0#

12-B1

Y2

RS1#

CPU1_RS1#

CPU1_DBI0#

17

A17#

RS2#

G3

12-A1

CPU1_RS2#

CPU1_D#(31:16)

12-D4

18

U5

A18#

TRDY#

G2

12-B1

CPU1_TRDY#

16

19

R3

A19#

G6

17

20

W6

12-B1

18

21

U4

A20#

HIT#

E4

12-B1

CPU1_HIT#

19

22

Y5

A21#

HITM#

CPU1_HITM#

20

23

U1

A22#

A6

29-C1

21

A23#

A20M#

CPU1_A20M#

24

R4

A24#

1

ICH

FERR#

A5

29-C1

CPU1_FERR#

22

29

Y4

A29#

GROUPADDR

LINT1

B4

29-B1

CPU1_NMI

27

25

T5

A25#

IGNNE#

C4

29-C1

CPU1_IGNNE#

23

26

T3

A26#

D5

24

27

W2

STPCLK#

29-B1

CPU1_STPCLK#

25

28

W5

A27#

C6

29-C1

26

A28#

LINT0

CPU1_INTR

30

U2

A30#

SMI#

A3

29-B1

CPU1_SMI#

28

31

V4

A31#

12-B1

CPU1_REQ#(4:0)

29

32

W3

K3

0

30

A32#

REQ0#

33

AA4

A33#

REQ1#

H2

1

31

34

AB2

K2

2

CPU1_DSTBN1#

12-B1

35

AA3

A34#

REQ2#

J3

3

12-B1

V1

A35#

REQ3#

L1

4

CPU1_DSTBP1#

12-B1

ADSTB1#

REQ4#

CPU1_DBI1#

0143854500|bga_479p_sock

CPU Socket : 3704-001153

E22

F24

E26

G22

F23

G25

E25

E23

K24

G24

J24

J23

H22

F26

K22

H23

J26

H26

H25

N22

K25

P26

R23

L23

M24

L22

M23

P25

P23

P22

T24

R24

L25

T25

N25

L26

M26

N24

CPU1-2

PENRYN

2 / 4

	D0#			D32#	Y22
	D1#			D33#	AB24
	D2#			D34#	V24
					V26
	D3#			D35#	V23
	D4#			D36#	T22
	D5#			D37#	U25
	D6#			D38#
	D7#	0	2	D39#	U23
	D8#	GRP	GRP	D40#	Y25
	D9#			D41#	W22
	D10#	DATA	DATA	D42#	Y23
					W24
	D12#			D44#	W25
	D11#			D43#
	D13#			D45#	AA23
	D14#			D46#	AA24
					AB25
	D15#			D47#	Y26
	DSTBN0#			DSTBN2#	AA26
	DSTBP0#			DSTBP2#	U22
	DINV0#			DINV2#
	D16#			D48#	AE24
	D17#			D49#	AD24
					AA21
	D18#			D50#	AB22
	D19#			D51#
					AB21
	D20#			D52#	AC26
	D21#			D53#
	D22#			D54#	AD20
					AE22
	D23#	1	3	D55#
	D24#	GRP	GRP	D56#	AF23
					AC25
	D25#			D57#
	D26#	DATA	DATA	D58#	AE21
					AD21
	D28#			D60#	AC22
	D27#			D59#
	D29#			D61#	AD23
	D30#			D62#	AF22
	D31#			D63#	AC23
					AE25
	DSTBN1#			DSTBN3#	AF24
	DSTBP1#			DSTBP3#
					AC20
	DINV1#			DINV3#

0143854500|bga_479p_sock

M501

SUPLECODE

MNT1 1

MNT2 2

MNT3 3

MNT4 4

BA75-01937A

D

12-D4

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

12-B1

12-B1

12-B1

12-D4

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

12-B1

12-B1

12-B1

CPU1_D#(47:32)

C

CPU1_DSTBN2#

CPU1_DSTBP2#

CPU1_DBI2#

CPU1_D#(63:48)

CPU1_DSTBN3#

CPU1_DSTBP3#

CPU1_DBI3#

B

		CPU bracket
A								A
		DRAW	DATE	TITLE		SAMSUNG
		Jun PARK	9/23/2008	Bremen-L3
		CHECK	DEV. STEP				ELECTRONICS
		YM.AHN	PV	CPU
		APPROVAL	REV	PENRYN (1/3)	PART NO.
		HJ.KIM	1.0				BA41-xxxxxA
		MODULE CODE	LAST EDIT			8		59
		undefined		October 27, 2009 14:27:43 PM	PAGE		OF
4	3	2		1
				D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN

R530/R730

8-8

- - - This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic

D

C

B

A

4

SAMSUNG PROPRIETARY

THIS DOCUMENT CONTAINS CONFIDENTIAL

PROPRIETARY INFORMATION THAT IS

SAMSUNG ELECTRONICS CO’S PROPERTY.

CPU1-3

DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS

EXCEPT AS AUTHORIZED BY SAMSUNG.

PENRYN

A22

3 / 4

CLK0_HCLK0

11-C1

BCLK0

CLK

11-C1

A21

CLK0_HCLK0#

BCLK1

H

12-B4

D7

CPU1_SLP#

SLP#

29-C1

B5

CPU1_DPSLP#

DPSLP#

13-B1,29-C1 54-C4

E5

CPU1_DPRSTP#

DPRSTP#

12-B1

D24

CPU1_DPWR#

DPWR#

29-C1

D6

CPU1_PWRGDCPU

PWRGOOD

54-D4

AE6

CPU1_PSI#

PSI#

54-C4

CPU1_VID(6:0)

AE2

6

VID_6

5

AF3

P1.05V

VID_5

4

AE3

VID_4

3

AF4

VID_3

2

AE5

VID_2

R572

1

AF5

VID_1

0

AD6

56

VID_0

CPU1_PROCHOT#_MN

D21

THERMAL

PROCHOT#

P1.05V CPU1_THRMTRIP#

13-B1,29-B1

C7

THERMTRIP#

CPU2_THERMDA

7-C2

A24

THRMDA

CPU2_THERMDC

7-C2

B25

THRMDC

CPU1_BSEL2

11-C4,12-A3

C21

BSEL2

R519

11-C4,12-A3

B23

CPU1_BSEL1

BSEL1

11-C4,12-A3

B22

1K

CPU1_BSEL0

BSEL0

1%

AD26

CPU1_GTLREF_MN

GTLREF

R517

C531

R538

54.9 1%CPU1_COMP3_MN

Y1

100nF

COMP3

2K

10V

R531

27.4 1%CPU1_COMP2_MN

AA1

COMP2

R553

54.9 1%CPU1_COMP1_MN

U26

1%

COMP1

nostuff

R555

27.4 1%CPU1_COMP0_MN

R26

COMP0

10-C4,54-A4

AF7

CPU1_VCCSENSE

VCCSENSE

10-B4,54-A4

AE7

CPU1_VSSSENSE

VSSSENSE

C23

SI team request

TEST1

D25

C24

TEST2

TEST3

AF26

AF1 TEST4

A26 TEST5

C3 TEST6

TEST7

0143854500|bga_479p_sock

	P1.05V	FSC	FSB	FSA	FRQ
		0	0	0	266M
		0	1	0	200M
		0	1	1	166M
	1%	1%
	54.9	54.9

near the CPU

R524	R526
1%	1%
54.9	54.9
R518	R521

9-C3

9-C3

9-C3

9-C3

CPU1_TDI CPU1_TMS

CPU1_TCK CPU1_TRST#

BSEL

FSB 1067 MHz

FSB 800 MHz

4

		3				P1.5V													2																			1
	VCCA_1	B26
		C26			C582		C580
	VCCA_2
	VCCP_1	J6			25V		6.3V													CPU Core Voltage Table										IMVP-6																		D
	VCCP_2	K6			10nF		10000nF-X5R
		M6
	VCCP_3
		N6
	VCCP_4	T6
	VCCP_5	R6																				Active Mode							Active/Deeper Sleep								Deeper Sleep/Extended Deeper Sleep
	VCCP_6																												Dual Mode Region
		K21
	VCCP_7																																				Dual Mode Region
		J21
	VCCP_8				P1.05V
		M21
	VCCP_9
		N21																	VID(6:0)							Voltage	VID(6:0)								Voltage		VID(6:0)								Voltage
	VCCP_10
		T21
	VCCP_11																		0	0	0	0	0	0	0	1.5000 V	0	1	0	1	0	0	0		1.0000 V		1	0		1	0	0	0	1	0.4875 V
		R21									C560		C557	C563	C569	C571	C567
	VCCP_12					EC502													0	0	0	0	0	0	1	1.4875 V	0	1	0	1	0	0	1		0.9875 V		1	0		1	0	0	1	0	0.4750 V
		V21
	VCCP_13	W21				220uF					100nF		100nF	100nF	100nF	100nF	100nF		0	0	0	0	0	1	0	1.4750 V	0	1	0	1	0	1	0		0.9750 V		1	0		1	0	0	1	1	0.4625 V
	VCCP_14	V6				2.5V					10V		10V	10V	10V	10V	10V		0	0	0	0	0	1	1	1.4625 V	0	1	0	1	0	1	1		0.9625 V		1	0		1	0	1	0	0	0.4500 V
	VCCP_15																		0	0	0	0	1	0	0	1.4500 V	0	1	0	1	1	0	0		0.9500 V		1	0		1	0	1	0	1	0.4375 V
		G21
	VCCP_16					nostuff							nostuff			nostuff			0	0	0	0	1	0	1	1.4375 V	0	1	0	1	1	0	1		0.9375 V		1	0		1	0	1	1	0	0.4250 V
	PREQ#	AC1			-> delete and change layout (ECAE)														0	0	0	0	1	1	0	1.4250 V	0	1	0	1	1	1	0		0.9250 V		1	0		1	0	1	1	1	0.4125 V
		AC2																	0	0	0	0	1	1	1	1.4125 V	0	1	0	1	1	1	1		0.9125 V		1	0		1	1	0	0	0	0.4000 V
	PRDY#	AC4																	0	0	0	1	0	0	0	1.4000 V	0	1	1	0	0	0	0		0.9000 V		1	0		1	1	0	0	1	0.3875 V
SIGNALS	BPM3#	AD1																	0	0	0	1	0	0	1	1.3875 V	0	1	1	0	0	0	1		0.8875 V		1	0		1	1	0	1	0	0.3750 V
	BPM0#	AD4																	0	0	0	1	1	0	0	1.3500 V	0	1	1	0	1	0	0		0.8500 V		1	0		1	1	1	0	1	0.3375 V
	BPM2#	AD3																	0	0	0	1	0	1	0	1.3750 V	0	1	1	0	0	1	0		0.8750 V		1	0		1	1	0	1	1	0.3625 V
	BPM1#																		0	0	0	1	0	1	1	1.3625 V	0	1	1	0	0	1	1		0.8625 V		1	0		1	1	1	0	0	0.3500 V
XDP/ITP		AC5						9-A4			CPU1_TCK								0	0	0	1	1	0	1	1.3375 V	0	1	1	0	1	0	1		0.8375 V		1	0		1	1	1	1	0	0.3250 V
	TDO																		0	0	1	0	0	0	0	1.3000 V	0	1	1	1	0	0	0		0.8000 V		1	1		0	0	0	0	1	0.2875 V
		AB3						9-A4
	TCK	AA6																	0	0	0	1	1	1	0	1.3250 V	0	1	1	0	1	1	0		0.8250 V		1	0		1	1	1	1	1	0.3125 V
	TDI										CPU1_TDI								0	0	0	1	1	1	1	1.3125 V	0	1	1	0	1	1	1		0.8125 V		1	1		0	0	0	0	0	0.3000 V
		AB5						9-A4																																								C
	TMS										CPU1_TMS								0	0	1	0	0	0	1	1.2875 V	0	1	1	1	0	0	1		0.7875 V		1	1		0	0	0	1	0	0.2750 V
		AB6						9-A4
	TRST#										CPU1_TRST#								0	0	1	0	0	1	0	1.2750 V	0	1	1	1	0	1	0		0.7750 V		1	1		0	0	0	1	1	0.2625 V
		C20					31-D3
	DBR#										ITP3_DBRESET#								0	0	1	0	0	1	1	1.2625 V	0	1	1	1	0	1	1		0.7625 V		1	1		0	0	1	0	0	0.2500 V
	RSVD_1	M4																	0	0	1	0	1	0	0	1.2500 V	0	1	1	1	1	0	0		0.7500 V		1	1		0	0	1	0	1	0.2375 V
		N5																	0	0	1	0	1	0	1	1.2375 V	0	1	1	1	1	0	1		0.7375 V		1	1		0	0	1	1	0	0.2250 V
	RSVD_2	T2																	0	0	1	0	1	1	0	1.2250 V	0	1	1	1	1	1	0		0.7250 V		1	1		0	0	1	1	1	0.2125 V
	RSVD_3	V3																	0	0	1	0	1	1	1	1.2125 V	0	1	1	1	1	1	1		0.7125 V		1	1		0	1	0	0	01	0.2000 V
RSVD	RSVD_4	B2																	0	0	1	1	0	0	0	1.2000 V	1	0	0	0	0	0	0		0.7000 V		1	1		0	1	0	0	1	0.1875 V
	RSVD_6	D2																	0	0	1	1	0	1	0	1.1750 V	1	0	0	0	0	1	0		0.6750 V		1	1		0	1	0	1	1	0.1625 V
	RSVD_5																		0	0	1	1	0	0	1	1.1875 V	1	0	0	0	0	0	1		0.6875 V		1	1		0	1	0	1	0	0.1750 V
	RSVD_7	D22																	0	0	1	1	0	1	1	1.1625 V	1	0	0	0	0	1	1		0.6625 V		1	1		0	1	1	0	0	0.1500 V
		D3
	RSVD_8	F6																	0	0	1	1	1	0	0	1.1500 V	1	0	0	0	1	0	0		0.6500 V		1	1		0	1	1	0	1	0.1375 V
	RSVD_9																		0	0	1	1	1	0	1	1.1375 V	1	0	0	0	1	0	1		0.6375 V		1	1		0	1	1	1	0	0.1250 V
																			0	0	1	1	1	1	0	1.1250 V	1	0	0	0	1	1	0		0.6250 V		1	1		0	1	1	1	1	0.1125 V
																			0	0	1	1	1	1	1	1.1125 V	1	0	0	0	1	1	1		0.6125 V		1	1		1	0	0	0	0	0.1000 V
																			0	1	0	0	0	0	0	1.1000 V	1	0	0	1	0	0	0		0.6000 V		1	1		1	0	0	0	1	0.0875 V
																			0	1	0	0	0	0	1	1.0875 V	1	0	0	1	0	0	1		0.5875 V		1	1		1	0	0	1	0	0.0750 V
																			0	1	0	0	0	1	0	1.0750 V	1	0	0	1	0	1	0		0.5750 V		1	1		1	0	0	1	1	0.0625 V
																			0	1	0	0	0	1	1	1.0625 V	1	0	0	1	0	1	1		0.5625 V		1	1		1	0	1	0	0	0.0500 V
																			0	1	0	0	1	0	0	1.0500 V	1	0	0	1	1	0	0		0.5500 V		1	1		1	0	1	0	1	0.0375 V
																			0	1	0	0	1	0	1	1.0375 V	1	0	0	1	1	0	1		0.5375 V		1	1		1	0	1	1	0	0.0250 V
CPU Socket : 3704-001153																			0	1	0	0	1	1	0	1.0250 V	1	0	0	1	1	1	0		0.5250 V		1	1		1	0	1	1	1	0.0125 V
																									1		1	10	1	0	0	0	0		0.5000 V		1	1		1	1	0	0	1	0.0000 V
																			0	1	0	0	1	1		1.0125 V	1	0	0	1	1	1	1		0.5125 V		1	1		1	1	0	10	0	0.0000 V
																																					1	1		1	1	0	1	0	0.0000 V
																								Active							Deeper Slp						1	1		1	1	0	1	1	0.0000 V
																																					1	1		1	1	1	0	0	0.0000 V
																				DPRSLPVR				0				DPRSLPVR			1
																																					1	1		1	1	1	0	1	0.0000 V
																				DPRSTP*				1				DPRSTP*			0						1	1		1	1	1	1	0	0.0000 V
																				PSI2*				0 or 1				PSI2*			0 or 1						1	1		1	1	1	1	1	0.0000 V
																																					*"1111111" : 0V power good asserted.
																																			*Yonah Processor (2.33 GHz / 800 MHz : TBD)
																								GTLREF : Keep the Voltage divider within 0.5"
																								of the first GTLREF0 pin with Zo=55ohm trace.
																								Minimize coupling of any switching signals to this net.
																								COMP0,2(COMP1,3) should be connected with Zo=27.4ohm(55ohm)
																								trace shorter than 1/2" to their respective Banias socket pins.
		Pull-down
		BSEL0, BSEL1, BSEL2																						GND test points within 100mil of the VCC/VSSsense at the end of the line.
																								Route the VCC/VSSsense as a Zo=55ohm traces with equal length.
		BSEL0, BSEL2
																								Observe 3:1 spacing b/w VCC/VSSsense lines and 25mil away
																								(preferred 50mil) from any other signal. And GND via 100mil away
																								from each of the VCC/VSS test point vias.
																																																A
																						DRAW					DATE				TITLE				Bremen-L3								SAMSUNG
																										Jun PARK			9/23/2008
																						CHECK					DEV. STEP																		ELECTRONICS
																										YM.AHN				PV					CPU
																						APPROVAL					REV								PENRYN (2/3)								PART NO.
																										HJ.KIM				1.0															BA41-xxxxxA
																						MODULE CODE					LAST EDIT																	9		59
																										undefined							October 27, 2009 14:27:43 PM								PAGE				OF
		3																	2																			1
																																						D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN

8-9

R530/R730

- - - This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic

4

SAMSUNG PROPRIETARY

THIS DOCUMENT CONTAINS CONFIDENTIAL

PROPRIETARY INFORMATION THAT IS

SAMSUNG ELECTRONICS CO’S PROPERTY.

DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.

D

C

CPU1_VCCSENSE

CPU1_VSSSENSE

B

A

4

3

CPU_CORE

R516

100

1%

9-C4,54-A4

10000nF-X5R6.3V

10000nF-X5R6.3V

10000nF-X5R6.3V

10000nF-X5R6.3V

10000nF-X5R6.3V

10000nF-X5R6.3V

10000nF-X5R6.3V

10000nF-X5R6.3V

10000nF-X5R6.3V

10000nF-X5R6.3V

10000nF-X5R6.3V

10000nF-X5R6.3V

10000nF-X5R6.3V

10000nF-X5R6.3V

10000nF-X5R6.3V

10000nF-X5R6.3V

R515

100

1%

C540

C541

C542

C543

C544

C545

C546

C547

C526

C573

C576

C574

C575

C527

C577

C578

9-C4,54-A4

Prodlizer & Cbulk common used(Socket inside)

3

2

1

A11 VSS_1

A14 VSS_2

A16 VSS_3

A19 VSS_4

A2 VSS_5

A23 VSS_6

A25 VSS_7

A4 VSS_8

A8 VSS_9

AA11 VSS_10 AA14 VSS_11 AA16 VSS_12 AA19 VSS_13 AA2 VSS_14 AA22 VSS_15 AA25 VSS_16

AA5 VSS_17 AA8 VSS_18 AB1 VSS_19 AB11 VSS_20

AB13 VSS_21 AB16 VSS_22 AB19 VSS_23

AB26 VSS_24 AB4 VSS_25 AB8 VSS_26 AC11 VSS_27 AC14 VSS_28 AC16 VSS_29 AC19 VSS_30 AC21 VSS_31 AC24 VSS_32 AC3 VSS_33 AC6 VSS_34 AC8 VSS_35 AD11 VSS_36 AD13 VSS_37 AD16 VSS_38 AD19 VSS_39 AD2 VSS_40 AD22 VSS_41 AB23 VSS_42

AD25 VSS_43 AD5 VSS_44 AD8 VSS_45 AE1 VSS_46 AE11 VSS_47 AE14 VSS_48 AE16 VSS_49 AE19 VSS_50 AE23 VSS_51 AE26 VSS_52

AE4 VSS_53 AE8 VSS_54 AF11 VSS_55 AF13 VSS_56 AF16 VSS_57 AF19 VSS_58 AF2 VSS_59 AF21 VSS_60

K23

K26

K4

L21

L24

L3

L6

M2

M22

M25

M5

N1

N23

N26

N4

P21

P24

P3

P6

R2

R22

CPU_CORE

VSS 121 VSS 122 VSS 123 VSS 124 VSS 125 VSS 126 VSS 127 VSS 128 VSS 129 VSS 130 VSS 131 VSS 132 VSS 133 VSS 134 VSS 135 VSS 136 VSS 137 VSS 138 VSS 139 VSS 140 VSS 141

CPU_CORE

A10

VCC_1

VCC_51

AE9

A12

AF10

VCC_2

VCC_52

A13

AF12

VCC_3

VCC_53

A15

AF14

VCC_4

VCC_54

A17

AF15

VCC_5

VCC_55

A18

AF17

VCC_6

VCC_56

A20

AF18

VCC_7

VCC_57

A7

AF20

VCC_8

VCC_58

A9

CPU1-4

AF9

VCC_9

VCC_59

AA10

B10

VCC_10

VCC_60

AA12

PENRYN

B12

VCC_11

VCC_61

AA13

B14

VCC_12

VCC_62

AA15

B15

VCC_13

VCC_63

AA17

4 / 4

B17

VCC_14

VCC_64

AA18

B18

VCC_15

VCC_65

AA20

B20

VCC_16

VCC_66

B7

AA7

VCC_17 0143854500|bga_479p_sock VCC_67

B9

AA9

VCC_18

VCC_68

AB10

VCC_19

VCC_69

C10

AB12

C12

VCC_20

VCC_70

AB14

C13

VCC_21

VCC_71

AB15

C15

VCC_22

VCC_72

AB17

C17

VCC_23

VCC_73

AB18

C18

VCC_24

VCC_74

AB20

VCC_25

VCC_75

C9

AB7

VCC_26

VCC_76

D10

AB9

D12

VCC_27

VCC_77

AC10

D14

VCC_28

VCC_78

AC12

D15

VCC_29

VCC_79

AC13

D17

VCC_30

VCC_80

AC15

D18

VCC_31

VCC_81

D9

AC17

VCC_32

VCC_82

AC18

VCC_33

VCC_83

E10

AC7

E12

VCC_34

VCC_84

AC9

E13

VCC_35

VCC_85

AD10

E15

VCC_36

VCC_86

AD12

E17

VCC_37

VCC_87

AD14

E18

VCC_38

VCC_88

AD15

E20

VCC_39

VCC_89

AD17

E7

VCC_40

VCC_90

E9

AD18

VCC_41

VCC_91

AD7

F10

VCC_42

VCC_92

AD9

F12

VCC_43

VCC_93

AE10

F14

VCC_44

VCC_94

AE12

F15

VCC_45

VCC_95

AE13

F17

VCC_46

VCC_96

AE15

F18

VCC_47

VCC_97

AE17

F20

VCC_48

VCC_98

AE18

F7

VCC_49

VCC_99

F9

AE20

VCC_50

VCC_100

VSS 163 VSS 162 VSS 161 VSS 160 VSS 159 VSS 158 VSS 157 VSS 156 VSS 155 VSS 154 VSS 153 VSS 152 VSS 151 VSS 150 VSS 149 VSS 148 VSS 147 VSS 146 VSS 145 VSS 144 VSS 143 VSS 142

Y6

Y3

Y24

Y21

W4

W26

W23

W1

V5

V25

V22

V2

U6

U3

U24

U21

T4

T26

T23

T1

R5

R25

				D
	VSS_120	K1
		J5
	VSS_119
		J25
	VSS_118
		J22
	VSS_117
		J2
	VSS_116	H6
	VSS_115	H3
	VSS_114	H24
	VSS_113
		H21
	VSS_112
		G4
	VSS_111
		G26
	VSS_110
		G23
	VSS_109
		G1
	VSS_108
		F8
	VSS_107	F5
	VSS_106
		F25
	VSS_105
		F22
	VSS_104
		F2
	VSS_103
		F19
	VSS_102
		F16
	VSS_101
		F13
	VSS_100
		F11		C
	VSS_99
		E8
	VSS_98
		E6
	VSS_97
		E3
	VSS_96	E24
	VSS_95
		E21
	VSS_94
		E19
	VSS_93
		E16
	VSS_92
		E14
	VSS_91
		E11
	VSS_90	D8
	VSS_89	D4
	VSS_88
		D26
	VSS_87
		D23
	VSS_86
		D19
	VSS_85
		D16
	VSS_84
		D13
	VSS_83
		D11
	VSS_82	D1
	VSS_81
		C8
	VSS_80
	VSS_79	C5
	VSS_78	C25
		C22
	VSS_77
		C2
	VSS_76	C19
	VSS_75
		C16
	VSS_74
		C14
	VSS_73
		C11
	VSS_72
		B8
	VSS_71			B
		B6
	VSS_70	B24
	VSS_69
		B21
	VSS_68
		B19
	VSS_67
		B16
	VSS_66
		B13
	VSS_65
		B11
	VSS_64
		AF8
	VSS_63
		AF6
	VSS_62
		AF25
	VSS_61

						A
DRAW	DATE	TITLE		SAMSUNG
Jun PARK	9/23/2008	Bremen-L3
CHECK	DEV. STEP				ELECTRONICS
YM.AHN	PV	CPU
APPROVAL	REV	PENRYN (3/3)	PART NO.
HJ.KIM	1.0				BA41-xxxxxA
MODULE CODE	LAST EDIT			10		59
undefined		October 27, 2009 14:27:43 PM	PAGE		OF
2		1
		D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN

R530/R730

8-10

- - - This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic

			4	3	2	1
	SAMSUNG PROPRIETARY				CK505M
	THIS DOCUMENT CONTAINS CONFIDENTIAL
	PROPRIETARY INFORMATION THAT IS
	SAMSUNG ELECTRONICS CO’S PROPERTY.
	DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
	EXCEPT AS AUTHORIZED BY SAMSUNG.
D	FSA	FSB	FSC						D
				HOST CLK	P1.5V	P3.3V
	BSEL0	BSEL1	BSEL2

0

0

0

266 MHz

4700nF->10uF (Y5V->X5R)

B522

B521

0

0

1

333 MHz

->delete and change layout? (ECAE)

BLM18PG181SN1

BLM18PG181SN1

0

1

0

200 MHz

VDD_SRC_IO

VDD_CPU_IO VDD_PLL3_IO

VDD_IO

VDD_REF

VDD_48

VDD_PCI

VDD_PLL3 VDD_SRC VDD_CPU

0

1

1

400 MHz

10000nF-X5R

1

0

0

133 MHz

10000nF-X5R

6.3V

100nF10V

10000nF-X5R

6.3V

100nF10V

10000nF-X5R 6.3V

100nF10V

6.3V

100nF10V

100nF10V

10000nF-X5R

6.3V

100nF10V

100nF10V

10000nF-X5R

6.3V

1

0

1

100 MHz

1

1

0

166 MHz

1

1

1

RSVD

C851

C865

C877

C849

C844

C152

C869

C837

C847

C843

C872

C838

C834

CLK3_VDD_SRC_IO_MN

CLK3_VDD_REF_MN

nostuff

nostuff

nostuff

P3.3V

C

41-C3

R107

33

1%

U9

C

CLK3_MMC48

SLG8SP513

31-A3

R103

33

1%

CLK3_USB48

19

4

1%

1%

VDD_IO

VDD_REF

CPU1_BSEL0

9-C4,12-A3

R100

2.2K

33

16

10K

10K

43

VDD_SRC_IO1

VDD_48

9

VDD_SRC_IO2

VDD_PCI

nostuff

52

23

0.022nF

VDD_SRC_IO3

VDD_PLL3

56

VDD_PLL3_IO

VDD_SRC

62

C134

27

VDD_CPU_IO

46

CPU1_BSEL1

9-C4,12-A3

50V

R684

R683

55

NC

VDD_CPU

R699

10K

1%

61

9-C4,12-A3

nostuff

CPU0

9-D4

CLK0_HCLK0

CPU1_BSEL2

17

31-A3

R689

33

1%

CLK3_USB48_R_MN

USB_FS_A

CPU0#

60

9-D4

CLK0_HCLK0#

CLK3_ICH14

64

FSB_TESTMODE

CLK3_ICH14_R_MN

5

58

12-B1

CLK0_HCLK1

REF_FS_C_TEST_SEL

CPU1_MCH

CHP3_CPUSTP#

31-C3

44

CPUSTOP#

CPU1_MCH#

57

12-B1

CLK0_HCLK1#

31-C3

45

40

CHP3_PCISTP#

PCISTOP#

SRC11_CLKREQH#

40-C4

39

LAN3_CLKREQ#

CLK3_PWRGD

31-B3

63

CLKPWRGD_PWRDN#

SRC11#_CLKREQG#

41

SRC10

CLK3_PCLKICH

R692

22

30-C2

CLK3_PCLKICH_R_MN

14

PCIF_5_ITP_EN

SRC10#

42

CLK3_DBGLPC

34-A4

R693

22

CLK3_DBGLPC_R_MN

13

PCI_4_SEL_LCDCLK#

SRC9

37

40-C4

CLK1_PCIELOM

12

PCI_3

SRC9#

38

40-C4

CLK1_PCIELOM#

54

SRC8_ITP

R691

22

CLK3_PCLKMICOM_R_MN 11

CLK3_PCLKMICOM

44-B4

PCI_2

SRC8#_ITP#

53

B

MCH3_CLKREQ#

13-A1

R690

475

1%

MCH3_CLKREQ#_R_MN

10

PCI_1_CLKREQ_B#

SRC7_CLKREQF#

51

42-C3

B

31-B3

R701

475

1%

CHP3_SATACLKREQ#_R_MN8

SRC7#_CLKREQE#

50

MIN3_CLKREQ#

CHP3_SATACLKREQ#

PCI_0_CLKREQ_A#

48

42-C3

SRC6

CLK1_MINIPCIE

SMB3_CLK

17-B4,18-B4 31-B4

7

SCL

SRC6#

47

42-C3

CLK1_MINIPCIE#

SMB3_DATA

17-B4,18-B4 31-B4

6

SDA

34

13-B1

SRC4

CLK1_MCH3GPLL

CLK_XTAL_IN_MN

3

XTAL_IN

SRC4#

35

13-B1

CLK1_MCH3GPLL#

2

XTAL_OUT

31

31-C1

CLK_XTAL_OUT_MN

SRC3_CLKREQC#

CLK1_PCIEICH

18

31-C1

0.033nF50V

0.033nF50V

0.033nF50V

VSS_48

SRC3#_CLKREQD#

32

CLK1_PCIEICH#

1

2

nostuff

10K

10K

15

VSS_PCI

SRC2#

29

29-B1

CLK1_SATA#

Y2

nostuff

1%

1%

59

VSS_CPU

nostuff

22

VSS_IO

SRC2

28

29-B1

CLK1_SATA

26

VSS_PLL3

R108

22

14.31818MHz

1

THERMGND

24

CLK1_27M_R_MN

19-B2

CLK1_27M

VSS_REF

LCDCLK_27M

50V

2801-004874

C822

C823

C821

R703

R702

30

VSS_SRC1

LCDCLK#_27M_SS

25

CLK1_27M_SS_R_MN

R110

22

19-B2

CLK1_27M_SS

50V

36

VSS_SRC2

SRC0#_DOT96#

CLK1_PEG#

C123

C122

49

SRC0_DOT96

20

19-C4

CLK1_PEG

0.018nF

0.018nF

VSS_SRC3

21

19-C4

CLK REQ

DEVICE

SRC PORT

nostuff

1205-003156

65

CLK REQ A

SATA

SRC2

CLK REQ B

GMCH

SRC4

Place 14.318MHz within

This part is 64pin QFN package.

500mils of CK-505

A

CLK REQ E

MINI CARD

SRC6

A

CLK REQ F

EXP3_CLKREQ#

SRC8

IDT : 1205-003159

DRAW

DATE

TITLE

SAMSUNG

SL : 1205-003533

Jun PARK

9/23/2008

Bremen-L3

SEL_LCDCLK*

Pin 20/21

Pin 24/25

CHECK

DEV. STEP

ELECTRONICS

LOW

DOT_96/DOT_96# PEG_CLK/PEG_CLK#

YM.AHN

PV

MAIN_CLOCK_CIRCUIT

HIGH

SRC_0/SRC_0#

27M & 27M_SS

APPROVAL

REV

CK_Clock_505M

PART NO.

HJ.KIM

1.0

BA41-xxxxxA

MODULE CODE

LAST EDIT

PAGE 11

59

undefined

October 27, 2009 14:27:43 PM

OF

4

3

2

1

D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN

8-11

R530/R730

4

3

2

1

R530/R730

SAMSUNG PROPRIETARY

P1.05V

P1.05V

THIS DOCUMENT CONTAINS CONFIDENTIAL

nostuff

PROPRIETARY INFORMATION THAT IS

SAMSUNG ELECTRONICS CO’S PROPERTY.

EC504

C724

C818

C759

C740

nostuff

nostuff

DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS

EXCEPT AS AUTHORIZED BY SAMSUNG.

220uF

10000nF-X5R

100nF

100nF

100nF

EC503

2.5V

6.3V

10V

10V

10V

C794

C809

C766

AD

1000nF-X5R

10000nF-X5R

10000nF-X5R

220uF

6.3V

6.3V

6.3V

2.5V

AD

AA28 AA33 AA34 AB34 AC26 AC28 AC33 AC34 AE26 AE33 AF23 AF25 AF28 AF33 AG24 AG25 AG26 AG33 AG34 AH23 AH25 AH28 AJ23 AJ26 AJ33 AK33 AM33 T32 U33 U34 V33 V34 W33 Y33 Y34

T10 T11 T12 T13 T2 T5 T6 T7 T8 T9 U1 U10 U11 U12 U13 U2 U3 U5 U6 U7 U8 U9 V1 V2 V3

8-C4

CPU1_A#(35:3)

D

CPU1_D#(63:0)

8-C1

A14

D

H_A#_3

3

F2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

0

H_D#_0

H_A#_4

C15

4

1

G8

H_D#_1

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_ VCC_

VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_

H_A#_5

F16

5

2

F8

H13

6

H_D#_2

H_A#_6

3

E6

H_D#_3

H_A#_7

C18

7

4

G2

M16

8

5

H6

H_D#_4

H_A#_8

J13

9

H_D#_5

H_A#_9

6

H2

H_D#_6

VCC CORE

VTT

H_A#_10

P16

10

7

F6

R16

11

8

D4

H_D#_7

H_A#_11

N17

12

H_D#_8

H_A#_12

9

H3

M13

13

10

M9

H_D#_9

H_A#_13

E17

14

11

M11

H_D#_10

H_A#_14

P17

15

12

J1

H_D#_11

BUS

H_A#_15

F17

16

P1.05V

13

J2

H_D#_12

H_A#_16

G20

17

14

N12

H_D#_13

ADDRESS

H_A#_17

B19

18

15

J6

H_D#_14

H_A#_18

J16

19

H_D#_15

H_A#_19

16

P2

E20

20

R580

17

L2

H_D#_16

H_A#_20

H16

21

H_D#_17

H_A#_21

221

18

R2

H_D#_18

HOST

H_A#_22

J20

22

1%

19

N9

H_D#_19

H_A#_23

L17

23

12-B4

MCH1_HXSWING

20

L6

A17

24

21

M5

H_D#_20

U7-1

H_A#_24

B17

25

H_D#_21

H_A#_25

R585

C635

22

J3

L16

26

23

N2

H_D#_22

H_A#_26

C21

27

100

100nF

H_D#_23

EB88CTPM

H_A#_27

1%

10V

24

R1

H_D#_24

H_A#_28

J17

28

25

N5

H20

29

C

26

N6

H_D#_25

1 OF 5

H_A#_29

B18

30

C

H_D#_26

H_A#_30

27

P13

H_D#_27

H_A#_31

K17

31

28

N8

B20

32

29

L7

H_D#_28

BUS

H_A#_32

F21

33

H_D#_29

H_A#_33

30

N10

H_D#_30

H_A#_34

K21

34

31

M3

H_D#_31

DATA

0904-002376

H_A#_35

L20

35

32

Y3

H_D#_32

33

AD14

H_ADS#

H12

8-C3

CPU1_ADS#

- -

34

Y6

H_D#_33

HOST

B16

8-C4

H_D#_34

H_ADSTB#_0

CPU1_ADSTB0#

35

Y10

G17

8-B4

36

Y12

H_D#_35

H_ADSTB#_1

A9

8-C3

CPU1_ADSTB1#

-

- This Document can not be used without Samsung's authorization

37

Y14

H_D#_36

H_BNR#

F11

8-C3

CPU1_BNR#

8. Block Diagram and Schematic

38

Y7

H_D#_37

H_BPRI#

G12

8-C3

CPU1_BPRI#

H_D#_38

H_BREQ#

CPU1_BREQ#

P1.05V

39

W2

H_D#_39

E9

40

AA8

H_DEFER#

8-C3

CPU1_DEFER#

41

Y9

H_D#_40

B10

8-C3

H_D#_41

H_DBSY#

CPU1_DBSY#

42

AA13

J11

9-D4

R592

43

AA9

H_D#_42

H_DPWR#

F9

8-C3

CPU1_DPWR#

H_D#_43

H_DRDY#

CPU1_DRDY#

1K

44

AA11

H_D#_44

H9

CPU1_HIT#

1%

MCH1_HVREF

45

AD11

H_D#_45

H_HIT#

8-C3

12-A4

46

AD10

H_D#_46

H_HITM#

E12

8-C3

CPU1_HITM#

R588

47

AD13

H_D#_47

H_LOCK#

H11

8-C3

CPU1_LOCK#

48

AE12

H_D#_48

H_TRDY#

C9

8-C3

CPU1_TRDY#

2K

49

AE9

H_D#_49

AH7

1%

50

AA2

H_D#_50

HPLL_CLK

11-C1

CLK0_HCLK1

51

AD8

H_D#_51

CONTROL

HPLL_CLK#

AH6

11-B1

CLK0_HCLK1#

52

AA3

H_D#_52

53

AD3

H_D#_53

H_DINV#_0

J8

8-C2

CPU1_DBI0#

B

54

AD7

H_D#_54

H_DINV#_1

L3

8-B2

CPU1_DBI1#

B

55

AE14

Y13

8-C1

56

AF3

H_D#_55

HOST

H_DINV#_2

Y1

8-B1

CPU1_DBI2#

57

AC1

H_D#_56

H_DINV#_3

CPU1_DBI3#

H_D#_57

H_DSTBN#_0

L10

CPU1_DSTBN0#

58

AE3

H_D#_58

8-C2

59

AC3

H_D#_59

H_DSTBN#_1

M7

8-B2

CPU1_DSTBN1#

60

AE11

H_D#_60

H_DSTBN#_2

AA5

8-C1

CPU1_DSTBN2#

61

AE8

H_D#_61

H_DSTBN#_3

AE6

8-B1

CPU1_DSTBN3#

62

AG2

H_D#_62

L9

63

AD6

H_DSTBP#_0

8-C2

CPU1_DSTBP0#

H_D#_63

H_DSTBP#_1

M8

8-B2

CPU1_DSTBP1#

CPU1_CPURST#

8-C3

C12

H_CPURST#

AA6

8-C1

9-D4

E11

H_DSTBP#_2

AE5

8-B1

CPU1_DSTBP2#

CPU1_SLP#

H_CPUSLP#

CFG

H_DSTBP#_3

CPU1_DSTBP3#

C5

NC

B15

0

8-B3

CPU1_REQ#(4:0)

MCH1_HXSWING

12-C4

H_SWING

H_REQ#_0

MCH1_H_RCOMP_MN E3

H_RCOMP

H_REQ#_1

K13

1

R67

24.9

1%

F13

2

MCH1_HVREF

B11

H_REQ#_2

1608

H_DVREF

VCC NCTF 17 VCC NCTF 18 VCC NCTF 19

VCC NCTF 23 VCC NCTF 24 VCC NCTF 25 VCC NCTF 26 VCC NCTF 27 VCC NCTF 28

VCC NCTF 31 VCC NCTF 32 VCC NCTF 33 VCC NCTF 34 VCC NCTF 35 VCC NCTF 36 VCC NCTF 37 VCC NCTF 38 VCC NCTF 39 VCC NCTF 40 VCC NCTF 41 VCC NCTF 42 VCC NCTF 43 VCC NCTF 44

H_REQ#_3

B13

3

12-B4

A11

H_AVREF

H_REQ#_4

B14

4

MCH1_VTTLF1_MN

A8

VTTLF_1

CFG 0

CFG 6 CFG 7 CFG 8 CFG 9 CFG 10 CFG 11 CFG 12 CFG 13

H_RS#_0

B6

8-C3

CPU1_RS0#

MCH1_VTTLF2_MN

AB2

F12

8-C3

MCH1_VTTLF3_MN

L1

VTTLF_2

H_RS#_1

C8

8-C3

CPU1_RS1#

*POCAFEB-12 Only (Remove in MP Model)

VTTLF_3

H_RS#_2

CPU1_RS2#

470nF

VTTLF T25

CFG1 CFG2 CFG3 CFG4 CFG5

M24 E21 C23 C24 N21 P21 T21 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20

NCTFVCC1 NCTFVCC2 NCTFVCC3 NCTFVCC4 NCTFVCC5 NCTFVCC6 NCTFVCC7 NCTFVCC8 NCTFVCC9 NCTFVCC10 NCTFVCC11 NCTFVCC12 NCTFVCC13 NCTFVCC14 NCTFVCC15 NCTFVCC16

AJ29 AJ32

NCTFVCC20 NCTFVCC21 NCTFVCC22

AK28 AK29 AK30 AK32 AL26

NCTFVCC29 NCTFVCC30

AL32 AM30 AM32 U30 U32 V29 V30 W29 W30 W32 Y29 Y30 Y32

CFG#

Current Setting

(def. : default Option)

P1.05V

Low

High

CPU1_BSEL0

C92

9-C4,11-C4

MCH1_CFG6_MN

A

CFG(5)

DMIx2

DMIx4 (def.)

CPU1_BSEL1

9-C4,11-C4

A

9-C4,11-C4

CFG(6)

iTPM Host Interface Enable

iTPM Host Interface Disable (def.)

470nFC646 470nFC778

16V 16V 16V

CPU1_BSEL2

R633

CFG(7) ME Crypto no confidentiality

ME Crypto confidentiality (def.)

DRAW

DATE

TITLE

SAMSUNG

2.2K

Jun PARK

9/23/2008

CFG(9)

PEG Reversal (def.)

Normal

Bremen-L3

nostuff

CFG(10)

PCIE Loop Back Enable

PCIE Loop Back Disable(def)

CHECK

DEV. STEP

ELECTRONICS

iTPM option

YM.AHN

PV

MCH_CANTIGA_GM_DDR2

CFG(16)

Dynamic ODT Disabled

Dynamic ODT Enabled (def.)

CFG(19) DMI Lane Normal (def.)

DMI Lane Reversal

APPROVAL

REV

CANTIGA (1/5)

PART NO.

HJ.KIM

1.0

BA41-xxxxxA

CFG(20)

SDVO or PCIE X1

SDVO and PCIE X1

Only(def.)

Simultaneously

MODULE CODE

LAST EDIT

12

59

undefined

October 27, 2009 14:27:43 PM

PAGE

OF

4

3

2

1

R25 P25 P20 P24 C25 N24

R20 M20 L21 H21 P29 R28 T28

AA29 AA30 AA32 AB30 AC29 AC30 AC32 AE29 AE30 AE32 AF30 AG29 AG30 AG32 AH29 AH30 AH32

AK23 AK24 AK25 AK26

AL28 AL29 AL30

D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN

8-12

- - - This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic

4

3

2

1

8-13

SAMSUNG PROPRIETARY

THIS DOCUMENT CONTAINS CONFIDENTIAL

PEG1_RXN(15:0)

19-C4

19-C4

PEG1_RXP(15:0)

PROPRIETARY INFORMATION THAT IS

19-A4

PEG1_TXN(15:0)

19-B4

PEG1_TXP(15:0)

SAMSUNG ELECTRONICS CO’S PROPERTY.

DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS

0 1 2 3 4 5 6 7 8 9 101112 1314 15

0 1 2 3 4 5 6 7 8 9 1011 1213 1415

EXCEPT AS AUTHORIZED BY SAMSUNG.

0 1

2

3

4 5 6 7 8

910 1112 13

1415

0 1 2 3 4 5 6

7

8

9

1011

12 1314 15

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

10V

PEG1TXN0 MN

PEG1TXN1 MN

PEG1TXN2 MN

PEG1TXN3 MN

PEG1TXN4 MN

PEG1TXN5 MN PEG1TXN6 MN

PEG1TXN7 MN PEG1TXN8 MN

PEG1TXN9 MN PEG1TXN10 MN PEG1TXN11 MN

PEG1TXN12 MN PEG1TXN13 MN

PEG1TXN14 MN PEG1TXN15 MN

PEG1TXP0 MN PEG1TXP1 MN PEG1TXP2 MN PEG1TXP3 MN

1608 PEG1TXP7MN

PEG1TXP8 MN PEG1TXP9 MN

PEG1TXP10 MN PEG1TXP11 MN PEG1TXP12 MN

PEG1TXP13 MN

PEG1TXP14MNP1.05V_PEG

H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39

H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40

J41C688100nF

C685M46100nF C654M47100nF C656M40100nF C708M42100nF R48C100100nF

N38C722100nF

T40C729100nF

C723U37100nF U40C731100nF

C749Y40100nF AA46C108100nF

AA37C748100nF

C765AA40100nF AD43C776100nF

C777AC46100nF

C687J42100nF L46C686100nF

M48C655100nF

C657M39100nF M43C702100nF

C101R47100nF C707N37100nF C732T39100nF C730U36100nF C728U39100nF C758Y39100nF C104Y46100nF C744AA36100nF AA39C757100nF

C782AD42100nF C783AD46100nF

D

MNTXP4PEG1 MNTXP5PEG1 MNTXP6PEG1

MNTXP15PEG1

D

H32

CRT_DDC_CLK

VGA

PEGRX# 0 PEGRX# 1 PEGRX# 2 PEGRX# 3 PEGRX# 4 PEGRX# 5 PEGRX# 6 PEGRX# 7 PEGRX# 8 PEGRX# 9 PEGRX# 10 PEGRX# 11 PEGRX# 12 PEGRX# 13 PEGRX# 14 PEGRX# 15

PEGRX 0 PEGRX 1 PEGRX 2 PEGRX 3 PEGRX 4 PEGRX 5 PEGRX 6 PEGRX 7 PEGRX 8 PEGRX 9 PEGRX 10 PEGRX 11 PEGRX 12 PEGRX 13 PEGRX 14 PEGRX 15

PEGTX# 0 PEGTX# 1 PEGTX# 2 PEGTX# 3 PEGTX# 4 PEGTX# 5 PEGTX# 6 PEGTX# 7 PEGTX# 8 PEGTX# 9 PEGTX# 10 PEGTX# 11 PEGTX# 12 PEGTX# 13 PEGTX# 14 PEGTX# 15

PEGTX 0 PEGTX 1 PEGTX 2 PEGTX 3 PEGTX 4 PEGTX 5 PEGTX 6 PEGTX 7 PEGTX 8 PEGTX 9 PEGTX 10 PEGTX 11 PEGTX 12 PEGTX 13 PEGTX 14 PEGTX 15

PEG_COMPI

T37

R664

49.9

1%

E28

CRT_DDC_DATA

GFX_VID_2

F33

J32

PEG_COMPO

T36

MCH1_COMPIO_R_MN

J29

CRT_HSYNC

GFX_VID_0

B33

L29

CRT_VSYNC

GFX_VID_1

B32

G33

G28

CRT_BLUE

GFX_VID_3

E33

J28

CRT_GREEN

GFX_VID_4

CRT_RED

PCIE GFX

PCIE GFX

GFX_VR_EN

C34

E29

CRT_TVO_IREF

AE41

31-D1

G29

CRT_IRTN

DMI_RXN_0

DMI1_TXN_0

AE37

31-D1

C31

U7-2

DMI_RXN_1

AE47

31-D1

DMI1_TXN_1

E32

TV_DCONSEL_0

DMI_RXN_2

AH39

31-C1

DMI1_TXN_2

H25

TV_DCONSEL_1

TV

EB88CTPM

DMI_RXN_3

AE38

31-D1

DMI1_TXN_3

TVB_DAC

DMI_RXP_1

DMI1_TXP_1

F25

TVA_DAC

DMI_RXP_0

AE40

31-D1

DMI1_TXP_0

K25

TVC_DAC

DMI_RXP_2

AE48

31-D1

DMI1_TXP_2

DMI

AH40

31-C1

H24

TV_RTN

AA15 AA20 AA21 AA23 AA24 AA25 AB15 AB20 AB23 AB25 AC20 AC21 AC23 AC24 AE15 AE20 AE21 AE23 AE24 AE25 AF15 AF20 AG15 AG21 AH15 AH20 AJ15 AJ21 AL15 AM14 AM15 AN14 T14 T16 T17 U14 U15 V15 Y15 Y21 Y24 Y26

AA16 AA19 AB16 AB17 AB19 AC16 AC17

DMI_RXP_3

AE35

31-D1

DMI1_TXP_3

DMI_TXN_0

DMI1_RXN_0

C

K33

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

1 2 3 4 5 6 7

DMI_TXN_1

AE43

31-D1

DMI1_RXN_1

C

L_DDC_CLK

DMI_TXN_2

AE46

31-D1

DMI1_RXN_2

J33

VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_ VCCAXG_

AXGNCTF AXGNCTF AXGNCTF AXGNCTF AXGNCTF AXGNCTF AXGNCTF

AH42

31-C1

L_DDC_DATA

DMI_TXP_2

AF46

31-D1

DMI1_RXP_2

DMI_TXN_3

DMI1_RXN_3

M32

L_CTRL_CLK

DMI_TXP_0

AD35 31-D1

DMI1_RXP_0

M33

L_CTRL_DATA

DMI_TXP_1

AE44

31-D1

DMI1_RXP_1

M29

L_VDD_EN

VCC VCC VCC VCC VCC VCC VCC

DMI_TXP_3

AH43

31-C1

DMI1_RXP_3

G32

L32

L_BKLT_EN

DPLL_REF_CLK

B38

L_BKLT_CTRL

A38

H47

LVDSA_DATA#_0

DPLL_REF_CLK#

E46

GFX VCC

GFX VCC NCTF

CLK

DPLL_REF_SSCLK

E41

G40

LVDSA_DATA#_1

2 OF 5

F41

A40

LVDSA_DATA#_2

0904-002376

DPLL_REF_SSCLK#

LVDSA_DATA#_3

PEG_CLK

F43

11-B1

CLK1_MCH3GPLL

H48

E43

11-B1

P1.05V

D45

LVDSA_DATA_0

GFX VCC NCTF

PEG_CLK#

CLK1_MCH3GPLL#

F40

LVDSA_DATA_1

AH37

31-C1

CHP3_CL_CLK_0

LVDSA_DATA_2

CL_CLK

B40

LVDSA_DATA_3

LVDS

CL_DATA

AH36

31-C1

CHP3_CL_DATA_0

C810

R679

C41

LVDSA_CLK#

NCTF8 NCTF9 NCTF10 NCTF11 NCTF12 NCTF13 NCTF14 NCTF15 NCTF16 NCTF17 NCTF18 NCTF19 NCTF20 NCTF21 NCTF22 NCTF23 NCTF24 NCTF25 NCTF26 NCTF27 NCTF28 NCTF29 NCTF30 NCTF31 NCTF32 NCTF33 NCTF34 NCTF35 NCTF36 NCTF37 NCTF38 NCTF39 NCTF40 NCTF41 NCTF42 NCTF43 NCTF44 NCTF45 NCTF46 NCTF47 NCTF48 NCTF49 NCTF50 NCTF51 NCTF52 NCTF53 NCTF54 NCTF55 NCTF56 NCTF57 NCTF58 NCTF59 NCTF60

ME

CL_PWROK

AN36 31-B3,44-C4

KBC3_PWRGD

CL_RST#

AH34

31-C1

MCH1_CL_VREF_MN

10V

1%

C40

LVDSA_CLK

AJ35

CHP3_CL_RST_0#

100nF

1K

A41

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

CL_VREF

LVDSB_DATA#_0

AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG AXG

H38

PM_SYNC#

R29

31-D3

CHP3_PM_SYNC#

R671

G37

LVDSB_DATA#_1

B7

54-C4 9-D4,29-C1

499

J37

LVDSB_DATA#_2

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

PM_DPRSTP#

R32

CPU1_DPRSTP#

LVDSB_DATA#_3

DPRSLPVR

31-C3,54-C4

CHP3_DPRSLPVR

1%

B

B42

AT40

B

LVDSB_DATA_0

AE16 AE17 AE19 AF16 AF17 AF19 AG16 AG17 AG19 AH16 AH17 AH19 AJ16 AJ19 AK16 AK17 AK19 AK20 AK21 AL16 AL19 AL21 AM16 AM17 AM19 AM20 AM21 U16 U19 U20 U21 V16 V17 V19 V21 V23 V24 V25 V26 V28 W16 W17 W19 W20 W21 W23 W24 W25 W26 W28 Y16 Y17 Y19

PM

PWROK

31-B3,44-C4

KBC3_PWRGD

G38

AT11

F37

LVDSB_DATA_2

RSTIN#

PLT3_RST#_R_MN

R704

LVDSB_DATA_1

K37

LVDSB_DATA_3

THERMTRIP#

T20

100

N33

1%

PLT3_RST#

A37

PM_EXT_TS#_0

LVDSB_CLK

PM_EXT_TS#_1

P32

19-D4,30-C1

B37

LVDSB_CLK#

MCH3_EXTTS0#_MN

34-A4,40-D4

DDPC_CTRLCLK

N28MCH3_EXTTS1#_MN

42-C2,44-B3

C44

LVDS_IBG

DDPC_CTRLDATA

M28

9-C4,29-B1

CPU1_THRMTRIP#

B43

LVDS_VBG

E37

SDVO_CTRLCLK

G36

P3.3V

E38

LVDS_VREFH

1RSVD 2RSVD 3RSVD 4RSVD RSVD115RSVD RSVD106RSVD RSVD137RSVD RSVD128RSVD 9RSVD 10RSVD 11RSVD 12RSVD 13RSVD 14RSVD 15RSVD 16RSVD 17RSVD 18RSVD 19RSVD 20RSVD 21RSVD 22RSVD

MISC

E36

LVDS_VREFL

HDA

1NC 2NC 3NC 4NC 5NC 6NC 7NC 8NC 9NC 10NC 11NC 12NC 13NC 14NC 15NC 16NC 17NC 18NC 19NC 20NC 21NC 22NC 23NC 24NC 25NC 26NC 27NC 28NC 29NC 30NC 31NC 32NC 33NC 34NC 35NC 36NC 37NC 38NC 39NC 40NC 41NC 42NC 43NC

SDVO_CTRLDATA

MN

B28

HDA_BCLK

NC

RSVD

CLKREQ#

K36

R638

10K

1%

A28

HDA_SYNC

R639

10K

1%

B30

H36

R599

HDA_RST#

ICH_SYNC#

B29

HDA_SDI

TSATN#

B12

0

nostuff

C29

HDA_SDO

A43 A44 A46 A47 A5 A6 B4 B45 B47 B48 BC1 BC48 BD1 BD48 BE2 BE47 BF1 BF3 BF46 BF48 BG1 BG2 BG4 BG45 BG47 BG48 BH2 BH3 BH43 BH44 BH46 BH47 BH5 BH6 C3 C46 C48 D2 D47 E1 E48 F1 F48

AH10

MEAH13AH9

DebugAL34AM35AN35

B2PortB31

BF23 BG23 BH18 K12 M1 M36 N36 R33 T24 T33

MCH3TSATN#

R595

56

MCH3_CLKREQ#

AH12

AK34

AY21

BF18

11-B4

MCH3_ICHSYNC#

P3.3V

31-B3

P1.05V

R622

10K

11-B4

MCH3_CLKREQ#

A

A

DRAW

DATE

TITLE

Bremen-L3

SAMSUNG

Jun PARK

9/23/2008

R530/R730

CHECK

DEV. STEP

ELECTRONICS

YM.AHN

PV

MCH_CANTIGA_GM_DDR2

APPROVAL

REV

CANTIGA (2/5)

PART NO.

HJ.KIM

1.0

BA41-xxxxxA

MODULE CODE

LAST EDIT

13

59

undefined

October 27, 2009 14:27:43 PM

PAGE

OF

4

3

2

1

D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN

- - - This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic

D

C

B

A

4

3

2

1

SAMSUNG PROPRIETARY

THIS DOCUMENT CONTAINS CONFIDENTIAL

PROPRIETARY INFORMATION THAT IS

PLACE EACH CAP NEAR AV42 PIN

SAMSUNG ELECTRONICS CO’S PROPERTY.

DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS

MEM1_ADQ(63:0)

17-D4

MEM1_VREF

17-C3,18-C3 51-B1

EXCEPT AS AUTHORIZED BY SAMSUNG.

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

5758

59

60

61

62

63

C839

C830

100nF

100nF

AJ38

AJ41

AN38

AM38

AJ36

AJ40

AM44

AM42

AN43

AN44

AU40

AT38

AN41

AN39

AU44

AU42

AV39

AY44

BA40

BD43

AV41

AY43

BB41

BC40

AY37

BD38

AV37

AT36

AY38

BB38

AV36

AW36

BD13

AU11

BC11

BA12

AU13

AV13

BD12

BC12

AU10

BA11

AN10

AM11

AN12

AM13

AJ11

AJ12

MEM1_SM_REXT_MN

10V

10V

BB9

BA9

AV9

BD9

AY8

BA6

AV5

AV7

AT9

AN8

AU5

AU6

AT5

AM5 AJ9

AJ8

R714

499 1%

nostuff

MEM1_ABS(2:0)

17-C2

nostuff

D

0

BD21

SA_BS_0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

SM_REXT

BF17

DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_ DQ_

1

BG18

AV42

51-B1 17-C3,18-C3

MEM1_VREF

SM_PWROK

SA_BS_1

SM_VREF

2

AT25

MEM1_ADM(7:0)

SA_BS_2

SA SA SA SA SA SA SA SA SA SA SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_ SA_

SM_DRAMRST#

0

AM37

AR36

17-B4

BC36

DDR2 : GND

SA_DM_0

SM_PWROK

DDR3 : Connect to VRM.

1

AT41

SA_DM_1

2

AY41

BG16

18-C1

MEM1_BCAS#

SA_DM_2

SB_CAS#

3

AU39

AU17

18-B4

SA_DM_3

SB_RAS#

MEM1_BRAS#

4

BB12

SYSTEM MEMORY A

BF14

18-B4

SA_DM_4

SB_WE#

MEM1_BWE#

5

AY6

SA_DM_5

6

AT7

SA_DM_6

SB_CS#_0

AV16

18-C1

MEM1_CS2#

7

AJ5

AR13

18-C1

SA_DM_7

SB_CS#_1

MEM1_CS3#

MEM1_ADQS#(7:0)

AJ43

BF15

17-A4

0

SA_DQS#_0

SB_ODT_0

18-B4

MEM1_ODT2

1

AT43

AY13

18-B4

SA_DQS#_1

SB_ODT_1

MEM1_ODT3

2

BA44

SA_DQS#_2

AY36

3

BD37

18-C1

MEM1_CKE2

SA_DQS#_3

SB_CKE_0

4

AY12

BB36

18-C1

SA_DQS#_4

SB_CKE_1

MEM1_CKE3

5

BD8

SA_DQS#_5

AV24

6

AU9

SA_DQS#_6

SB_CK_0

18-C4

CLK1_MCLK2

7

AM8

AU24

18-C4

SA_DQS#_7

SB_CK#_0

CLK1_MCLK2#

AU20

MEM1_ADQS(7:0)

17-B4

SB_CK_1

18-C4

CLK1_MCLK3

0

AJ44

AV20

18-C4

SA_DQS_0

U7-3

SB_CK#_1

CLK1_MCLK3#

1

AT44

18-B4

SA_DQS_1

AM47

0

MEM1_BDM(7:0)

2

BA43

SA_DQS_2

SB_DM_0

3

BC37

A

EB88CTPM

AY47

1

SA_DQS_4

SB_DM_2

5

BC8

BF35

3

4

AW12

SA_DQS_3

SB_DM_1

BD40

2

17-D2

SA_DQS_7

MEMORY

3 OF 5

SB_DM_5

C

AP1

6

6

AU8

SA_DQS_5

SB_DM_3

BG11

4

7

AM7

SA_DQS_6

SB_DM_4

BA3

5

MEM1_AMA(14:0)

SYSTEM

SB_DM_6

BA21

0

AK2

7

SA_MA_2

0904-002376

SB_DQS#_0

2

BG24

AL46

0

1

BC24

SA_MA_0

SB_DM_7

18-A4

MEM1_BDQS#(7:0)

SA_MA_1

3

BH24

SA_MA_3

SB_DQS#_1

AV47

1

4

BG25

BH41

2

SA_MA_4

SB_DQS#_2

5

BA24

BH37

3

SA_MA_5

SB_DQS#_3

6

BD24

BG9

4

SA_MA_6

SB_DQS#_4

7

BG27

B

BC2

5

SA_MA_7

SB_DQS#_5

8

BF25

MEMORY

AT2

6

SA_MA_8

SB_DQS#_6

11

BG26

AL47

0

SA_MA_11

SB_DQS_0

9

AW24

SA_MA_9

SB_DQS#_7

AN5

7

10 BC21

SA_MA_10

18-B4

MEM1_BDQS(7:0)

12

BH26

SA_MA_12

SYSTEM

SB_DQS_1

AV48

1

13

BH17

BH9

4

SA_MA_14

SB_DQS_3

SA_MA_13

SB_DQS_2

14

AY25

BG37 3

SB_DQS_4

BD20

MEM1_ACAS#

17-C2

SA_CAS#

BB2

5

SB_DQS_5

17-B4

BB20

AU1

6

MEM1_ARAS#

SA_RAS#

SB_DQS_6

17-B4

AY20

AN6

7

MEM1_AWE#

SA_WE#

SB_DQS_7

18-D1

MEM1_BMA(14:0)

17-C2

BA17

AV17

0

MEM1_CS0#

SA_CS#_0

SB_MA_0

17-C2

AY16

BA25

1

MEM1_CS1#

SA_CS#_1

SB_MA_1

BC25

2

BD17

SB_MA_2

MEM1_ODT0

17-B4

SA_ODT_0

AU25

3

SB_MA_3

17-B4

AY17

AW25

4

MEM1_ODT1

SA_ODT_1

SB_MA_4

B

BB28

5

17-C2

BC28

SB_MA_5

MEM1_CKE0

SA_CKE_0

AU28

6

SB_MA_6

17-C2

AY28

AW28

7

P1.8V_AUX

MEM1_CKE1

SA_CKE_1

SB_MA_7

AT33

8

AP24

SB_MA_8

CLK1_MCLK0

17-C4

SA_CK_0

BD33 9

SB_MA_9

AR24

CLK1_MCLK0#

17-C4

SA_CK#_0

SB_MA_10

BB16

10

R716

CLK1_MCLK1

17-C4

AT21

SA_CK_1

SYSTEM MEMORY B

SB_MA_11

AW33

11

17-C4

AR21

AY33

12

80.6

CLK1_MCLK1#

SA_CK#_1

SB_MA_12

BH15 13

1%

SB_MA_13

MCH1_SM_RCOMP_MN

BG22

SM_RCOMP

SB_MA_14

AU33

14

MCH1_SM_RCOMP#_MN

BH21

DQSB0 DQSB1 DQSB2 DQSB3 DQSB4 DQSB5 DQSB6 DQSB7 DQSB8 DQSB9 DQSB10 DQSB11 DQSB12 DQSB13 DQSB14 DQSB15 DQSB16 DQSB17 DQSB18 DQSB19 DQSB20 DQSB21 DQSB22 DQSB23 DQSB24 DQSB25 DQSB26 DQSB27 DQSB28 DQSB29 DQSB30 DQSB31 DQSB32 DQSB33 DQSB34 DQSB35 DQSB36 DQSB37 DQSB38 DQSB39 DQSB40 DQSB41 DQSB42 DQSB43 DQSB44 DQSB45 DQSB46 DQSB47 DQSB48 DQSB49 DQSB50 DQSB51 DQSB52 DQSB53 DQSB54 DQSB55 DQSB56 DQSB57 DQSB58 DQSB59 DQSB60 DQSB61 DQSB62 DQSB63

18-C1

MEM1_BBS(2:0)

1%

SM_RCOMP#

SB_BS_0

BC16 0

R720

MCH1_SM_RCOMP_V_OH_MN

BF28

SM_RCOMP_V_OH

SB_BS_1

BB17

1

MCH1_SM_RCOMP_V_OL_MN

BH28

BB33

2

80.6

SM_RCOMP_V_OL

SB_BS_2

P1.8V_AUX

AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3

Route as short as possible

0

1

2

3

4

5

6

7

8

9

10

11

12

13

1415

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

R708

18-D4

1K

10nF->100nF

MEM1_BDQ(63:0)

1%

C852

C866

100nF

R715

10V

2200nF-X5R

3.01K

10V

A

1%

Cantiga

SM_RCOMP : 80 ohm to P1.8V_AUX

DDR2

SM_RCOMP# : 80 ohm to VSS

DRAW

DATE

TITLE

Bremen-L3

SAMSUNG

Jun PARK

9/23/2008

R719

C874

C873

CHECK

DEV. STEP

MCH_CANTIGA_GM_DDR2

ELECTRONICS

100nF

YM.AHN

PV

1K

10V

2200nF-X5R

nostuff

1%

10V

APPROVAL

REV

CANTIGA (3/5)

PART NO.

nostuff

HJ.KIM

1.0

BA41-xxxxxA

MODULE CODE

LAST EDIT

14

59

October 27, 2009 14:27:43 PM

PAGE

OF

4

3

2

1

R530/R730

8-14

- - - This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic

D

C

B

A

4	3	2	1	8-15

SAMSUNG PROPRIETARY

THIS DOCUMENT CONTAINS CONFIDENTIAL

PROPRIETARY INFORMATION THAT IS

SAMSUNG ELECTRONICS CO’S PROPERTY.

DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS P1.8V_AUX

EXCEPT AS AUTHORIZED BY SAMSUNG.

EC506

C826

C827

C845

C841

220uF

10000nF-X5R 10000nF-X5R

100nF

100nF

nostuff

2.5V

6.3V

6.3V

10V

10V

AD

22uF->10uF

D

P1.05V

BD16 BB24 BB21 BA36 AW16 AW13 AT13 BH32 BH31 BH29 BG32 BG31 BG30 BG29 BF32 BF31 BF29 BD32 BD29 BC32 BC29 BB32 BB29 BA32 BA29 AY32 AY29 AW32 AW29 AV32 AV29 AU32 AU29 AT32 AT29 AR32 AR29 AP33 AP32 AP29 AN33 AN32

P3.3V

P1.05V

MCH1_P1.05V_AXF_MN

C650

C645

7 6 5 4 3 2 1

35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

SMVCCNC SMVCCNC SMVCCNC SMVCCNC SMVCCNC SMVCCNC SMVCCNC

VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM_ VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM

C644

BAT54A

nostuff

10000nF-X5R

1000nF-X5R

MCH1_P3.3V_HV_R_MN

6.3V

6.3V

R109

12.1

3

2

1

1%

30V

100nF

D11

A21

AXG

HAD

10V

P1.05V_PEG

VCC_AXF_1

A32 HDMI OPTION

B21

VCC_SM

VCC_HDA

B22

VCC_AXF_2

VCC

VCC

VCC_AXF_3

P1.05V_PEG

INSTPARP1.05V

C793

VCC HV

VCC_HV_1

A35

2A routing

SHORT502

100nF

AF48

10V

VCC_DMI_1

VCC AXG

VCC_HV_2

B35

C121

C120

AG47

VCC_DMI_2

VCC_HV_3

C35

10000nF-X5R 10000nF-X5R

INSTPAR

AH47

VCC_DMI_3

6.3V

6.3V

SHORT503P1.05V

AH48

VCC_DMI_4

U7-4

VCC_PEG_1

U46

Y5V -> X5R

POWER

U47

P1.5V

22uF->10uF

B10

A26

VCCA_CRT_DAC_2

VCC_PEG_2

U48

EB88CTPM

VCC_PEG_5

V48

Cantiga : 1.5V

BLM18PG181SN1

C

B27

VCCA_CRT_DAC_1

VCC_PEG_3

V47

PEG

VCC_PEG_4

AD48

1

4 OF 5

VCCA_PEG_BG

R80

C784

C113

0904-002376

100nF

10V

A25

VCCA_DAC_BG

100nF

C112

POWER

VCCA_PEG_PLL

AA48

10V

10000nF-X5R

6.3V

A24

VCCA_TV_DAC_1

/ TV

VCCD_PEG_PLL

AA47

MCH1_P1.05V_PEG_PLL_MN

B24

VCCA_TV_DAC_2

CRT

F47

VCCA_DPLLA

POWER

P1.5V

VCCA_DPLLB

L48

C658

MCH1_P1.5V_TVDAC_M25MN

VCCD_TVDAC

PLL

Y5V -> X5R

C667

VCCA_HPLL

AD1

100nF

L28

C767

C785

10V

10nF

VCCD_QDAC

6.3V

25V

AE1

10000nF-X5R

100nF

VCCA_MPLL

MCH1_P1.05V_MPLL_MN

J48

VCCA_LVDS

10V

POWER

P1.05V

L37

VCCD_LVDS_1

VCCD_HPLL

AF1

M38

VCCD_LVDS_2

LVDS

VCC_SM_LF

VCC_SM_CK VCCA_SM_CK_NCTF

VCCA_SM_CK

VCCA_SM

AXG SENSE

VCC_AXG_SENSE

R680 100 1%

C796

22uF->10uF

B

7LFSMVCC 6LFSMVCC 5LFSMVCC 4LFSMVCC 3LFSMVCC 2LFSMVCC 1LFSMVCC

4CKSMVCC 3CKSMVCC 2CKSMVCC 1CKSMVCC

CKSMVCCANCTF 8 CKSMVCCANCTF 7 CKSMVCCANCTF 6 CKSMVCCANCTF 5 CKSMVCCANCTF 4 CKSMVCCANCTF 3 CKSMVCCANCTF 2 CKSMVCCANCTF 1

CKSMVCCA5 CKSMVCCA4 CKSMVCCA3 CKSMVCCA2 CKSMVCCA1

9SMVCCA 8SMVCCA 7SMVCCA 6SMVCCA 5SMVCCA 4SMVCCA 3SMVCCA 2SMVCCA 1SMVCCA

MCH1_VSS_AXG_SENSE_MN

AJ14

100nF

K47

VCC_TX_LVDS

VSS_AXG_SENSE

AH14 R672 100 1%

10V

BLM18PG181SN1

nostuff

R674 B515

nostuff

R673

1

1

P1.05V

C801

C811

100nF

MCH1_VCC_AXG_SENSE_MN

10V

10000nF-X5R

6.3V

C842

100nF

10V

BB13 BA37 AY5 AV44 AV21 AM40 AM10

BH20 BG20 BF21 BF20

AM28 AM26 AM25 AM24 AM23 AL25 AL24 AL23

AP28 AP25 AN28 AN25 AN24

AT16 AR20 AR17 AR16 AP20 AP17 AP16 AN20 AN17

MN

MCH1_P1.05V_MPLL_R_MN

C840

1000nF-X5R 6.3V

P1.05V

C836

220nF

16V

C825

1000nF-X5R 6.3V

CK

C835

220nF

16V

SM

C795

C816

C824

C751

EC505

C815

470nF

16V

_

C819

P1.8V_AUX

P1.8VAUX

nostuff

100nF

10V

1000nF-X5R

10000nF-X5R

10000nF-X5R

22000nF-X5R

220uF

nostuff

6.3V

6.3V

6.3V

20%

2.5V

6.3V

AD

MCH1

P1.05V

Y5V -> X5R

A

22uF->10uF

B523

1

C817

C828

C750

DRAW

DATE

TITLE

Bremen-L3

SAMSUNG

BLM18PG181SN1

Jun PARK

9/23/2008

R721

R530/R730

C870

100nF

2200nF-X5R 10000nF-X5R

22uF->10uF

CHECK

DEV. STEP

ELECTRONICS

YM.AHN

PV

MCH_CANTIGA_GM_DDR2

10V

10V

6.3V

C875

100nF

APPROVAL

REV

PART NO.

10V

nostuff

CANTIGA (4/5)

10000nF-X5R

HJ.KIM

1.0

BA41-xxxxxA

6.3V

MODULE CODE

LAST EDIT

15

59

October 27, 2009 14:27:43 PM

PAGE

OF

4

3

2

1

D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN

- - - This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic

4

3

2

1

SAMSUNG PROPRIETARY

THIS DOCUMENT CONTAINS CONFIDENTIAL

PROPRIETARY INFORMATION THAT IS

SAMSUNG ELECTRONICS CO’S PROPERTY.

DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS

EXCEPT AS AUTHORIZED BY SAMSUNG.

D

AJ25 AJ28 AJ34 AJ37 AJ39 AJ42 AJ47 AJ7 AK15 AL3 AL33 AL48 AM1 AM12 AM34 AM36 AM39 AM41 AM43 AM46 AM6 AM9 AN11 AN13 AN16 AN21 AN29 AN37 AN40 AN42 AN47 AN7 AN9 AP2 AP21 AR2 AR25 AR28 AR33 AR46 AR48 AT10 AT12 AT17 AT20 AT24 AT28 AT37 AT39 AT42 AT6 AT8 AU16 AU2 AU21 AU36 AU38 AU41 AU43 AU48 AU7 AV10 AV12 AV25 AV28

A12

VSS_3

VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135

VSS_137

AV40

A20

A15

VSS_1

AV3

A18

VSS_2

VSS_136

AV33

A23

VSS_4

VSS_138

AV43

VSS_5

VSS_139

A29

VSS_6

VSS

VSS_140

AV46

A31

VSS_7

F38

M44

VSS_141

AV6

A34

VSS_8

VSS_241

VSS_295

VSS_142

AV8

AA1

F44

M6

AW17

AA10

VSS_9

F46

VSS_242

VSS_296

N11

VSS_143

AW2

VSS_10

VSS_243

VSS_297

VSS_144

AA12

F5

N13

AW20

AA14

VSS_11

G11

VSS_244

VSS_298

N16

VSS_145

AW21

VSS_12

VSS_245

VSS_299

VSS_146

AA26

VSS_13

G13

VSS_246

VSS_300

N20

VSS_147

AW37

AA35

VSS_14

G16

VSS_247

VSS_301

N25

VSS_148

AW47

AA38

VSS_15

G21

VSS_248

VSS_302

N29

VSS_149

AY11

AA41

G24

N32

AY24

AA44

VSS_16

G25

VSS_249

VSS_303

N39

VSS_150

AY42

AA7

VSS_17

G41

VSS_250

VSS_304

N42

VSS_151

AY46

AB21

VSS_18

G47

VSS_251

U7-5

VSS_305

N47

VSS_152

AY7

VSS_19

VSS_252

VSS_306

VSS_153

AB24

VSS_20

G9

VSS_253

VSS_307

N7

VSS_154

B23

AB28

VSS_22

H17

VSS_255

EB88CTPM

VSS_309

P28

VSS_156

B34

AB26

VSS_21

H1

VSS_254

VSS_308

P1

VSS_155

B26

AB33

VSS_23

H28

VSS_256

5 OF 5

VSS_310

P3

VSS_157

B36

AB47

VSS_24

H29

VSS_257

VSS_311

P33

VSS_158

B39

AC15

VSS_25

H33

VSS_258

VSS_312

P36

VSS_159

B41

C

AC2

H37

P46

B8

VSS_26

VSS_259

0904-002376

VSS_313

VSS_160

AC25

VSS_27

H40

VSS_260

VSS_314

R17

VSS_161

B9

AD12

H46

R21

BA13

AD2

VSS_28

H5

VSS_261

VSS_315

R24

VSS_162

BA16

AD38

VSS_29

J12

VSS_262

VSS_316

R3

VSS_163

BA2

AD41

VSS_30

J21

VSS_263

VSS_317

R46

VSS_164

BA20

VSS_31

VSS_264

VSS_318

VSS_165

AD44

VSS_32

J24

VSS_265

VSS_319

T29

VSS_166

BA28

AD47

VSS_33

J25

VSS_266

VSS

VSS

VSS_320

T35

VSS_167

BA33

AD5

VSS_34

J36

VSS_267

VSS_321

T38

VSS_168

BA38

AD9

VSS

J38

T41

VSS

BA46

AE13

VSS_36

J5

VSS_269

VSS_323

T47

VSS_170

BB11

AE10

VSS_35

J43

VSS_268

VSS_322

T44

VSS_169

BA5

AE2

VSS_37

J7

VSS_270

VSS_324

U24

VSS_171

BB25

VSS_38

VSS_271

VSS_325

VSS_172

AE28

VSS_39

K16

VSS_272

VSS_326

U25

VSS_173

BB37

AE34

VSS_40

K2

VSS_273

VSS_327

U28

VSS_174

BB40

AE36

VSS_41

K20

VSS_274

VSS_328

U29

VSS_175

BB47

AE39

K24

U35

BB8

AE42

VSS_42

K28

VSS_275

VSS_329

U38

VSS_176

BC13

VSS_43

VSS_276

VSS_330

VSS_177

AE7

K29

U41

BC17

AF2

VSS_44

K32

VSS_277

VSS_331

U44

VSS_178

BC20

VSS_45

VSS_278

VSS_332

VSS_179

AF21

VSS_46

L12

VSS_279

VSS_333

V46

VSS_180

BC3

AF24

L13

W15

BC33

VSS_47

VSS_280

VSS_334

VSS_181

AF26

VSS_48

L24

VSS_281

VSS_335

W34

VSS_182

BC38

AF34

L25

Y11

BC43

AF47

VSS_49

L33

VSS_282

VSS_336

Y2

VSS_183

BC9

AG20

VSS_50

L36

VSS_283

VSS_337

Y20

VSS_184

BD11

AG23

VSS_51

L39

VSS_284

VSS_338

Y23

VSS_185

BD25

VSS_52

VSS_285

VSS_339

VSS_186

AG28

VSS_53

L42

VSS_286

VSS_340

Y25

VSS_187

BD28

B

AH11

VSS_54

L47

VSS_287

VSS_341

Y28

VSS_188

BD36

AH2

L5

Y35

BD41

AH21

VSS_55

L8

VSS_288

VSS_342

Y38

VSS_189

BD46

AH24

VSS_56

M10

VSS_289

VSS_343

Y41

VSS_190

BD6

AH26

VSS_57

M17

VSS_290

VSS_344

Y44

VSS_191

BE4

AH33

VSS_58

M2

VSS_291

VSS_345

Y47

VSS_192

BF12

VSS_59

VSS_292

VSS_346

VSS_193

AH35

VSS_60

M21

VSS_293

VSS_347

Y5

VSS_194

BF24

AH38

M41

Y8

BF26

VSS_61

VSS_294

VSS_348

VSS_195

AH41

VSS_62

TV & LVDS

VSS_196

BF34

AH44

BF37

AH5

VSS_63

VSS

VSS SCB

VSS NCTF

VSS

VSS_197

BF44

AH8

VSS_64

VSS_198

BF9

AJ10

VSS_65

DACVSSABG

VSS_199

BG10

VSS_66

NCTFVSS1 NCTFVSS2 NCTFVSS3 NCTFVSS4 NCTFVSS5 NCTFVSS6 NCTFVSS7 NCTFVSS8 NCTFVSS9 NCTFVSS10 NCTFVSS11 NCTFVSS12 NCTFVSS13 NCTFVSS14 NCTFVSS15 NCTFVSS16

VSS_200

AJ13

VSS_67

LVDSVSSA

SCBVSS1 SCBVSS2 SCBVSS3 SCBVSS4 SCBVSS5

349VSS 206VSS 207VSS 208VSS 209VSS 210VSS 211VSS 212VSS 213VSS 214VSS 215VSS 216VSS 217VSS 218VSS 219VSS 220VSS 221VSS 222VSS 223VSS 224VSS 225VSS 226VSS 227VSS 228VSS 229VSS 230VSS 231VSS 232VSS 233VSS 234VSS 235VSS 236VSS 237VSS 238VSS 239VSS 240VSS

VSS_201

BG13

AJ2

VSS_68

VSS_202

BG14

AJ20

VSS_69

VSS_203

BG15

AJ24

BG17

VSS_70

VSS_204

BG19

VSS_205

B25

J47

A3 A48 BH1 BH48 C1

AA17 AB29 AB32 AC19 AF29 AF32 AJ17 AJ30 AL17 AL20 AM29 U17 U23 U26 V20 V32

AJ6 BG21 BG28 BG33 BG36 BG40 BG42 BG6 BH23 BH25 BH38 BH8 C11 C14 C17 C20 C26 C28 C32 C37 C38 C43 C6 E13 E16 E24 E25 E40 E8 F20 F24 F28 F29 F3 F32 F36

A

DRAW

DATE

TITLE

Jun PARK

9/23/2008

Bremen-L3

CHECK

DEV. STEP

YM.AHN

PV

MCH_CANTIGA_GM_DDR2

APPROVAL

REV

CANTIGA (5/5)

HJ.KIM

1.0

MODULE CODE

LAST EDIT

October 27, 2009 14:27:43 PM

4

3

2

1

D

C

B

A

SAMSUNG

ELECTRONICS

PART NO.

BA41-xxxxxA

PAGE 16 OF 59

D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN

R530/R730

8-16

- - - This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic

4			3	2	1
	SAMSUNG PROPRIETARY	DDR2 SO-DIMM #0
	THIS DOCUMENT CONTAINS CONFIDENTIAL
	PROPRIETARY INFORMATION THAT IS
	SAMSUNG ELECTRONICS CO’S PROPERTY.	Height : 4mm (Standard)
	DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
	EXCEPT AS AUTHORIZED BY SAMSUNG.

D	MEM1_ADQ(63:0)																															D
			14-D3
																								P0.9V
					DDR2M2-1												MEM1_AMA(14:0)		14-C4,17-D4		R858		56
					DDR2-SODIMM-200P-STD															0
					1/2															1	R832		56
	MEM1_AMA(14:0)		14-C4,17-D2																	2	R857		56
			0	102	A0	DQ0	5	0												3	R831		56
			1	101			7	1				P1.8V_AUX								4	R856		56
			2	100	A1	DQ1	17	2												5	R830		56
			3	99	A2	DQ2	19	3												6	R855		56
					A3	DQ3
			4	98	A4	DQ4	4	4						DDR2M2-2						7	R854		56
			5	97			6	5												8	R829		56
					A5	DQ5
			6	94	A6	DQ6	14	6						DDR2-SODIMM-200P-STD						9	R827		56
			7	92	A7	DQ7	16	7						2/2						10	R833		56
			8	93			23	8												11	R853		56
			9	91	A8	DQ8	25	9					112	VDD1	VSS16	18				12	R828		56
			10	105	A9	DQ9	35	10					111			24				13	R863		56
					A10_AP	DQ10								VDD2	VSS17
			11	90	A11	DQ11	37	11					117	VDD3	VSS18	41				14	R852		56
			12	89			20	12					96			53
					A12	DQ12				P3.3V				VDD4	VSS19						R861
			13	116			22	13					95			42	MEM1_CS0#		14-B4,17-C4				56
			14	86	A13	DQ13	36	14					118	VDD5	VSS20	54			14-B4,17-C4		R838		56
				84	A14	DQ14	38	15					81	VDD6	VSS21	59	MEM1_CS1#
					A15	DQ15								VDD7	VSS22						R825
	MEM1_ABS(2)		14-D4,17-C2	85			43	16					82			65	MEM1_CKE0		14-B4,17-C4				56
C					A16_BA2	DQ16	45	17		C997	C996		87	VDD8	VSS23	60			14-B4,17-C4		R851		56									C
						DQ17								VDD9	VSS24		MEM1_CKE1
	MEM1_ABS(0)		14-D4,17-C2	107			55	18		100nF	2200nF-X5R		103			66
					BA0	DQ18								VDD10	VSS25						R862
			14-D4,17-C2	106			57	19		10V	10V		88			127	MEM1_ODT0		14-B4,17-B4				56
	MEM1_ABS(1)				BA1	DQ19	44	20					104	VDD11	VSS26	139			14-B4,17-B4		R837		56
						DQ20								VDD12	VSS27		MEM1_ODT1
	MEM1_CS0#		14-B4,17-C2	110			46	21								128
					S0*	DQ21							199		VSS28		MEM1_ABS(0)				R834
	MEM1_CS1#		14-B4,17-C2	115	S1*	DQ22	56	22						VDDSPD	VSS29	145			14-D4,17-C4				56
						DQ23	58	23							VSS30	165	MEM1_ABS(1)		14-D4,17-C4		R859		56
	CLK1_MCLK0		14-B4	30			61	24					83			171			14-D4,17-C4		R826		56
					CK0	DQ24								NC1	VSS31		MEM1_ABS(2)
	CLK1_MCLK0#		14-B4	32	CK0*	DQ25	63	25					120	NC2	VSS32	172					R836
			14-B4	164			73	26					50			177	MEM1_ACAS#		14-B4,17-C4				56
	CLK1_MCLK1		14-B4	166	CK1	DQ26	75	27					69	NC3	VSS33	187			14-B4,17-B4		R860		56
	CLK1_MCLK1#		14-B4,17-C2	79	CK1*	DQ27	62	28					163	NC4	VSS34	178	MEM1_ARAS#		14-B4,17-B4		R835		56
	MEM1_CKE0		14-B4,17-C2	80	CKE0	DQ28	64	29						NCTEST	VSS35	190	MEM1_AWE#
	MEM1_CKE1				CKE1	DQ29			MEM1_VREF				1		VSS36
	MEM1_ACAS#					DQ30	74	30		14-D1,18-C3 51-B1				VREF	VSS37	9
			14-B4,17-C2	113	CAS*	DQ31	76	31		C978		C962	201		VSS38	21
	MEM1_ARAS#		14-B4,17-C2	108	RAS*	DQ32	123	32						GND0	VSS39	33
			14-B4,17-C2	109			125	33		100nF		2200nF-X5R	202			155
	MEM1_AWE#				WE*	DQ33								GND1	VSS40
							135	34		10V		10V				34
	R846					DQ34									VSS41
DDR2M_SA00_MN		10K	1%	198			137	35				nostuff	47			132
					SA0	DQ35								VSS1	VSS42
DDR2M_SA01_MN	R847	10K	1%	200	SA1	DQ36	124	36					133	VSS2	VSS43	144
	SMB3_CLK		11-B4,18-B4 31-B4 197		SCL	DQ37	126	37					183	VSS3	VSS44	156
	SMB3_DATA		11-B4,18-B4 31-B4 195		SDA	DQ38	134	38					77	VSS4	VSS45	168
						DQ39	136	39					12	VSS5	VSS46	2
	MEM1_ODT0		14-B4,17-C2	114			141	40					48			3
					ODT0	DQ40								VSS6	VSS47
	MEM1_ODT1		14-B4,17-C2 119		ODT1	DQ41	143	41					184	VSS7	VSS48	15
			14-D4				151	42					78			27
	MEM1_ADM(7:0)		0	10		DQ42	153	43					71	VSS8	VSS49	39		Place one cap close to every 2 pull-up resistors terminated to P0.9V
					DM0	DQ43								VSS9	VSS50
			1	26	DM1	DQ44	140	44					72	VSS10	VSS51	149	P0.9V
B			2	52			142	45					121			161																B
			3	67	DM2	DQ45	152	46					122	VSS11	VSS52	28
			4	130	DM3	DQ46	154	47					196	VSS12	VSS53	40
			5	147	DM4	DQ47	157	48					193	VSS13	VSS54	138
			6	170	DM5	DQ48	159	49					8	VSS14	VSS55	150
			7	185	DM6	DQ49	173	50						VSS15	VSS56	162	C1009	C981	C979	C964		C1005	C1010	C1004	C1006		C1008	C1007	C1000		C974	C980
					DM7	DQ50									VSS57
	MEM1_ADQS(7:0)		14-C4	13		DQ51	175	51									100nF	100nF	100nF	100nF		100nF	100nF	100nF	100nF		100nF	100nF	100nF		100nF	100nF
			0		DQS0	DQ52	158	52						3709-001573|sodimm-200p-s-4-1			10V	10V	10V	10V		10V	10V	10V	10V		10V	10V	10V		10V	10V
			1	31	DQS1	DQ53	160	53
			2	51			174	54
			3	70	DQS2	DQ54	176	55																nostuff		nostuff nostuff nostuff				nostuff nostuff
			4	131	DQS3	DQ55	179	56
			5	148	DQS4	DQ56	181	57
					DQS5	DQ57
			6	169	DQS6	DQ58	189	58										ME POWER RAIL UNDER ME ENABLE
			7	188	DQS7	DQ59	191	59
	MEM1_ADQS#(7:0)		14-D4	11		DQ60	180	60
			0				182	61
			1	29	DQS*0	DQ61	192	62									P1.8V_AUX		Place near SO-DIMM0
			2	49	DQS*1	DQ62	194	63
			3	68	DQS*2	DQ63
					DQS*3
			4	129	DQS*4												EC508
			5	146	DQS*5													C993	C1013		C991		C992	C1011	C994		C1012	C990	C995
			6	167	DQS*6												220uF
			7	186	DQS*7												2.5V	2200nF-X5R 2200nF-X5R			2200nF-X5R		2200nF-X5R	2200nF-X5R 100nF			100nF	100nF	100nF
																	AD	10V	10V		10V		10V	10V	10V		10V	10V	10V
					3709-001573|sodimm-200p-s-4-1
																	nostuff
A																																A
																	DRAW			DATE		TITLE		Bremen-L3				SAMSUNG
																		Jun PARK			9/23/2008
																	CHECK			DEV. STEP											ELECTRONICS
																			YM.AHN			PV		SODIMM_DDR2
																	APPROVAL			REV				SODIMM_DDR2 #1				PART NO.
																			HJ.KIM			1.0									BA41-xxxxxA
																	MODULE CODE			LAST EDIT									17			59
																							October 27, 2009 14:27:43 PM					PAGE			OF
		4							3								2										1
																											D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAIN

8-17

R530/R730

- - - This Document can not be used without Samsung's authorization -

8. Block Diagram and Schematic

	4								3								2									1
SAMSUNG PROPRIETARY				DDR2 SO-DIMM #1
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS				Height : 4mm (Reverse)
EXCEPT AS AUTHORIZED BY SAMSUNG.
D	MEM1_BDQ(63:0)		14-A1																						P0.9V									D
																		MEM1_BMA(14:0)			14-B1,18-D4	R799		56
																					0
																					1	R779		56
					DDR2M1-1																2	R798		56
												P1.8V_AUX									3	R778		56
					DDR2-SODIMM-200P-RVS																4	R797		56
					1/2									DDR2M1-2							5	R777		56
MEM1_BMA(14:0)		14-B1,18-D1		102		DQ0	5														6	R795		56
			0		A0			0						DDR2-SODIMM-200P-RVS							7	R796		56
			1	101	A1	DQ1	7	1						2/2							8	R776		56
			2	100			17	2													9	R775		56
			3	99	A2	DQ2	19	3					112			18					10	R781		56
					A3	DQ3								VDD1	VSS16
			4	98	A4	DQ4	4	4					111	VDD2	VSS17	24					11	R793		56
			5	97	A5	DQ5	6	5					117	VDD3	VSS18	41					12	R774		56
			6	94	A6	DQ6	14	6					96	VDD4	VSS19	53					13	R803		56
			7	92			16	7	P3.3V				95			42					14	R794		56
			8	93	A7	DQ7	23	8					118	VDD5	VSS20	54
			9	91	A8	DQ8	25	9					81	VDD6	VSS21	59		MEM1_CS2#			14-D1,18-C4	R802		56
					A9	DQ9								VDD7	VSS22
			10	105	A10_AP	DQ10	35	10					82	VDD8	VSS23	65		MEM1_CS3#			14-D1,18-C4	R784		56
			11	90	A11	DQ11	37	11		C942	C941		87	VDD9	VSS24	60						R773
			12	89			20	12					103			66		MEM1_CKE2			14-C1,18-C4			56
					A12	DQ12								VDD10	VSS25
			13	116	A13	DQ13	22	13		100nF	2200nF-X5R		88	VDD11	VSS26	127		MEM1_CKE3			14-C1,18-C4	R772		56
			14	86			36	14		10V	10V		104			139
					A14	DQ14								VDD12	VSS27							R804
				84			38	15								128		MEM1_ODT2			14-D1,18-B4			56
	MEM1_BBS(2)		14-B1,18-C1	85	A15	DQ15	43	16					199	VDDSPD	VSS28	145					14-C1,18-B4	R785		56
C					A16_BA2	DQ16	45	17							VSS29	165		MEM1_ODT3																C
			14-B1,18-C1	107		DQ17							83		VSS30						14-B1,18-C4	R780		56
	MEM1_BBS(0)				BA0	DQ18	55	18						NC1	VSS31	171		MEM1_BBS(0)
			14-B1,18-C1	106			57	19					120			172					14-B1,18-C4	R800		56
	MEM1_BBS(1)				BA1	DQ19	44	20					50	NC2	VSS32	177		MEM1_BBS(1)			14-B1,18-C4	R792		56
	MEM1_CS2#		14-D1,18-C1	110		DQ20	46	21					69	NC3	VSS33	187		MEM1_BBS(2)
					S0*	DQ21								NC4	VSS34							R783
			14-D1,18-C1	115			56	22					163			178		MEM1_BCAS#			14-D1,18-C4			56
	MEM1_CS3#				S1*	DQ22								NCTEST	VSS35
						DQ23	58	23							VSS36	190		MEM1_BRAS#			14-D1,18-B4	R801		56
	CLK1_MCLK2		14-C1	30			61	24	MEM1_VREF	14-D1,17-C3 51-B1			1			9					14-D1,18-B4	R782		56
					CK0	DQ24								VREF	VSS37			MEM1_BWE#
	CLK1_MCLK2#		14-C1	32	CK0*	DQ25	63	25			C933	C944			VSS38	21
			14-C1	164			73	26					201	GND0		33
	CLK1_MCLK3		14-C1	166	CK1	DQ26	75	27			100nF	2200nF-X5R	202		VSS39	155
	CLK1_MCLK3#				CK1*	DQ27								GND1	VSS40
			14-C1,18-C1	79			62	28			10V	10V				34
	MEM1_CKE2		14-C1,18-C1	80	CKE0	DQ28	64	29				nostuff	47	VSS1	VSS41	132
	MEM1_CKE3				CKE1	DQ29	74	30					133		VSS42	144
P3.3V	MEM1_BCAS#		14-D1,18-C1 113		CAS*	DQ30	76	31					183	VSS2	VSS43	156
			14-D1,18-C1	108		DQ31	123	32					77	VSS3	VSS44	168
	MEM1_BRAS#		14-D1,18-C1	109	RAS*	DQ32	125	33					12	VSS4	VSS45	2
	MEM1_BWE#				WE*	DQ33	135	34					48	VSS5	VSS46	3
DDR2M_SA10_MN	R807	10K	1%	198	SA0	DQ34	137	35					184	VSS6	VSS47	15
	R808	10K	1%	200		DQ35	124	36					78	VSS7	VSS48	27
DDR2M_SA11_MN					SA1	DQ36								VSS8	VSS49
	SMB3_CLK	11-B4,17-B4 31-B4 197			SCL	DQ37	126	37					71	VSS9	VSS50	39
	SMB3_DATA	11-B4,17-B4 31-B4 195			SDA	DQ38	134	38					72	VSS10	VSS51	149
						DQ39	136	39					121	VSS11	VSS52	161
	MEM1_ODT2		14-D1,18-C1	114			141	40					122			28
					ODT0	DQ40								VSS12	VSS53				Place one cap close to every 2 pull-up resistors terminated to P0.9V
	MEM1_ODT3		14-C1,18-C1 119		ODT1	DQ41	143	41					196	VSS13	VSS54	40	P0.9V
			14-C1				151	42					193			138
	MEM1_BDM(7:0)		0	10		DQ42	153	43					8	VSS14	VSS55	150
					DM0	DQ43								VSS15	VSS56
			1	26			140	44								162
					DM1	DQ44									VSS57
B			2	52	DM2	DQ45	142	45									C971	C937	C939	C935	C973	C965	C963	C934		C938		C972		C940		C966	C936	B
			3	67			152	46						3709-001572|sodimm-200p-r-1-1
			4	130	DM3	DQ46	154	47									100nF	100nF	100nF	100nF	100nF	100nF	100nF	100nF		100nF		100nF		100nF		100nF	100nF
					DM4	DQ47
			5	147			157	48									10V	10V	10V	10V	10V	10V	10V	10V		10V		10V		10V		10V	10V
			6	170	DM5	DQ48	159	49															nostuff		nostuff		nostuff		nostuff		nostuff nostuff
			7	185	DM6	DQ49	173	50
	MEM1_BDQS(7:0)		14-C1		DM7	DQ50	175	51
				13		DQ51
			0		DQS0	DQ52	158	52
			1	31			160	53
					DQS1	DQ53
			2	51			174	54
			3	70	DQS2	DQ54	176	55
					DQS3	DQ55
			4	131			179	56
			5	148	DQS4	DQ56	181	57
					DQS5	DQ57											P1.8V_AUX		Place near SO-DIMM1
			6	169	DQS6	DQ58	189	58
			7	188	DQS7	DQ59	191	59
MEM1_BDQS#(7:0)			14-C1	11		DQ60	180	60
			0		DQS*0		182	61
			1	29		DQ61	192	62									EC507
					DQS*1	DQ62												C969	C920	C923		C921	C968		C970	C967		C922		C919
			2	49	DQS*2	DQ63	194	63									220uF
			3	68	DQS*3												2.5V	2200nF-X5R 2200nF-X5R 2200nF-X5R				2200nF-X5R	2200nF-X5R		100nF	100nF		100nF		100nF
			4	129													AD	10V	10V	10V		10V	10V		10V	10V		10V		10V
			5	146	DQS*4												nostuff
			6	167	DQS*5
			7	186	DQS*6
					DQS*7
					3709-001572|sodimm-200p-r-1-1
A																																		A
																	DRAW		DATE			TITLE		Bremen-L3						SAMSUNG
																			Jun PARK		9/23/2008
																	CHECK		DEV. STEP													ELECTRONICS
																			YM.AHN		PV		SODIMM_DDR2
																	APPROVAL		REV				SODIMM_DDR2 #2						PART NO.
																			HJ.KIM		1.0											BA41-xxxxxA
																	MODULE CODE		LAST EDIT											18			59
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R530/R730

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