SaRonix STA, STT Technical data

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SaRonix
Technical Data
ACTUAL SIZE
Description
A crystal controlled, low current, low jitter and high frequency oscillator with precise rise and fall times demanded in high performance networking, telecom and processor applications. The tri-state function enables the output to go high impedance. Available in a 14 or an 8 pin DIP compatible, resistance welded, all metal case. Pin 7 (or Pin 4) is grounded to case to reduce EMI. See photo above for new, full size metal package with a true SMD adapter. For this package option select option S in part number builder.
Applications & Features
Fibre Channel
• Gigabit Ethernet
• High performance Processors
• True SMD DIL14 version available
• High Drive HCMOS, ACMOS or TTL
• capability Tri-State output
• Precise Rise/Fall Times
• Reduced EMI circuitry
• Short circuit protected output
Crystal Clock Oscillator
3.3 & 5V, HCMOS, ACMOS, TTL
STA / STT Series
Frequency Range:
Frequency Stability: ±20, ±25, ±50 or ±100 ppm over all conditions: calibration
* 1 year @ +40°C
Temperature Range:
Supply Voltage:
Recommended Operating: +5V ±10% or 3.3V ±10% (STA only)
Supply Current: 50mA typ, 70mA max @ 5V or 30mA typ, 45mA max @ 3.3V
Output Drive:
ACMOS / TTL
Rise & Fall Times:
Period Jitter RMS:
Mechanical:
Terminal Strength:
Solvent Resistance:
Resistance to Soldering Heat:
Environmental:
Moisture Resistance:
Full Size:
Operating:
Storage:
Symmetry:
Logic 0: Logic 1:
Load:
Shock:
Solderability:
Vibration:
Gross Leak Test:
Fine Leak Test:
Thermal Shock:
Part Numbering Guide
Series
STA = ACMOS compatible, 3.3 or 5V STT = TTL compatible, 5V only
Symmetry
0 = 40/60% max, 0 to +70°C
A = 45/55% max, 0 to +70°C STT to 80 MHz max only STA 3.3V to 109.9999 MHz max only 2 = 40/60% max, -40 to +85°C STA 3.3V to 109.9999 MHz max only
Standard* Rise/Fall Times
1 = STT 4.0ns max 250kHz to 15 MHz full, to 35 MHz ½ size 2 = STT 2.0ns max from 15+ MHz full, 35+ MHz ½ size to 60 MHz 3 = STT 1.0ns max from 60+ MHz to 135 MHz 7 = STA 5.5ns max, 125kHz to 15 MHz full, 500kHz to 35 MHz ½ size 8 = STA 3.5ns max from 15+ MHz full, 35+ MHz ½ size to 60 MHz 9 = STA 2ns max from 60+ MHz to 135 MHz(5V), to 125 MHz(3.3V)
*
R/F times are standard with given frequency ranges, non-standard R/F times available on some models, please contact SaRonix
Example PN: STT220C - 60.0000
STT 5V STA 5V STA 3.3V 250kHz - 135MHz 125kHz - 135MHz 125kHz - 125MHz 250kHz - 135MHz 500kHz - 135MHz 500kHz - 125MHz
tolerance, operating temperature, rated input voltage change, load change, aging*, shock and vibration
0 to +70°C or -40 to +85°C
-55 to +125°C
See Part Numbering Guide See Part Numbering Guide 10% VDD or 0.5V max 90% VDD or 2.5Vmin 50 ACMOS, 95 ACMOS @ 3.3V, 50mA sink & source @ TTL 8ps max
MIL-STD-883, Method 2002, Condition B MIL-STD-883, Method 2003 MIL-STD-202, Method 211, Conditions B2 MIL-STD-883, Method 2007, Condition A MIL-STD-202, Method 215 MIL-STD-202, Method 210, Condition A, B or C
MIL-STD-883, Method 1014, Condition C MIL-STD-883, Method 1014, Condition A2 MIL-STD-883, Method 1011, Conditions A MIL-STD-883, Method 1004
STA A 9 9 B 3 - 90.0000
Frequency (MHz)
Supply
blank = 5V (STA or STT, 135MHz max) 3 = 3.3V (STA only, 125MHz max)
Stability Tolerance
AA = ±20ppm, 80MHz max, 0 to +70°C only A = ±25ppm, 80MHz max, 0 to +70°C only B = ±50ppm C = ±100ppm
Package Size / Style
0 = Full Size 9 = ½ Size K = Full Size, Gull Wing J = ½ Size, Gull Wing N = ½ Size, Gull Wing, Spanked Leads S = Full Size, True SMD Adapter
DS-108 REV K
SaRonix
141 Jefferson Drive • Menlo Park, CA 94025 • USA • 650-470-7700 • 800-227-8974 • Fax 650-462-9894
SaRonix
Technical Data
Package Details
FULL SIZE PACKAGE
21.0
0.9
.036
max
Pin 1
Tri-State
Control
Pin 14
+5 or +3.3 VDC
Includes Date Code, Frequency & Part Number
SARONIX XTAL OSC
max
.825
.46±.08 .018±.003
15.24±.13 .600±.005
(4) Glass Insulators
Marking Format
**
6.35±.51
.250±.020
Pin 8 Output
7.75 .305
5.08 .200
Pin 7
GND
13.0 .510 max
max
max
Crystal Clock Oscillator
3.3 & 5V, HCMOS, ACMOS, TTL
Output Waveform Tri-State Logic Table
ACMOS
Tr Tf Tr Tf
LOGIC 1
80% VDD
50% VDD
20% VDD
LOGIC 0
TTL
VDD
Pin 1 Input
Logic 1 or NC
2.5 VDC
1.5 VDC
0.5 VDC
GND
SYMMETRYSYMMETRY
Logic 0 or GND
Required Input Levels on Pin 1: Logic 1 = 2.2V min Logic 0 = 0.8V max
Test Circuit
POWER SUPPLY
mA
M
V M
.01 µF
Pin 1 ( 1 )
POINT
VCC
OSCILLATOR
*
TEST
OUT
GND
ACMOS
50Ω Load
Pin 8 (5)Pin 14 (8)
Pin 7 (4)
STA / STT Series
Output
Standard Logic
Oscillation
High Impedance
56
0.01 µF
Denotes Pin 1
HALF SIZE PACKAGE
13.0 max
0.9
.036
.46±.08
.018±.003
Pin 1
Tri-State
1.5 .059
13.0 .510 max
Pin 14
+5 or +3.3 VDC
Includes Date Code, Frequency & Part Number
.510
max
7.62±.20
.300±.008
120° 120°
Glass Insulators
Marking Format
120°
5.08 .200
6.35±.51
.250±.020
7.62±.20 .300±.008
**
SARONIX
Denotes Pin 1
max
Pin 4
GND
Pin 5
Output
POWER SUPPLY
mA
M
TRI-STATE INPUT
(current limited on fixture)
*
( ) Indicates pin numbers for half-size package
ΩΩ
ACMOS TEST CIRCUIT (5V operation)
50
ΩΩ
TEST
POINT
Pin 14 (8)
V
CC
OUT
V M
.01 µF
Pin 1 ( 1 )
OSCILLATOR
GND
*
TRI-STATE INPUT
(current limited on fixture)
*
( ) Indicates pin numbers for half-size package
ΩΩ
95
ACMOS TEST CIRCUIT (3.3V operation)
ΩΩ
ACMOS
95
Pin 8 (5)
Pin 7 (4)
Load
95
0.01 µF
**
Exact location of items may vary
Scale: None (Dimensions in )
SaRonix
mm
inches
DS-108 REV K
141 Jefferson Drive • Menlo Park, CA 94025 • USA • 650-470-7700 • 800-227-8974 • Fax 650-462-9894
All specifications are subject to change without notice.
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