SANYO VPC-C6EXE, VPC-C6EXBK, VPC-C6EXR, VPC-C6EX, VPC-C6E CIRCUIT DESCRIPTION

1. OUTLINE OF CIRCUIT DESCRIPTION

1-1. CCD CIRCUIT DESCRIPTION

1. IC Configuration

The CCD peripheral circuit block basically consists of the fol­lowing ICs.
IC903 (MN39830PLJ-A) CCD imager
IC901 (AN20112A) V driver
IC905 (AD9996BBCZ) CDS, AGC, A/D converter,

H driver, vertical TG

Pin 1

5

V

6

12

Pin 13

H

58

2. IC903 (CCD)

[Structure]

Interline type CCD image sensor

Optical size 1/2.5 type format
Effective pixels 2864 (H) X 2160 (V)
Pixels in total 2934 (H) X 2171 (V)
Optical black

Horizontal (H) direction: Front 12 pixels, Rear 58 pixels
Vertical (V) direction: Front 6 pixels, Rear 5 pixels

Dummy bit number Horizontal : 28 Vertical :7

Pin No.

Symbol Pin Description

Fig. 1-1.Optical Black Location (Top View)

Photo diode

10

VDD

VO

GND

13
14

15

Vertical shift register

Output part

Horizontal shift register

16

RG

ø

20

21

22

H2

H1

HL

ø

ø

ø

11
12
23
24
17
18
19

Fig. 1-2. CCD Block Diagram

Waveform

Voltag e

ø

1

ø

2

ø

3

ø

4

ø

5

ø

6

ø

7

ø

8
9

ø
ø
ø

GND

ø

ø

PT

SUBSW

ø

V6
V5B
V5A
V4
V3B
V3A
V3L
V3R

V2
V1
V1S

V5R
V5L

Vsub

1, 23, 24

2, 3

4, 7, 8, 9, 11

5, 6, 10

14

13

16

12, 15

17

18

19

20, 21

22

5L, V5R, V6

V

5A, V5B Vertical register transfer clock

V

V1S, V2, V3L,

V3R, V4

V

1, V3A, V3B

VO

VDD

ØRG

GND

PT

Vertical register transfer clock

Vertical register transfer clock

Vertical register transfer clock

Signal output

Circuit power DC 12 V

Reset gate clock

GND
Protection transister bias

Substrate controlSUB SW

SUB

L, H1

H

H

Substrate clock

Horizontal register transfer clock

Horizontal register transfer clock

2

Table 1-1. CCD Pin Description

-6.0 V, 0 V

-6.0 V, 0 V, 12 V

-6.0 V, 0 V

-6.0 V, 0 V, 12 V

DC

Aprox. 12 V

4.5 V, 7.8 V

GND 0 V

DC

-6.0 V

0, 3.3 V (When importing all
picture element: 3.3 V)

DC

Aprox. 6 V
(Different from every CCD)

0 V, 3.3 V

0 V, 3.3 V

When sensor read-out

– 2 –

3. Part of IC905 (generation of vertical transfer clock,
H Driver) and IC901 (V Driver)

An H driver (part of IC905) and V driver (IC901) are neces­sary in order to generate the clocks (vertical transfer clock,
horizontal transfer clock and electronic shutter clock) which
driver the CCD.
IC905 has the generation of horizontal transfer clock and the
function of H driver, and is an inverter IC which drives the
horizontal CCDs (H1 and H2). It carries out generating verti­cal transfer clock, and output to IC901.
In addition the XV1-XV6 signals which are output from IC905
are vertical transfer clocks, and the XSG signal is superim­posed onto XV1, XV3 and XV5 at IC901 in order to generate
a ternary pulse. In addition, the XSUB signal which is output
from IC101 is used as the sweep pulse for the electronic shut­ter, and the RG signal which is output from IC905 is the reset
gate clock.

4. IC905 (H Driver, CDS, AGC and A/D converter)

IC905 contains the functions of H driver, CDS, AGC and A/D
converter. As horizontal clock driver for CCD image sensor,
HØ1 (A and B) and HØ2 (A and B) are generated inside, and
output to CCD.
The video signal which is output from the CCD is input to pin
(A6) of IC905. There are sampling hold blocks generated from
the SHP and SHD pulses, and it is here that CDS (correlated
double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier (VGA: Variable Gain Amplifier). It
is A/D converted internally into a 14-bit signal, and is then
input to ASIC (IC101). The gain of the VGA amplifier is con­trolled by pin (A2), (B3) and (C4) serial signal which is output
from ASIC (IC101).

REFB

REFT

OSUB

VM

OV1

RESET

SUBCNT

VDC

CH1

V5R

V5L

V3R

V3L

V1S

CLI

AD9996

14-BIT

ADC

CLAMP

INTERNAL

REGISTERS

CLO

14

DOUT

SL

SCK

SDI

VMSUB

9

3-level

10

VL

5

VL

27

2-level

24OV2

2-level

23OV4

2-level

21OV6

8

3-level

20

28

Level

1

conversion

3

Level

32

conversion

Level

V1

33

conversion

Level

31

V6

conversion

Level

V4

30

conversion

Level

29

V2

conversion

Level

37

conversion

Level

38

conversion

Level

35

conversion

Level

36

conversion

Level

34

conversion

2-level

2-level

2-level

2-level

2-level

3-level

3-level

3-level

3-level

Level

conversion

Level

conversion

Level

conversion

Level

conversion

Level

conversion

Level

conversion

Level

conversion

7

VHH

16

OV5R

15

OV5L

18

OV3R

17

OV3L

19

OV1S

25

VM

12

OV5A

11

OV5B

14

OV3A

13

OV3B

6

VH

26

VH

4

GND

41

CH2

40

V3

39

CH4

44

CH3

43

V5

42

CH5

2

SUB

CCDIN

3V INPUT

1.8V OUTPUT

1.8V INPUT

3V OUTPUT

H1 TO H8

XV1 TO XV24

XSUBCK

RG

HL

CDS

-3dB, 0dB, +3dB

LDO
REG

CHARGE

PUMP

HORIZONTAL

DRIVERS

8

24

VERTICAL

TIMING

CONTROL

8

GP01 TO GP08

Fig. 1-4. IC905 Block Diagram

6~42 dB

VGA

INTERNAL

CLOCKS

PRECISION

TIMING

GENERATOR

SYNC

GENERATOR

VD

HD

VREF

SYNC

Fig. 1-3. IC901 Block Diagram

– 3 –

1-2. CP1 CIRCUIT DESCRIPTION

1. Circuit Description

1-1. Digital clamp

The optical black section of the CCD extracts averaged val­ues from the subsequent data to make the black level of the
CCD output data uniform for each line. The optical black sec­tion of the CCD averaged value for each line is taken as the
sum of the value for the previous line multiplied by the coeffi­cient k and the value for the current line multiplied by the
coefficient 1-k.

1-2. Signal processor

1. γ correction circuit

This circuit performs (gamma) correction in order to maintain
a linear relationship between the light input to the camera
and the light output from the picture screen.

2. Color generation circuit

This circuit converts the CCD data into RGB signals.

3. Matrix circuit

This circuit generates the Y signals, R-Y signals and B-Y sig­nals from the RGB signals.

4. Horizontal and vertical aperture circuit

This circuit is used gemerate the aperture signal.

1-3. AE/AWB and AF computing circuit

The AE/AWB carries out computation based on a 64-segment
screen, and the AF carries out computations based on a 6­segment screen.

1-4. SDRAM controller

This circuit outputs address, RAS, CAS and AS data for con­trolling the SDRAM. It also refreshes the SDRAM.

1-5. Communication control

1. SIO

This is the interface for the 8-bit microprocessor.

2. PIO/PWM/SIO for LCD

8-bit parallel input and output makes it possible to switch be­tween individual input/output and PWM input/output.

When the TG/SG drives the CCD, picture data passes through
the A/D and CDS, and is then input to the ASIC as 12-bit
data. The AF, AE, AWB, shutter, and AGC value are com­puted from this data, and three exposures are made to obtain
the optimum picture. The data which has already been stored
in the SDRAM is read by the CPU and color generation is
carried out. Each pixel is interpolated from the surrounding
data as being either Ye, Cy, Mg or B primary color data to
produce R, G and B data. At this time, correction of the lens
distortion which is a characteristic of wide-angle lenses is
carried out. After AWB and γ processing are carried out, a
matrix is generated and aperture correction is carried out for
the Y signal, and the data is then compressed by JPEG and
is then written to card memory (SD card).
When the data is to be output to an external device, it is taken
data from the memory and output via the USB I/F. When played
back on the LCD and monitor, data is transferred from memery
to the SDRAM, and the image is then elongated so that it is
displayed over the SDRAM display area.

3. LCD Block

The LCD display circuit is located on the CP1 board, and
consists of driver (IC171). The video signals (YCrCb) from
the ASIC are input as 8-bit digital signals together with the
synchronization control signals (LCDCLK, LCDVD and
LCDHD). They are converted to RGB inside the driver and
output to the LCD panel. Furthermore, the driver has a built­in DC/DC converter to generate the power supplies (8.5 V
and 5.5 V) that are necessary for the LCD.

4. Lens drive block

4-1. Iris drive

When the drive signals (IIN1 and IIN2) which are output from
the ASIC (IC101), iris motor is driven by the driver (IC956),
and are then used to drive the iris steps.

4-2. Focus drive

When the drive signals (FIN1, FIN2, FIN3 and FIN4) which are
output from the ASIC (IC101), the focus stepping motor is driven
by the driver (IC956). Detection of the standard focusing posi­tions is carried out by means of the photointerruptor (FOCUS
PI) inside the lens block.

1-6. TG/SG

Timing generated for 6 million pixel horizontal addtion CCD
control.

1-7. Digital encorder

It generates chroma signal from color difference signal.

2. Outline of Operation

When the shutter opens, the reset signals (ASIC and CPU)
and the serial signals (“take a picture” commands) from the
8-bit microprocessor are input and operation starts.

4-3. Zoom drive

When the drive signals (ZIN1, ZIN2, ZIN3 and ZIN4) which are
output from the ASIC (IC101), the zoom stepping motor is driven
by the driver (IC956). Detection of the standard zoom posi­tions is carried out by means of photointerruptor (ZOOM PI)
inside the lens block.

4-4. Shutter drive

When the drive signals (SIN1 and SIN2) which are output from
the ASIC (IC101), it is driven regular current by the driver
(IC956).

– 4 –

1-3. PWA POWER CIRCUIT DESCRIPTION

1. Outline

This is the main power circuit, and is comprised of the follow­ing blocks.
Switching controller (IC501)
Analog system power output (L5001, Q5001)

4.5 V power output (L5005, Q5008)

Digital 3.25 V power output (L5006)
Digital 1.2 V power output (L5007)
Backlight power output (L5008, Q5009)
Motor system power output (IC531, L5301, Q5301)

2. Switching Controller (IC501)

This is the basic circuit which is necessary for controlling the
power supply for a PWM-type switching regulator, and is pro­vided with seven built-in channels, only CH1 (digital system

1.2 V), CH2 (digital 3.25 V), CH4 (4.5 V system), CH5 (ana-

log system) and CH6 (backlight system) are used. Feedback
from digital system 1.2 V (D) (CH1), 3.25 V (D) (CH2), 4.5 V
system (CH4), analog system (CH5) and backlight system
(CH6) power supply outputs are received, and the PWM duty
is varied so that each one is maintained at the correct voltage
setting level.
Feedback for the backlight power (CH6) is provided to the
both ends voltage of registance so that regular current can
be controlled to be current that was setting.

2-1. Short-circuit protection circuit

If output is short-circuited for the length of time determined
by internal fixing of IC501 , all output is turned off. The control
signal (P ON) are recontrolled to restore output.

3. Analog System Power Output

+12 V (A), +3.45 V (A) and -6.0 V (A) are output. Feedback for
the +12 V (A) is provided to the switching controller (Pin (4) of
IC501) so that PWM control can be carried out.

4. Digital 3.25 V Power Output

VDD3 is output. Feedback for the VDD3 is provided to the
swiching controller (Pin (54) of IC501) so that PWM control
can be carried out.

5. Digital 1.2 V Power Output

VDD1.2 is output. Feedback for the VDD1.2 is provided to the
switching controller (Pin (52) of IC501) so that PWM control
to be carried out.

6. 4.5 V System Power Output

4.5 V is output. Feedback for the 4.5 V output is provided to
the switching controller (Pin (2) of IC501) so that PWM con­trol to be carried out.

7. Backlight Power Supply output

Regular current is being transmitted to LED for LCD back­light. Feedback for the both ends voltage of registance that is
being positioned to in series LED are provided to the switch­ing controller (Pin (6) of IC501) so that PWM control to be
carried out.

8. Motor System Power Output

4.8 V is output. Feedback for the 4.8 V output is sent to pin (1)
of IC531 for PWM control to be carried out.

9. Camera charging circuit

If the camera’s power is turned off, play mode and USB con­nection mode (card reader and pictbridge) setting while it is
connected to the AC adaptor, the battery will be recharged. In
the above condition, a CTL signal is sent from the micropro­cessor and recharging starts.

– 5 –

1-4. ST1 STROBE CIRCUIT DESCRIPTION

1. Charging Circuit

When UNREG power is supplied to the charge circuit and the
CHG signal from microprocessor becomes High (3.3 V), the
charging circuit starts operating and the main electorolytic
capacitor is charged with high-voltage direct current.
However, when the CHG signal is Low (0 V), the charging
circuit does not operate.

1-1. Charging switch

The CHG signal becomes High, Q5406 becomes ON and the
charging circuit starts operating.

1-2. Power supply filter

C5406 constitutes the power supply filter. They smooth out
ripples in the current which accompany the switching of the
oscillation transformer.

1-3. Oscillation circuit

This circuit generates an AC voltage (pulse) in order to in­crease the UNREG power supply voltage when drops in cur­rent occur. This circuit generates a drive pulse with a frequency
of approximately 50-100 kHz. Because self-excited light omis­sion is used, the oscillation frequency changes according to
the drive conditions.

2. Light Emission Circuit

When FLCLT signals are input from the ASIC expansion port,
the stroboscope emits light.

2-1. Emission control circuit

When the FLCLT signal is input to Hi at the emission control
circuit, Q5409 switches on and preparation is made to the
light emitting. Moreover, when a FLCLT signal becomes Lo,
the stroboscope stops emitting light.

2-2. Trigger circuit

The Q5409 is turned ON by the FLCLT signal and light emis­sion preparation is preformed. Simultaneously, high voltage
pulses of several kV are emitted from the trigger coil and ap­plied to the light emitter.

2-3. Light emitting element

When the high-voltage pulse form the trigger circuit is ap­plied to the light emitting part, currnet flows to the light emit­ting element and light is emitted.

Beware of electric shocks.

1-4. Oscillation transformer

The low-voltage alternating current which is generated by the
oscillation control circuit is converted to a high-voltage alter­nating current by the oscillation transformer.

1-5. Rectifier circuit

The high-voltage alternating current which is generated at
the secondary side of T5401 is rectified to produce a high­voltage direct current and is accumulated at electrolytic ca­pacitor C5412.

1-6. Voltage monitoring circuit

This circuit is used to maintain the voltage accumulated at
C5412 at a constance level.
After the charging voltage is divided and converted to a lower
voltage by R5405 and R5406, it is output as the monitoring
voltage VMONIT. When VMONIT voltage reaches a specified
level, the CHG signal is switched to Low and charging is in­terrupted.

– 6 –

1-5. SYA CIRCUIT DESCRIPTION

1. Configuration and Functions

For the overall configuration of the SYA block, refer to the block diagram. The SYA block centers around a 8-bit microprocessor
(IC301), and controls camera system condition (mode).
The 8-bit microprocessor handles the following functions.

1. Operation key input, 2. Clock control and backup, 3. Power ON/OFF, 4. Storobe charge control.

Pin

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42 COMREQ/ZBOOT I

Signal

SCK

BACKUP_CTL

BAT_CHG ON

DC IN

LCD PWM

TSEN_CLK

BR MOTOR +

BR MOTOR –

VDD2

VSS2

CHG_LED

SELF_LED

TH ON

BR PI ON

AV JACK

HOT LINE

SCAN IN0

CHGERR

USB CONNECT

SCAN IN1

SCAN IN2

SCAN IN3

NOT USED

BR DET SW

ST_CHG ON

MAIN RESET

PRG ENA/DATA1

AVREF ON

TSEN_LED

CARD

PLLEN

SCAN OUT 2

SCAN OUT 1

SCAN OUT 0

VSS3

VDD3

(DBGP2)

(DBGP1/CLK)

(DBGP0/DATA0)

P ON

BAT_CHG_CNT

I/O

O

O

O

I

O

O

O

O

-

-

O

O

O

O

I

I

I

I

I

I

I

I

O-

I

O

O

I

O

O

I

O

O

O

O

-

-

I

O

O

O

O

Serial clock output

Backup battery charging control

Camera charging control

DC JACK detection

LCD backlight brightness adjustment

Touch sensor clock (66 kHz)

Barrier motor control +

Barrier motor control –

VDD

GND

Charge LED (L= lighting)

Self timer LED (L= lighting)

Battery temperature detection power control (L= ON)

Barrier motor PI power ON/OFF

AV JACK detection

Hot line request from ASIC

Keymatrix input

Camera charging error detection

USB power detection terminal (L= detection)

Key matrix input

Key matrix input

Key matrix input

Barrier motor detection switch

Strobo charging control

System reset (MRST)

Flash rewrite select terminal

AD VREF ON/OFF signal (L= ON)

Touch sensor LED (H= lighting)

Card detection

PLL oscillation ON/OFF

Key matrix output

Key matrix output

Key matrix output

GND

VDD

(Terminal for debugger)

(Terminal for debugger)

(Terminal for debugger)

D/D converter (digital system) ON/OFF signal

Charging currrent control

Command request input (combined with BOOT output)

Outline

– 7 –

See next page

43

44

45

46

47

48 BAT_TEMP I Battery temperature detection
49

50

51

52

53

54

55

56

57 XIN

58

59

60

61

62 TSEN_SENSE

63

64

NOT USED O

LCD BL

TH TEMP

TIME OUT

NOT USED

BAT_OFF I

SREQ

SCAN IN 4

BR PI E

RESET I

XCIN

XCOUT

VSS1 -

XOUT

VDD1

BATTERY

VMONIT

SO

SI

O

I

I

O

I

I Key matrix input (interruption)

I

I

O

I

O

- VDD

I

I

I

O

I

-

LCD backlight ON/OFF signal

Internal temperature detection

Camera charging completed detection

-

Battery OFF detection signal input

Serial communication request signal

Barrier motor PI input (interruption)

Microprocessor reset input

Clock oscillation terminal for clock (32.768 kHz)

Clock oscillation terminal for clock (32.768 kHz)

GND

Main clock oscillation terminal (4 MHz)

Main clock oscillation terminal (4 MHz)

Battery voltage detection

Main condenser charging voltage detection

Touch sensor detection

Serial data output

Serial data input

Table 5-1. 8-bit Microprocessor Port Specification

2. Internal Communication Bus

The SYA block carries out overall control of camera operation by detecting the input from the keyboard and the condition of the
camera circuits. The 8-bit microprocessor reads the signals from each sensor element as input data and outputs this data to the
camera circuits (ASIC) as operation mode setting data. Fig. 5-1 shows the internal communication between the 8-bit micropro­cessor, ASIC and SPARC lite circuits.

MAIN RESET

S. REQ

8-bit

Microprocessor

ASIC SO

ASIC SI

ASIC SCK

PLLEN

ASIC

Fig. 5-1 Internal Bus Communication System

– 8 –

3. Key Operaiton

For details of the key operation, refer to the instruction manual.

SCAN
SCAN
OUT

IN

0

0

← LEFT

123

↑ UP

→ RIGHT

↓ DOWN

4

OK

1

2

MENU

1st

-

2nd

Table 5-2. Key Operation

TELE

PW_TEST

WIDE

TEST

PLAY

PW-ON

4. Power Supply Control

The 8-bit microprocessor controls the power supply for the overall system.
The following is a description of how the power supply is turned on and off. When the battery is attached, a regulated 3.2 V
voltage is normally input to the 8-bit microprocessor (IC301) by IC302, so that clock counting and key scanning is carried out
even when the power switch is turned off, so that the camera can start up again. When the battery is removed, the 8-bit micro­processor operates in sleep mode using the backup lithium secondary battery. At this time, the 8-bit microprocessor only carries
out clock counting, and waits in standby for the battery to be attached again. When a switch is operated, the 8-bit microprocessor
supplies power to the system as required.
The 8-bit microprocessor first sets the P ON signal at pin (40) to high, and then turns on the DC/DC converter. After this, high
signals are output from pins (26) and (31) so that the ASIC is set to the active condition. Once it is completed, the ASIC returns
to the reset condition, all DC/DC converters are turned off and the power supply to the whole system is halted.

LCD

MONITOR

+15 V (L)

Power voltage

Power OFF

ASIC,

memory

3.3 V

OFF

CCD

5 V (A)

+15 V (A) etc.

OFF

8 bit

CPU

3.2 V

(ALWAYS)

32KHz OFF

Power switch ON-

Auto power OFF

CAMERA

Note) 4 MHz = Main clock operation, 32 kHz = Sub clock operation

Shutter switch ON

LCD finder

Play back

Table 5-3. Camera Mode (Battery Operation)

OFF

ON

ON

ON

ON

ON

ON

OFF

4 MHz ON

4 MHz ON

4 MHz ON

4 MHz ON

5. 16-bit A/D circuit (Audio)

This circuit converts the audio signals (analog signals) from the microphone to 16-bit digital signals.

6. 16-bit D/A circuit (Audio)

The audio signals which were converted to digial form by the 16-bit A/D circuit are temporarily to a sound buffer and then
recorded in the SSFDC card. During playback, the 16-bit D/A circuit converts these signals into analog audio signals.

– 9 –

2. DISASSEMBLY

2-1. REMOVAL OF CABINET FRONT AND CP1 BOARD

1. Three screws 1.7 x 5

2. Three screws 1.7 x 4

3. Cabinet front

4. Holder cover baria

5. Cover lens

6. FPC

7. Two screws 1.7 x 5

8. Assy motor barrier

9. Remove the solder. (speaker)

13

3

11

10. Remove the solder. (microphone)

11. Remove the solder.

12. Three FPCs

13. Screw 1.7 x 2.5

14. Screw 1.7 x 3.5

15. Connector

16. CP1 board

17. Holder motor

2

12

B

14

A

15

2

A

NOTE: Discharge a strobe capacitor

with the discharge jig (VJ8-0188) for

electric shock prevention.

B

17

16

10

9

6

8

1

a

5

b

7

4

When assembling,

tighten the screws order.

a → b

– 10 –